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authorSimon Glass <sjg@chromium.org>2014-11-14 18:18:32 -0700
committerSimon Glass <sjg@chromium.org>2014-11-25 06:34:00 -0700
commit4e7a6acac7a46cc5ab0ea7986cc9e74351eed165 (patch)
tree15ac5235dec1c99e93da8444d7070d0b0c2e180c /arch/x86/include/asm
parenta0bd851ecec0e04c5e3f224a912b2872618f77ba (diff)
x86: ivybridge: Add support for BD82x6x PCH
Add basic setup for the PCH. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/include/asm')
-rw-r--r--arch/x86/include/asm/arch-ivybridge/bd82x6x.h14
-rw-r--r--arch/x86/include/asm/arch-ivybridge/pch.h13
2 files changed, 27 insertions, 0 deletions
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
new file mode 100644
index 0000000000..e02520c208
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_BD82X6X_H
+#define _ASM_ARCH_BD82X6X_H
+
+void bd82x6x_pci_init(pci_dev_t dev);
+int bd82x6x_init_pci_devices(void);
+int bd82x6x_init(void);
+
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index c6efdb8565..aa626ad65d 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -19,6 +19,16 @@
#define SMBUS_IO_BASE 0x0400
+/* PCI Configuration Space (D30:F0): PCI2PCI */
+#define PSTS 0x06
+#define SMLT 0x1b
+#define SECSTS 0x1e
+#define INTR 0x3c
+#define BCTRL 0x3e
+#define SBR (1 << 6)
+#define SEE (1 << 1)
+#define PERE (1 << 0)
+
#define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0)
#define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0)
#define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0)
@@ -343,6 +353,9 @@
#define DMISCI_STS (1 << 9)
#define TCO2_STS 0x66
+int lpc_init(struct pci_controller *hose, pci_dev_t dev);
+void lpc_enable(pci_dev_t dev);
+
/**
* lpc_early_init() - set up LPC serial ports and other early things
*