diff options
author | Bin Meng <bmeng.cn@gmail.com> | 2018-06-12 01:26:46 -0700 |
---|---|---|
committer | Bin Meng <bmeng.cn@gmail.com> | 2018-06-13 09:50:57 +0800 |
commit | 51050ff0a239f2640467d4c2fe54e0e8679a4093 (patch) | |
tree | 538eaae07bfce8242a13905db8c0e6a6b1f1c883 /arch/x86/include/asm | |
parent | dcec5d565a20e025d843828d8424851d0271677b (diff) |
x86: irq: Support discrete PIRQ routing registers via device tree
Currently both pirq_reg_to_linkno() and pirq_linkno_to_reg() assume
consecutive PIRQ routing control registers. But this is not always
the case on some platforms. Introduce a new device tree property
intel,pirq-regmap to describe how the PIRQ routing register offset
is mapped to the link number and adjust the irq router driver to
utilize the mapping.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/include/asm')
-rw-r--r-- | arch/x86/include/asm/irq.h | 32 |
1 files changed, 8 insertions, 24 deletions
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index 9ac91f2296..e5c916070c 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -22,6 +22,11 @@ enum pirq_config { PIRQ_VIA_IBASE }; +struct pirq_regmap { + int link; + int offset; +}; + /** * Intel interrupt router control block * @@ -30,6 +35,7 @@ enum pirq_config { * @config: PIRQ_VIA_PCI or PIRQ_VIA_IBASE * @link_base: link value base number * @link_num: number of PIRQ links supported + * @has_regmap: has mapping table between PIRQ link and routing register offset * @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means * IRQ N is available to be routed * @lb_bdf: irq router's PCI bus/device/function number encoding @@ -41,6 +47,8 @@ struct irq_router { int config; u32 link_base; int link_num; + bool has_regmap; + struct pirq_regmap *regmap; u16 irq_mask; u32 bdf; u32 ibase; @@ -54,30 +62,6 @@ struct pirq_routing { int pirq; }; -/** - * pirq_reg_to_linkno() - Convert a PIRQ routing register offset to link number - * - * @reg: PIRQ routing register offset from the base address - * @base: PIRQ routing register block base address - * @return: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc) - */ -static inline int pirq_reg_to_linkno(int reg, int base) -{ - return reg - base; -} - -/** - * pirq_linkno_to_reg() - Convert a PIRQ link number to routing register offset - * - * @linkno: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc) - * @base: PIRQ routing register block base address - * @return: PIRQ routing register offset from the base address - */ -static inline int pirq_linkno_to_reg(int linkno, int base) -{ - return linkno + base; -} - #define PIRQ_BITMAP 0xdef8 #endif /* _ARCH_IRQ_H_ */ |