diff options
author | Simon Glass <sjg@chromium.org> | 2019-12-19 17:58:19 -0700 |
---|---|---|
committer | Bin Meng <bmeng.cn@gmail.com> | 2020-02-04 01:19:25 +0800 |
commit | 8c3ccb3f6d5602e47536fa83d1a8b938cae06f11 (patch) | |
tree | a77e09fd12f59af107bfd2389493e16f1ef6bfb1 /arch/x86/include/asm | |
parent | 62cbde4c4e462e5147d07cf1424492bb39e7bf94 (diff) |
x86: Update coreboot serial table struct
Since mid 2016, coreboot has additional fields in the serial struct that
it passes down to U-Boot. Add these so we are in sync.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/include/asm')
-rw-r--r-- | arch/x86/include/asm/coreboot_tables.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h index 2c54e24e02..61de0077d7 100644 --- a/arch/x86/include/asm/coreboot_tables.h +++ b/arch/x86/include/asm/coreboot_tables.h @@ -97,6 +97,25 @@ struct cb_serial { u32 type; u32 baseaddr; u32 baud; + u32 regwidth; + + /* + * Crystal or input frequency to the chip containing the UART. + * Provide the board specific details to allow the payload to + * initialize the chip containing the UART and make independent + * decisions as to which dividers to select and their values + * to eventually arrive at the desired console baud-rate. + */ + u32 input_hertz; + + /* + * UART PCI address: bus, device, function + * 1 << 31 - Valid bit, PCI UART in use + * Bus << 20 + * Device << 15 + * Function << 12 + */ + u32 uart_pci_addr; }; #define CB_TAG_CONSOLE 0x0010 |