x86: queensbay: Implement PIRQ routing

Implement Intel Queensbay platform-specific PIRQ routing support.
The chipset PIRQ routing setup is called in the arch_misc_init().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

4 files changed, 188 insertions, 2 deletions

diff --git a/arch/x86/include/asm/arch-queensbay/device.h b/arch/x86/include/asm/arch-queensbay/device.h
new file mode 100644
index 0000000000..953b48f15c
--- /dev/null
+++ b/arch/x86/include/asm/arch-queensbay/device.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _QUEENSBAY_DEVICE_H_
+#define _QUEENSBAY_DEVICE_H_
+
+#include <pci.h>
+
+/* TunnelCreek PCI Devices */
+#define TNC_HOST_BRIDGE_DEV	0
+#define TNC_HOST_BRIDGE_FUNC	0
+#define TNC_IGD_DEV		2
+#define TNC_IGD_FUNC		0
+#define TNC_SDVO_DEV		3
+#define TNC_SDVO_FUNC		0
+#define TNC_PCIE0_DEV		23
+#define TNC_PCIE0_FUNC		0
+#define TNC_PCIE1_DEV		24
+#define TNC_PCIE1_FUNC		0
+#define TNC_PCIE2_DEV		25
+#define TNC_PCIE2_FUNC		0
+#define TNC_PCIE3_DEV		26
+#define TNC_PCIE3_FUNC		0
+#define TNC_HDA_DEV		27
+#define TNC_HDA_FUNC		0
+#define TNC_LPC_DEV		31
+#define TNC_LPC_FUNC		0
+
+#define TNC_HOST_BRIDGE		\
+	PCI_BDF(0, TNC_HOST_BRIDGE_DEV, TNC_HOST_BRIDGE_FUNC)
+#define TNC_IGD			\
+	PCI_BDF(0, TNC_IGD_DEV, TNC_IGD_FUNC)
+#define TNC_SDVO		\
+	PCI_BDF(0, TNC_SDVO_DEV, TNC_SDVO_FUNC)
+#define TNC_PCIE0		\
+	PCI_BDF(0, TNC_PCIE0_DEV, TNC_PCIE0_FUNC)
+#define TNC_PCIE1		\
+	PCI_BDF(0, TNC_PCIE1_DEV, TNC_PCIE1_FUNC)
+#define TNC_PCIE2		\
+	PCI_BDF(0, TNC_PCIE2_DEV, TNC_PCIE2_FUNC)
+#define TNC_PCIE3		\
+	PCI_BDF(0, TNC_PCIE3_DEV, TNC_PCIE3_FUNC)
+#define TNC_HDA			\
+	PCI_BDF(0, TNC_HDA_DEV, TNC_HDA_FUNC)
+#define TNC_LPC			\
+	PCI_BDF(0, TNC_LPC_DEV, TNC_LPC_FUNC)
+
+/* Topcliff IOH PCI Devices */
+#define TCF_PCIE_PORT_DEV	0
+#define TCF_PCIE_PORT_FUNC	0
+
+#define TCF_DEV_0		0
+#define TCF_PKT_HUB_FUNC	0
+#define TCF_GBE_FUNC		1
+#define TCF_GPIO_FUNC		2
+
+#define TCF_DEV_2		2
+#define TCF_USB1_OHCI0_FUNC	0
+#define TCF_USB1_OHCI1_FUNC	1
+#define TCF_USB1_OHCI2_FUNC	2
+#define TCF_USB1_EHCI_FUNC	3
+#define TCF_USB_DEVICE_FUNC	4
+
+#define TCF_DEV_4		4
+#define TCF_SDIO0_FUNC		0
+#define TCF_SDIO1_FUNC		1
+
+#define TCF_DEV_6		6
+#define TCF_SATA_FUNC		0
+
+#define TCF_DEV_8		8
+#define TCF_USB2_OHCI0_FUNC	0
+#define TCF_USB2_OHCI1_FUNC	1
+#define TCF_USB2_OHCI2_FUNC	2
+#define TCF_USB2_EHCI_FUNC	3
+
+#define TCF_DEV_10		10
+#define TCF_DMA1_FUNC		0
+#define TCF_UART0_FUNC		1
+#define TCF_UART1_FUNC		2
+#define TCF_UART2_FUNC		3
+#define TCF_UART3_FUNC		4
+
+#define TCF_DEV_12		12
+#define TCF_DMA2_FUNC		0
+#define TCF_SPI_FUNC		1
+#define TCF_I2C_FUNC		2
+#define TCF_CAN_FUNC		3
+#define TCF_1588_FUNC		4
+
+#endif /* _QUEENSBAY_DEVICE_H_ */
diff --git a/arch/x86/include/asm/arch-queensbay/irq.h b/arch/x86/include/asm/arch-queensbay/irq.h
new file mode 100644
index 0000000000..e7f861623e
--- /dev/null
+++ b/arch/x86/include/asm/arch-queensbay/irq.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ARCH_IRQ_H_
+#define _ARCH_IRQ_H_
+
+enum pci_int_pin {
+	INTX,
+	INTA,
+	INTB,
+	INTC,
+	INTD
+};
+
+enum pirq_pin {
+	PIRQA,
+	PIRQB,
+	PIRQC,
+	PIRQD,
+	PIRQE,
+	PIRQF,
+	PIRQG,
+	PIRQH
+};
+
+/* PIRQ link number and value conversion */
+#define LINK_V2N(link)	(link - 0x60)
+#define LINK_N2V(link)	(link + 0x60)
+
+#define PIRQ_BITMAP	0xdee0
+
+struct irq_info;
+
+/**
+ * board_fill_irq_info() - Board-specific irq_info fill routine
+ *
+ * This fills the irq_info table for any board-specific add-in cards.
+ *
+ * @slot:	pointer to the struct irq_info that is to be filled in
+ * @return:	number of entries were written to the struct irq_info
+ */
+int board_fill_irq_info(struct irq_info *slot);
+
+/**
+ * pirq_init() - Initialize platform PIRQ routing
+ *
+ * This initializes the PIRQ routing on the platform and configures all PCI
+ * devices' interrupt line register to a working IRQ number on the 8259 PIC.
+ */
+void pirq_init(void);
+
+#endif /* _ARCH_IRQ_H_ */
diff --git a/arch/x86/include/asm/arch-queensbay/tnc.h b/arch/x86/include/asm/arch-queensbay/tnc.h
index 10ea51d0f1..ad9a6c4892 100644
--- a/arch/x86/include/asm/arch-queensbay/tnc.h
+++ b/arch/x86/include/asm/arch-queensbay/tnc.h
@@ -7,8 +7,43 @@
 #ifndef _X86_ARCH_TNC_H_
 #define _X86_ARCH_TNC_H_
 
-#include <pci.h>
+/* Memory BAR Enable */
+#define MEM_BAR_EN	0x00000001
 
-#define TNC_LPC		PCI_BDF(0, 31, 0)
+/* LPC PCI Configuration Registers */
+#define LPC_RCBA	0xf0
+
+/* Root Complex Register Block */
+struct tnc_rcba {
+	u32	rctl;
+	u32	esd;
+	u32	rsvd1[2];
+	u32	hdd;
+	u32	rsvd2;
+	u32	hdba;
+	u32	rsvd3[3129];
+	u32	d31ip;
+	u32	rsvd4[3];
+	u32	d27ip;
+	u32	rsvd5;
+	u32	d02ip;
+	u32	rsvd6;
+	u32	d26ip;
+	u32	d25ip;
+	u32	d24ip;
+	u32	d23ip;
+	u32	d03ip;
+	u32	rsvd7[3];
+	u16	d31ir;
+	u16	rsvd8[3];
+	u16	d27ir;
+	u16	d26ir;
+	u16	d25ir;
+	u16	d24ir;
+	u16	d23ir;
+	u16	rsvd9[7];
+	u16	d02ir;
+	u16	d03ir;
+};
 
 #endif /* _X86_ARCH_TNC_H_ */
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index c743efd60b..122e05425f 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -53,6 +53,8 @@ int video_bios_init(void);
 void	board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
 void	board_init_f_r(void) __attribute__ ((noreturn));
 
+int arch_misc_init(void);
+
 /* Read the time stamp counter */
 static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void)
 {