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authorSimon Glass <sjg@chromium.org>2020-04-26 09:12:53 -0600
committerBin Meng <bmeng.cn@gmail.com>2020-04-30 17:40:16 +0800
commitc793dbdb902baafeef869e3b3b16049af9c11979 (patch)
tree75e21f19c34864dcac52788f309b2747eb6c553f /arch/x86/lib/fsp2/fsp_dram.c
parent0b885bcfd9b06943bf3dc3102f95961826b04f18 (diff)
x86: fsp: Allow skipping init code when chain loading
It is useful to be able to boot the same x86 image on a device with or without a first-stage bootloader. For example, with chromebook_coral, it is helpful for testing to be able to boot the same U-Boot (complete with FSP) on bare metal and from coreboot. It allows checking of things like CPU speed, comparing registers, ACPI tables and the like. When U-Boot is not the first-stage bootloader much of this code is not needed and can break booting. Add checks for this to the FSP code. Rather than checking for the amount of available SDRAM, just use 1GB in this situation, which should be safe. Using 2GB may run into a memory hole on some SoCs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/lib/fsp2/fsp_dram.c')
-rw-r--r--arch/x86/lib/fsp2/fsp_dram.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c
index c8f2c09b6a..3869c53c5f 100644
--- a/arch/x86/lib/fsp2/fsp_dram.c
+++ b/arch/x86/lib/fsp2/fsp_dram.c
@@ -12,11 +12,18 @@
#include <asm/fsp/fsp_support.h>
#include <asm/fsp2/fsp_api.h>
#include <asm/fsp2/fsp_internal.h>
+#include <linux/sizes.h>
int dram_init(void)
{
int ret;
+ if (!ll_boot_init()) {
+ /* Use a small and safe amount of 1GB */
+ gd->ram_size = SZ_1G;
+
+ return 0;
+ }
if (spl_phase() == PHASE_SPL) {
#ifdef CONFIG_HAVE_ACPI_RESUME
bool s3wake = gd->arch.prev_sleep_state == ACPI_S3;
@@ -68,6 +75,9 @@ int dram_init(void)
ulong board_get_usable_ram_top(ulong total_size)
{
+ if (!ll_boot_init())
+ return gd->ram_size;
+
#if CONFIG_IS_ENABLED(HANDOFF)
struct spl_handoff *ho = gd->spl_handoff;