diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2016-10-09 04:14:18 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-10-12 10:58:24 +0800 |
| commit | 2d3c573ee6373f4521491f1a38e81245c3a6be57 (patch) | |
| tree | 4e75dfa2d62db43829a0092128ec054696a6c776 /arch/x86 | |
| parent | 3968398eb2d974b4840d7210d8503d7cbd8f4c48 (diff) | |
x86: coreboot: Convert to use DM coreboot video driver
This converts coreboot to use DM framebuffer driver.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/cpu/coreboot/Kconfig | 4 | ||||
| -rw-r--r-- | arch/x86/dts/bayleybay.dts | 1 | ||||
| -rw-r--r-- | arch/x86/dts/broadwell_som-6896.dts | 1 | ||||
| -rw-r--r-- | arch/x86/dts/chromebook_link.dts | 1 | ||||
| -rw-r--r-- | arch/x86/dts/chromebook_samus.dts | 1 | ||||
| -rw-r--r-- | arch/x86/dts/chromebox_panther.dts | 1 | ||||
| -rw-r--r-- | arch/x86/dts/coreboot_fb.dtsi | 5 | ||||
| -rw-r--r-- | arch/x86/dts/minnowmax.dts | 1 |
8 files changed, 11 insertions, 4 deletions
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig index e0e3c64506..4b3601f66d 100644 --- a/arch/x86/cpu/coreboot/Kconfig +++ b/arch/x86/cpu/coreboot/Kconfig @@ -8,8 +8,4 @@ config CBMEM_CONSOLE bool default y -config VIDEO_COREBOOT - bool - default y - endif diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index c8907ce44b..18b310d39e 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -14,6 +14,7 @@ /include/ "serial.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" +/include/ "coreboot_fb.dtsi" / { model = "Intel Bayley Bay"; diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts index 4bb0a34b5f..3966199085 100644 --- a/arch/x86/dts/broadwell_som-6896.dts +++ b/arch/x86/dts/broadwell_som-6896.dts @@ -4,6 +4,7 @@ /include/ "serial.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" +/include/ "coreboot_fb.dtsi" / { model = "Advantech SOM-6896"; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index fb1b31dc5e..b93234046e 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -7,6 +7,7 @@ /include/ "serial.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" +/include/ "coreboot_fb.dtsi" / { model = "Google Link"; diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts index 5dd3e57cb9..52a9ea6622 100644 --- a/arch/x86/dts/chromebook_samus.dts +++ b/arch/x86/dts/chromebook_samus.dts @@ -7,6 +7,7 @@ /include/ "serial.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" +/include/ "coreboot_fb.dtsi" / { model = "Google Samus"; diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index 480b36658e..b25c9194f3 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -4,6 +4,7 @@ /include/ "serial.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" +/include/ "coreboot_fb.dtsi" / { model = "Google Panther"; diff --git a/arch/x86/dts/coreboot_fb.dtsi b/arch/x86/dts/coreboot_fb.dtsi new file mode 100644 index 0000000000..7d72f18537 --- /dev/null +++ b/arch/x86/dts/coreboot_fb.dtsi @@ -0,0 +1,5 @@ +/ { + coreboot-fb { + compatible = "coreboot-fb"; + }; +}; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 1a8a8cc7f1..d51318bdf6 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -13,6 +13,7 @@ /include/ "serial.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" +/include/ "coreboot_fb.dtsi" / { model = "Intel Minnowboard Max"; |