diff options
author | Bin Meng <bmeng.cn@gmail.com> | 2016-05-22 01:45:31 -0700 |
---|---|---|
committer | Bin Meng <bmeng.cn@gmail.com> | 2016-05-23 15:27:41 +0800 |
commit | 3299be2479f9878dd3bb484f2b8f1ef7c0a20fb4 (patch) | |
tree | 7cbd1da873afdbf011dc968e951f3b976b774e66 /arch/x86 | |
parent | 0ac8d5e552c5642d97ce71658ecebb273d259221 (diff) |
x86: Don't touch IA32_APIC_BASE MSR on Intel Quark
Intel Quark processor core provides an integrated Local APIC but
does not support the IA32_APIC_BASE MSR. As a result, the Local
APIC is always globally enabled and the Local APIC base address
is fixed at 0xfee00000. Attempting to access the IA32_APIC_BASE
MSR causes a general protection fault.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86')
-rw-r--r-- | arch/x86/cpu/lapic.c | 28 |
1 files changed, 16 insertions, 12 deletions
diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c index 30d23130eb..dbb32c4447 100644 --- a/arch/x86/cpu/lapic.c +++ b/arch/x86/cpu/lapic.c @@ -65,23 +65,27 @@ void lapic_write(unsigned long reg, unsigned long v) void enable_lapic(void) { - msr_t msr; - - msr = msr_read(MSR_IA32_APICBASE); - msr.hi &= 0xffffff00; - msr.lo |= MSR_IA32_APICBASE_ENABLE; - msr.lo &= ~MSR_IA32_APICBASE_BASE; - msr.lo |= LAPIC_DEFAULT_BASE; - msr_write(MSR_IA32_APICBASE, msr); + if (!IS_ENABLED(CONFIG_INTEL_QUARK)) { + msr_t msr; + + msr = msr_read(MSR_IA32_APICBASE); + msr.hi &= 0xffffff00; + msr.lo |= MSR_IA32_APICBASE_ENABLE; + msr.lo &= ~MSR_IA32_APICBASE_BASE; + msr.lo |= LAPIC_DEFAULT_BASE; + msr_write(MSR_IA32_APICBASE, msr); + } } void disable_lapic(void) { - msr_t msr; + if (!IS_ENABLED(CONFIG_INTEL_QUARK)) { + msr_t msr; - msr = msr_read(MSR_IA32_APICBASE); - msr.lo &= ~MSR_IA32_APICBASE_ENABLE; - msr_write(MSR_IA32_APICBASE, msr); + msr = msr_read(MSR_IA32_APICBASE); + msr.lo &= ~MSR_IA32_APICBASE_ENABLE; + msr_write(MSR_IA32_APICBASE, msr); + } } unsigned long lapicid(void) |