diff options
| author | Simon Glass <sjg@chromium.org> | 2019-12-06 21:42:12 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2019-12-15 11:44:15 +0800 |
| commit | 42791100180943c0f776a325843c66540e9595e7 (patch) | |
| tree | df632b0cb2d5939b0ab4a6681f2ac8dfd4fd0a2e /arch/x86 | |
| parent | ea4e97a511483dfd61b1417f935a7ed97e5565f9 (diff) | |
x86: Set up the MTRR for SDRAM
Set up MTRRs for the FSP SDRAM regions to improve performance.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/lib/fsp/fsp_dram.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 987cb4f8f3..9ce0ddf0d3 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -9,6 +9,7 @@ #include <asm/fsp/fsp_support.h> #include <asm/e820.h> #include <asm/mrccache.h> +#include <asm/mtrr.h> #include <asm/post.h> DECLARE_GLOBAL_DATA_PTR; @@ -61,6 +62,8 @@ int dram_init_banksize(void) gd->bd->bi_dram[bank].start = res_desc->phys_start; gd->bd->bi_dram[bank].size = res_desc->len; + mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start, + res_desc->len); log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start, gd->bd->bi_dram[bank].size); } @@ -69,6 +72,8 @@ int dram_init_banksize(void) gd->bd->bi_dram[0].start = 0; gd->bd->bi_dram[0].size = low_end; + mtrr_add_request(MTRR_TYPE_WRBACK, 0, low_end); + return 0; } |