diff options
| author | Simon Glass <sjg@chromium.org> | 2019-12-06 21:42:28 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2019-12-15 11:44:19 +0800 |
| commit | dda8e3efa0a46551370135e99daafbdda7b71d23 (patch) | |
| tree | 11e085fc3d478bd5a2d7dec4b6a06368a044dcd0 /arch/x86 | |
| parent | b75617b035a7eee94669e7dbd83921dd66dcb61e (diff) | |
x86: Update .dtsi file for FSP2
Include the IFWI section and the FSP-M binary. The FSP-T binary is not
currently used, as CAR is set up manually.
Also drop the FSP binary as this relates only to FSP1.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/dts/u-boot.dtsi | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 850fe3ac11..14e3c13072 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -100,12 +100,42 @@ offset = <CONFIG_X86_MRC_ADDR>; }; #endif -#ifdef CONFIG_HAVE_FSP +#ifdef CONFIG_FSP_VERSION1 intel-fsp { filename = CONFIG_FSP_FILE; offset = <CONFIG_FSP_ADDR>; }; #endif +#ifdef CONFIG_FSP_VERSION2 + intel-descriptor { + filename = CONFIG_FLASH_DESCRIPTOR_FILE; + }; + intel-ifwi { + filename = CONFIG_IFWI_INPUT_FILE; + convert-fit; + + section { + size = <0x8000>; + ifwi-replace; + ifwi-subpart = "IBBP"; + ifwi-entry = "IBBL"; + u-boot-tpl { + }; + x86-start16-tpl { + offset = <0x7800>; + }; + x86-reset16-tpl { + offset = <0x7ff0>; + }; + }; + }; + intel-fsp-m { + filename = CONFIG_FSP_FILE_M; + }; + intel-fsp-s { + filename = CONFIG_FSP_FILE_S; + }; +#endif #ifdef CONFIG_HAVE_CMC intel-cmc { filename = CONFIG_CMC_FILE; |