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| author | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2018-09-07 19:02:04 +0200 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2018-09-22 21:02:03 +0200 |
| commit | b838586086af3278bcaead3720c7a18813cf4619 (patch) | |
| tree | 879cf10b808b1cc2f4aa708d44cbba717089ad6c /arch/xtensa/include/asm/regs.h | |
| parent | 2f85c2be21dfee1e8ac1f8fb9759be7108233e85 (diff) | |
MIPS: cache: optimise changing of k0 CCA mode
Changing the Cache Coherency Algorithm (CCA) for kernel mode
requires executing from KSEG1. Thus do a jump from KSEG0 to KSEG1
before changing the CCA mode. Jump back to KSEG0 afterwards.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'arch/xtensa/include/asm/regs.h')
0 files changed, 0 insertions, 0 deletions