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authorAngelo Durgehello <angelo.dureghello@timesys.com>2020-01-26 19:31:22 +0100
committerTom Rini <trini@konsulko.com>2020-01-26 13:36:14 -0500
commitc05b38df477a50c3918b50c5f986592411785859 (patch)
tree31bd0ca8c12fe0e7a5be0d296ba2ffc154cee69a /arch/xtensa
parent080dbc64fcbc9e17ed424778e51b4f3db152ec1e (diff)
common: fix regression on block cache init
m68k needs block cache list initialized after relocation. Other architectures must not be involved. Fixing regression related to: commit 1526bcce0f7285087621e16e6720636d01839da8 ("common: add blkcache init") Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
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