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authorTom Rini <trini@konsulko.com>2018-01-17 13:48:35 -0500
committerTom Rini <trini@konsulko.com>2018-01-17 13:48:35 -0500
commit086ebcd40e9bf8efc520f1b177fd8e3cc0e506fa (patch)
treee25d93fda4ce7cd672e7340f60015ec6fe2de27f /arch
parent3759df0c0810636b31fe64c56868aa831514e509 (diff)
parent2eb2dbd4577898bf289e911b2286df3f2363af6e (diff)
Merge git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig12
-rw-r--r--arch/arm/cpu/armv8/Kconfig5
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/cpu.c4
-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/fsl-ls1012a-2g5rdb.dts43
5 files changed, 61 insertions, 4 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 001ece3cf1..9dc542625e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -968,6 +968,18 @@ config TARGET_LS1012ARDB
development platform that supports the QorIQ LS1012A
Layerscape Architecture processor.
+config TARGET_LS1012A2G5RDB
+ bool "Support ls1012a2g5rdb"
+ select ARCH_LS1012A
+ select ARM64
+ select BOARD_LATE_INIT
+ imply SCSI
+ help
+ Support for Freescale LS1012A2G5RDB platform.
+ The LS1012A 2G5 Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
config TARGET_LS1012AFRDM
bool "Support ls1012afrdm"
select ARCH_LS1012A
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 12aba9d4e9..3a0e129d2e 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -85,11 +85,12 @@ endmenu
config PSCI_RESET
bool "Use PSCI for reset and shutdown"
default y
- depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
+ depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \
!TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
- !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
+ !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
!TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
!TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
+ !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
!TARGET_LS2081ARDB && \
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 1e0030cbfb..70a6070935 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -578,7 +578,7 @@ int timer_init(void)
#ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
#endif
-#ifdef CONFIG_ARCH_LS2080A
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
u32 svr_dev_id;
#endif
@@ -597,7 +597,7 @@ int timer_init(void)
out_le32(cltbenr, 0xf);
#endif
-#ifdef CONFIG_ARCH_LS2080A
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
/*
* In certain Layerscape SoCs, the clock for each core's
* has an enable bit in the PMU Physical Core Time Base Enable
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e22b52cbb6..26b2a528e6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -209,6 +209,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
+ fsl-ls1012a-2g5rdb.dtb \
fsl-ls1012a-frdm.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
diff --git a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
new file mode 100644
index 0000000000..dbe01dd7f6
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
@@ -0,0 +1,43 @@
+/*
+ * NXP ls1012a 2G5RDB board device tree source
+ *
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A 2G5RDB Board";
+
+ aliases {
+ spi0 = &qspi;
+ };
+
+ chosen {
+ stdout-path = &duart0;
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fl128s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&duart0 {
+ status = "okay";
+};