diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-05-24 21:13:57 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-05-26 00:35:26 +0900 |
| commit | 0bd20207ab2d874842161cab37c213310d785b24 (patch) | |
| tree | da95cd1c624176e51bd12a9b709e968afd89205f /arch | |
| parent | fc15b9beed05dec6cc092c265042381a0eadb0e9 (diff) | |
ARM: uniphier: disable cache in SPL of PH1-LD20
The Boot ROM has enabled D-cache and MMU setting DDR memory area
as Normal Memory in its page table. Disable D-cache and MMU
before jumping to U-Boot proper.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-uniphier/init/init-ld20.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/init/init-ld20.c b/arch/arm/mach-uniphier/init/init-ld20.c index 660ad457dc..7f66053e1f 100644 --- a/arch/arm/mach-uniphier/init/init-ld20.c +++ b/arch/arm/mach-uniphier/init/init-ld20.c @@ -51,5 +51,7 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd) led_puts("L5"); + dcache_disable(); + return 0; } |