diff options
author | Akshay Saraswat <akshay.s@samsung.com> | 2015-02-20 13:27:13 +0530 |
---|---|---|
committer | Minkyu Kang <mk7.kang@samsung.com> | 2015-02-28 18:03:46 +0900 |
commit | 0c08baf05317c723214ba6e0ba89e4a4d9e0d3f1 (patch) | |
tree | 755bd123bb6f55b38a96b2b744d1f323b31d617b /arch | |
parent | ac0d98cd557e0939bd0f10ff68e2e648a74bbea6 (diff) |
Exynos542x: Add workaround for ARM errata 798870
This patch adds workaround for ARM errata 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."
Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/include/asm/armv7.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index a13da23cf1..a2040b776d 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -69,6 +69,22 @@ #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) +/* + * Workaround for ARM errata # 798870 + * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been + * stalled for 1024 cycles to verify that its hazard condition still exists. + */ +static inline void v7_enable_l2_hazard_detect(void) +{ + uint32_t val; + + /* L2ACTLR[7]: Enable hazard detect timeout */ + asm volatile ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(val)); + val |= (1 << 7); + asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(val)); +} + +void v7_en_l2_hazard_detect(void); void v7_outer_cache_enable(void); void v7_outer_cache_disable(void); void v7_outer_cache_flush_all(void); |