Merge branch 'master' of git://git.denx.de/u-boot-sunxi

18 files changed, 1455 insertions, 175 deletions

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 82dbf764e4..3b6ae47329 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -13,6 +13,7 @@ obj-y	+= clock.o
 obj-y	+= pinmux.o
 obj-$(CONFIG_MACH_SUN6I)	+= prcm.o
 obj-$(CONFIG_MACH_SUN8I)	+= prcm.o
+obj-$(CONFIG_MACH_SUN6I)	+= p2wi.o
 obj-$(CONFIG_MACH_SUN4I)	+= clock_sun4i.o
 obj-$(CONFIG_MACH_SUN5I)	+= clock_sun4i.o
 obj-$(CONFIG_MACH_SUN6I)	+= clock_sun6i.o
@@ -27,9 +28,10 @@ endif
 endif
 
 ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_MACH_SUN4I)	+= dram.o
-obj-$(CONFIG_MACH_SUN5I)	+= dram.o
-obj-$(CONFIG_MACH_SUN7I)	+= dram.o
+obj-$(CONFIG_MACH_SUN4I)	+= dram_sun4i.o
+obj-$(CONFIG_MACH_SUN5I)	+= dram_sun4i.o
+obj-$(CONFIG_MACH_SUN6I)	+= dram_sun6i.o
+obj-$(CONFIG_MACH_SUN7I)	+= dram_sun4i.o
 ifdef CONFIG_SPL_FEL
 obj-y	+= start.o
 endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 6c812fc6e9..9b3e80c24a 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -114,6 +114,11 @@ void reset_cpu(ulong addr)
 /* do some early init */
 void s_init(void)
 {
+#if defined CONFIG_SPL_BUILD && defined CONFIG_MACH_SUN6I
+	/* Magic (undocmented) value taken from boot0, without this DRAM
+	 * access gets messed up (seems cache related) */
+	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+#endif
 #if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
 		defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
 	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 1eae9767d0..16ab6f3729 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -16,6 +16,33 @@
 #include <asm/arch/prcm.h>
 #include <asm/arch/sys_proto.h>
 
+#ifdef CONFIG_SPL_BUILD
+void clock_init_safe(void)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	struct sunxi_prcm_reg * const prcm =
+		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+	/* Set PLL ldo voltage without this PLL6 does not work properly */
+	clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
+			PRCM_PLL_CTRL_LDO_KEY);
+	clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
+		PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
+		PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
+	clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
+
+	clock_set_pll1(408000000);
+
+	writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
+
+	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+
+	writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
+	writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
+}
+#endif
+
 void clock_init_uart(void)
 {
 	struct sunxi_ccm_reg *const ccm =
@@ -65,6 +92,56 @@ int clock_twi_onoff(int port, int state)
 	return 0;
 }
 
+#ifdef CONFIG_SPL_BUILD
+void clock_set_pll1(unsigned int clk)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	int k = 1;
+	int m = 1;
+
+	if (clk > 1152000000) {
+		k = 2;
+	} else if (clk > 768000000) {
+		k = 3;
+		m = 2;
+	}
+
+	/* Switch to 24MHz clock while changing PLL1 */
+	writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+	       ATB_DIV_2 << ATB_DIV_SHIFT |
+	       CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+	       &ccm->cpu_axi_cfg);
+
+	/* PLL1 rate = 24000000 * n * k / m */
+	writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_MAGIC |
+	       CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
+	       CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
+	sdelay(200);
+
+	/* Switch CPU to PLL1 */
+	writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+	       ATB_DIV_2 << ATB_DIV_SHIFT |
+	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+	       &ccm->cpu_axi_cfg);
+}
+#endif
+
+void clock_set_pll5(unsigned int clk)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	const int k = 2;
+	const int m = 1;
+
+	/* PLL5 rate = 24000000 * n * k / m */
+	writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
+	       CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
+	       CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
+
+	udelay(5500);
+}
+
 unsigned int clock_get_pll6(void)
 {
 	struct sunxi_ccm_reg *const ccm =
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c
index dc9fdb930b..dc9fdb930b 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
new file mode 100644
index 0000000000..10a62416d2
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
@@ -0,0 +1,435 @@
+/*
+ * Sun6i platform dram controller init.
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/prcm.h>
+
+/* DRAM clk & zq defaults, maybe turn these into Kconfig options ? */
+#define DRAM_CLK_DEFAULT 312000000
+#define DRAM_ZQ_DEFAULT 0x78
+
+struct dram_sun6i_para {
+	u8 bus_width;
+	u8 chan;
+	u8 rank;
+	u8 rows;
+	u16 page_size;
+};
+
+/*
+ * Wait up to 1s for value to be set in given part of reg.
+ */
+static void await_completion(u32 *reg, u32 mask, u32 val)
+{
+	unsigned long tmo = timer_get_us() + 1000000;
+
+	while ((readl(reg) & mask) != val) {
+		if (timer_get_us() > tmo)
+			panic("Timeout initialising DRAM\n");
+	}
+}
+
+static void mctl_sys_init(void)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	const int dram_clk_div = 2;
+
+	clock_set_pll5(DRAM_CLK_DEFAULT * dram_clk_div);
+
+	clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK,
+		CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST |
+		CCM_DRAMCLK_CFG_UPD);
+	await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
+
+	writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg);
+
+	/* deassert mctl reset */
+	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+
+	/* enable mctl clock */
+	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+}
+
+static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para)
+{
+	struct sunxi_mctl_phy_reg *mctl_phy;
+
+	if (ch_index == 0)
+		mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+	else
+		mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
+
+	/* disable + reset dlls */
+	writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr);
+	writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr);
+	writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr);
+	if (para->bus_width == 32) {
+		writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr);
+		writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr);
+	}
+	udelay(2);
+
+	/* enable + reset dlls */
+	writel(0, &mctl_phy->acdllcr);
+	writel(0, &mctl_phy->dx0dllcr);
+	writel(0, &mctl_phy->dx1dllcr);
+	if (para->bus_width == 32) {
+		writel(0, &mctl_phy->dx2dllcr);
+		writel(0, &mctl_phy->dx3dllcr);
+	}
+	udelay(22);
+
+	/* enable and release reset of dlls */
+	writel(MCTL_DLLCR_NRESET, &mctl_phy->acdllcr);
+	writel(MCTL_DLLCR_NRESET, &mctl_phy->dx0dllcr);
+	writel(MCTL_DLLCR_NRESET, &mctl_phy->dx1dllcr);
+	if (para->bus_width == 32) {
+		writel(MCTL_DLLCR_NRESET, &mctl_phy->dx2dllcr);
+		writel(MCTL_DLLCR_NRESET, &mctl_phy->dx3dllcr);
+	}
+	udelay(22);
+}
+
+static bool mctl_rank_detect(u32 *gsr0, int rank)
+{
+	const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank;
+	const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank;
+
+	await_completion(gsr0, done, done);
+	await_completion(gsr0 + 0x10, done, done);
+
+	return !(readl(gsr0) & err) && !(readl(gsr0 + 0x10) & err);
+}
+
+static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para)
+{
+	struct sunxi_mctl_com_reg * const mctl_com =
+		(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+	struct sunxi_mctl_ctl_reg *mctl_ctl;
+	struct sunxi_mctl_phy_reg *mctl_phy;
+
+	if (ch_index == 0) {
+		mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+		mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+	} else {
+		mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE;
+		mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
+	}
+
+	writel(MCTL_MCMD_NOP, &mctl_ctl->mcmd);
+	await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0);
+
+	/* PHY initialization */
+	writel(MCTL_PGCR, &mctl_phy->pgcr);
+	writel(MCTL_MR0, &mctl_phy->mr0);
+	writel(MCTL_MR1, &mctl_phy->mr1);
+	writel(MCTL_MR2, &mctl_phy->mr2);
+	writel(MCTL_MR3, &mctl_phy->mr3);
+
+	writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST,
+	       &mctl_phy->ptr0);
+	/* Unknown magic performed by boot0 */
+	if ((readl(SUNXI_RTC_BASE + 0x20c) & 3) == 2)
+		setbits_le32(&mctl_phy->ptr0, 1 << 18);
+
+	writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1);
+	writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2);
+
+	writel((MCTL_TCCD << 31) | (MCTL_TRC << 25) | (MCTL_TRRD << 21) |
+	       (MCTL_TRAS << 16) | (MCTL_TRCD << 12) | (MCTL_TRP << 8) |
+	       (MCTL_TWTR << 5) | (MCTL_TRTP << 2) | (MCTL_TMRD << 0),
+	       &mctl_phy->dtpr0);
+
+	writel((MCTL_TDQSCKMAX << 27) | (MCTL_TDQSCK << 24) |
+	       (MCTL_TRFC << 16) | (MCTL_TRTODT << 11) |
+	       ((MCTL_TMOD - 12) << 9) | (MCTL_TFAW << 3) | (0 << 2) |
+	       (MCTL_TAOND << 0), &mctl_phy->dtpr1);
+
+	writel((MCTL_TDLLK << 19) | (MCTL_TCKE << 15) | (MCTL_TXPDLL << 10) |
+	       (MCTL_TEXSR << 0), &mctl_phy->dtpr2);
+
+	writel(1, &mctl_ctl->dfitphyupdtype0);
+	writel(MCTL_DCR_DDR3, &mctl_phy->dcr);
+	writel(MCTL_DSGCR, &mctl_phy->dsgcr);
+	writel(MCTL_DXCCR, &mctl_phy->dxccr);
+	writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx0gcr);
+	writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx1gcr);
+	writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx2gcr);
+	writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx3gcr);
+
+	await_completion(&mctl_phy->pgsr, 0x03, 0x03);
+
+	writel(DRAM_ZQ_DEFAULT, &mctl_phy->zq0cr1);
+
+	setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
+	writel(MCTL_PIR_STEP1, &mctl_phy->pir);
+	udelay(10);
+	await_completion(&mctl_phy->pgsr, 0x1f, 0x1f);
+
+	/* rank detect */
+	if (!mctl_rank_detect(&mctl_phy->dx0gsr0, 1)) {
+		para->rank = 1;
+		clrbits_le32(&mctl_phy->pgcr, MCTL_PGCR_RANK);
+	}
+
+	/*
+	 * channel detect, check channel 1 dx0 and dx1 have rank 0, if not
+	 * assume nothing is connected to channel 1.
+	 */
+	if (ch_index == 1 && !mctl_rank_detect(&mctl_phy->dx0gsr0, 0)) {
+		para->chan = 1;
+		clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
+		return;
+	}
+
+	/* bus width detect, if dx2 and dx3 don't have rank 0, assume 16 bit */
+	if (!mctl_rank_detect(&mctl_phy->dx2gsr0, 0)) {
+		para->bus_width = 16;
+		para->page_size = 2048;
+		setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE);
+		setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE);
+		clrbits_le32(&mctl_phy->dx2gcr, MCTL_DX_GCR_EN);
+		clrbits_le32(&mctl_phy->dx3gcr, MCTL_DX_GCR_EN);
+	}
+
+	setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
+	writel(MCTL_PIR_STEP2, &mctl_phy->pir);
+	udelay(10);
+	await_completion(&mctl_phy->pgsr, 0x11, 0x11);
+
+	if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK)
+		panic("Training error initialising DRAM\n");
+
+	/* Move to configure state */
+	writel(MCTL_SCTL_CONFIG, &mctl_ctl->sctl);
+	await_completion(&mctl_ctl->sstat, 0x07, 0x01);
+
+	/* Set number of clks per micro-second */
+	writel(DRAM_CLK_DEFAULT / 1000000, &mctl_ctl->togcnt1u);
+	/* Set number of clks per 100 nano-seconds */
+	writel(DRAM_CLK_DEFAULT / 10000000, &mctl_ctl->togcnt100n);
+	/* Set memory timing registers */
+	writel(MCTL_TREFI, &mctl_ctl->trefi);
+	writel(MCTL_TMRD, &mctl_ctl->tmrd);
+	writel(MCTL_TRFC, &mctl_ctl->trfc);
+	writel((MCTL_TPREA << 16) | MCTL_TRP, &mctl_ctl->trp);
+	writel(MCTL_TRTW, &mctl_ctl->trtw);
+	writel(MCTL_TAL, &mctl_ctl->tal);
+	writel(MCTL_TCL, &mctl_ctl->tcl);
+	writel(MCTL_TCWL, &mctl_ctl->tcwl);
+	writel(MCTL_TRAS, &mctl_ctl->tras);
+	writel(MCTL_TRC, &mctl_ctl->trc);
+	writel(MCTL_TRCD, &mctl_ctl->trcd);
+	writel(MCTL_TRRD, &mctl_ctl->trrd);
+	writel(MCTL_TRTP, &mctl_ctl->trtp);
+	writel(MCTL_TWR, &mctl_ctl->twr);
+	writel(MCTL_TWTR, &mctl_ctl->twtr);
+	writel(MCTL_TEXSR, &mctl_ctl->texsr);
+	writel(MCTL_TXP, &mctl_ctl->txp);
+	writel(MCTL_TXPDLL, &mctl_ctl->txpdll);
+	writel(MCTL_TZQCS, &mctl_ctl->tzqcs);
+	writel(MCTL_TZQCSI, &mctl_ctl->tzqcsi);
+	writel(MCTL_TDQS, &mctl_ctl->tdqs);
+	writel(MCTL_TCKSRE, &mctl_ctl->tcksre);
+	writel(MCTL_TCKSRX, &mctl_ctl->tcksrx);
+	writel(MCTL_TCKE, &mctl_ctl->tcke);
+	writel(MCTL_TMOD, &mctl_ctl->tmod);
+	writel(MCTL_TRSTL, &mctl_ctl->trstl);
+	writel(MCTL_TZQCL, &mctl_ctl->tzqcl);
+	writel(MCTL_TMRR, &mctl_ctl->tmrr);
+	writel(MCTL_TCKESR, &mctl_ctl->tckesr);
+	writel(MCTL_TDPD, &mctl_ctl->tdpd);
+
+	/* Unknown magic performed by boot0 */
+	setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3);
+	clrbits_le32(&mctl_ctl->dfiodtcfg1, 0x1f);
+
+	/* Select 16/32-bits mode for MCTL */
+	if (para->bus_width == 16)
+		setbits_le32(&mctl_ctl->ppcfg, 1);
+
+	/* Set DFI timing registers */
+	writel(MCTL_TCWL, &mctl_ctl->dfitphywrl);
+	writel(MCTL_TCL - 1, &mctl_ctl->dfitrdden);
+	writel(MCTL_DFITPHYRDL, &mctl_ctl->dfitphyrdl);
+	writel(MCTL_DFISTCFG0, &mctl_ctl->dfistcfg0);
+
+	writel(MCTL_MCFG_DDR3, &mctl_ctl->mcfg);
+
+	/* DFI update configuration register */
+	writel(MCTL_DFIUPDCFG_UPD, &mctl_ctl->dfiupdcfg);
+
+	/* Move to access state */
+	writel(MCTL_SCTL_ACCESS, &mctl_ctl->sctl);
+	await_completion(&mctl_ctl->sstat, 0x07, 0x03);
+}
+
+static void mctl_com_init(struct dram_sun6i_para *para)
+{
+	struct sunxi_mctl_com_reg * const mctl_com =
+		(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+	struct sunxi_mctl_phy_reg * const mctl_phy1 =
+		(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
+	struct sunxi_prcm_reg * const prcm =
+		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+	writel(MCTL_CR_UNKNOWN | MCTL_CR_CHANNEL(para->chan) | MCTL_CR_DDR3 |
+	       ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) |
+	       MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
+	       MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr);
+
+	/* Unknown magic performed by boot0 */
+	setbits_le32(&mctl_com->dbgcr, (1 << 6));
+
+	if (para->chan == 1) {
+		/* Shutdown channel 1 */
+		setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE);
+		setbits_le32(&mctl_phy1->dxccr, MCTL_DXCCR_DISABLE);
+		clrbits_le32(&mctl_phy1->dsgcr, MCTL_DSGCR_ENABLE);
+		/*
+		 * CH0 ?? this is what boot0 does. Leave as is until we can
+		 * confirm this.
+		 */
+		setbits_le32(&prcm->vdd_sys_pwroff,
+			     PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF);
+	}
+}
+
+static void mctl_port_cfg(void)
+{
+	struct sunxi_mctl_com_reg * const mctl_com =
+		(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	/* enable DRAM AXI clock for CPU access */
+	setbits_le32(&ccm->axi_gate, 1 << AXI_GATE_OFFSET_DRAM);
+
+	/* Bunch of magic writes performed by boot0 */
+	writel(0x00400302, &mctl_com->rmcr[0]);
+	writel(0x01000307, &mctl_com->rmcr[1]);
+	writel(0x00400302, &mctl_com->rmcr[2]);
+	writel(0x01000307, &mctl_com->rmcr[3]);
+	writel(0x01000307, &mctl_com->rmcr[4]);
+	writel(0x01000303, &mctl_com->rmcr[6]);
+	writel(0x01000303, &mctl_com->mmcr[0]);
+	writel(0x00400310, &mctl_com->mmcr[1]);
+	writel(0x01000307, &mctl_com->mmcr[2]);
+	writel(0x01000303, &mctl_com->mmcr[3]);
+	writel(0x01800303, &mctl_com->mmcr[4]);
+	writel(0x01800303, &mctl_com->mmcr[5]);
+	writel(0x01800303, &mctl_com->mmcr[6]);
+	writel(0x01800303, &mctl_com->mmcr[7]);
+	writel(0x01000303, &mctl_com->mmcr[8]);
+	writel(0x00000002, &mctl_com->mmcr[15]);
+	writel(0x00000310, &mctl_com->mbagcr[0]);
+	writel(0x00400310, &mctl_com->mbagcr[1]);
+	writel(0x00400310, &mctl_com->mbagcr[2]);
+	writel(0x00000307, &mctl_com->mbagcr[3]);
+	writel(0x00000317, &mctl_com->mbagcr[4]);
+	writel(0x00000307, &mctl_com->mbagcr[5]);
+}
+
+static bool mctl_mem_matches(u32 offset)
+{
+	const int match_count = 64;
+	int i, matches = 0;
+
+	for (i = 0; i < match_count; i++) {
+		if (readl(CONFIG_SYS_SDRAM_BASE + i * 4) ==
+		    readl(CONFIG_SYS_SDRAM_BASE + offset + i * 4))
+			matches++;
+	}
+
+	return matches == match_count;
+}
+
+unsigned long sunxi_dram_init(void)
+{
+	struct sunxi_mctl_com_reg * const mctl_com =
+		(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+	u32 offset;
+	int bank, bus, columns;
+
+	/* Set initial parameters, these get modified by the autodetect code */
+	struct dram_sun6i_para para = {
+		.bus_width = 32,
+		.chan = 2,
+		.rank = 2,
+		.page_size = 4096,
+		.rows = 16,
+	};
+
+	mctl_sys_init();
+
+	mctl_dll_init(0, &para);
+	mctl_dll_init(1, &para);
+
+	setbits_le32(&mctl_com->ccr,
+		     MCTL_CCR_MASTER_CLK_EN |
+		     MCTL_CCR_CH0_CLK_EN |
+		     MCTL_CCR_CH1_CLK_EN);
+
+	mctl_channel_init(0, &para);
+	mctl_channel_init(1, &para);
+	mctl_com_init(&para);
+	mctl_port_cfg();
+
+	/*
+	 * Change to 1 ch / sequence / 8192 byte pages / 16 rows /
+	 * 8 bit banks / 1 rank mode.
+	 */
+	clrsetbits_le32(&mctl_com->cr,
+		MCTL_CR_CHANNEL_MASK | MCTL_CR_PAGE_SIZE_MASK |
+		    MCTL_CR_ROW_MASK | MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
+		MCTL_CR_CHANNEL(1) | MCTL_CR_SEQUENCE |
+		    MCTL_CR_PAGE_SIZE(8192) | MCTL_CR_ROW(16) |
+		    MCTL_CR_BANK(1) | MCTL_CR_RANK(1));
+
+	/* Detect and set page size */
+	for (columns = 7; columns < 20; columns++) {
+		if (mctl_mem_matches(1 << columns))
+			break;
+	}
+	bus = (para.bus_width == 32) ? 2 : 1;
+	columns -= bus;
+	para.page_size = (1 << columns) * (bus << 1);
+	clrsetbits_le32(&mctl_com->cr, MCTL_CR_PAGE_SIZE_MASK,
+			MCTL_CR_PAGE_SIZE(para.page_size));
+
+	/* Detect and set rows */
+	for (para.rows = 11; para.rows < 16; para.rows++) {
+		offset = 1 << (para.rows + columns + bus);
+		if (mctl_mem_matches(offset))
+			break;
+	}
+	clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
+			MCTL_CR_ROW(para.rows));
+
+	/* Detect bank size */
+	offset = 1 << (para.rows + columns + bus + 2);
+	bank = mctl_mem_matches(offset) ? 0 : 1;
+
+	/* Restore interleave, chan and rank values, set bank size */
+	clrsetbits_le32(&mctl_com->cr,
+			MCTL_CR_CHANNEL_MASK | MCTL_CR_SEQUENCE |
+			    MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
+			MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) |
+			    MCTL_CR_RANK(para.rank));
+
+	return 1 << (para.rank + para.rows + bank + columns + para.chan + bus);
+}
diff --git a/arch/arm/cpu/armv7/sunxi/p2wi.c b/arch/arm/cpu/armv7/sunxi/p2wi.c
new file mode 100644
index 0000000000..48613bd0ea
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/p2wi.c
@@ -0,0 +1,117 @@
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/p2wi.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+void p2wi_init(void)
+{
+	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+
+	/* Enable p2wi and PIO clk, and de-assert their resets */
+	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
+
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUNXI_GPL0_R_P2WI_SCK);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUNXI_GPL1_R_P2WI_SDA);
+
+	/* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
+	writel(P2WI_CTRL_RESET, &p2wi->ctrl);
+	sdelay(0x100);
+	writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
+	       &p2wi->cc);
+}
+
+int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
+{
+	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+	unsigned long tmo = timer_get_us() + 1000000;
+
+	writel(P2WI_PM_DEV_ADDR(slave_addr) |
+	       P2WI_PM_CTRL_ADDR(ctrl_reg) |
+	       P2WI_PM_INIT_DATA(init_data) |
+	       P2WI_PM_INIT_SEND,
+	       &p2wi->pm);
+
+	while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) {
+		if (timer_get_us() > tmo)
+			return -ETIME;
+	}
+
+	return 0;
+}
+
+static int p2wi_await_trans(void)
+{
+	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+	unsigned long tmo = timer_get_us() + 1000000;
+	int ret;
+	u8 reg;
+
+	while (1) {
+		reg = readl(&p2wi->status);
+		if (reg & P2WI_STAT_TRANS_ERR) {
+			ret = -EIO;
+			break;
+		}
+		if (reg & P2WI_STAT_TRANS_DONE) {
+			ret = 0;
+			break;
+		}
+		if (timer_get_us() > tmo) {
+			ret = -ETIME;
+			break;
+		}
+	}
+	writel(reg, &p2wi->status); /* Clear status bits */
+	return ret;
+}
+
+int p2wi_read(const u8 addr, u8 *data)
+{
+	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+	int ret;
+
+	writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
+	writel(P2WI_DATA_NUM_BYTES(1) |
+	       P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
+	writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
+	writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
+
+	ret = p2wi_await_trans();
+
+	*data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
+	return ret;
+}
+
+int p2wi_write(const u8 addr, u8 data)
+{
+	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+
+	writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
+	writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
+	writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
+	writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
+	writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
+
+	return p2wi_await_trans();
+}
diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index 0084c811f3..b9ea78b84e 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -87,8 +87,8 @@ psci_cpu_on:
 	str	r2, [r0]
 	dsb
 
-	movw	r0, #(SUNXI_CPUCFG_BASE & 0xffff)
-	movt	r0, #(SUNXI_CPUCFG_BASE >> 16)
+	movw	r0, #(SUN7I_CPUCFG_BASE & 0xffff)
+	movt	r0, #(SUN7I_CPUCFG_BASE >> 16)
 
 	@ CPU mask
 	and	r1, r1, #3	@ only care about first cluster
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index 42382a8ae2..b40c16b6e7 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -25,6 +25,7 @@
 int clock_init(void);
 int clock_twi_onoff(int port, int state);
 void clock_set_pll1(unsigned int hz);
+void clock_set_pll5(unsigned int hz);
 unsigned int clock_get_pll5p(void);
 unsigned int clock_get_pll6(void);
 void clock_init_safe(void);
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 90af8e2506..9dca800d78 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -262,5 +262,8 @@ struct sunxi_ccm_reg {
 #define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
 #define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
 #define CCM_USB_CTRL_PHYGATE (0x1 << 8)
+/* These 2 are sun6i only, define them as 0 on sun4i */
+#define CCM_USB_CTRL_PHY1_CLK 0
+#define CCM_USB_CTRL_PHY2_CLK 0
 
 #endif /* _SUNXI_CLOCK_SUN4I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 1397b35889..e16a7647ed 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -170,7 +170,17 @@ struct sunxi_ccm_reg {
 #define CPU_CLK_SRC_OSC24M		1
 #define CPU_CLK_SRC_PLL1		2
 
-#define PLL1_CFG_DEFAULT		0x90011b21
+#define CCM_PLL1_CTRL_M(n)		((((n) - 1) & 0x3) << 0)
+#define CCM_PLL1_CTRL_K(n)		((((n) - 1) & 0x3) << 4)
+#define CCM_PLL1_CTRL_N(n)		((((n) - 1) & 0x1f) << 8)
+#define CCM_PLL1_CTRL_MAGIC		(0x1 << 16)
+#define CCM_PLL1_CTRL_EN		(0x1 << 31)
+
+#define CCM_PLL5_CTRL_M(n)		((((n) - 1) & 0x3) << 0)
+#define CCM_PLL5_CTRL_K(n)		((((n) - 1) & 0x3) << 4)
+#define CCM_PLL5_CTRL_N(n)		((((n) - 1) & 0x1f) << 8)
+#define CCM_PLL5_CTRL_UPD		(0x1 << 20)
+#define CCM_PLL5_CTRL_EN		(0x1 << 31)
 
 #define PLL6_CFG_DEFAULT		0x90041811
 
@@ -179,6 +189,15 @@ struct sunxi_ccm_reg {
 #define CCM_PLL6_CTRL_K_SHIFT		4
 #define CCM_PLL6_CTRL_K_MASK		(0x3 << CCM_PLL6_CTRL_K_SHIFT)
 
+#define AHB1_ABP1_DIV_DEFAULT		0x00002020
+
+#define AXI_GATE_OFFSET_DRAM		0
+
+#define AHB_GATE_OFFSET_USB_OHCI1	30
+#define AHB_GATE_OFFSET_USB_OHCI0	29
+#define AHB_GATE_OFFSET_USB_EHCI1	27
+#define AHB_GATE_OFFSET_USB_EHCI0	26
+#define AHB_GATE_OFFSET_MCTL		14
 #define AHB_GATE_OFFSET_MMC3		11
 #define AHB_GATE_OFFSET_MMC2		10
 #define AHB_GATE_OFFSET_MMC1		9
@@ -190,6 +209,23 @@ struct sunxi_ccm_reg {
 
 #define CCM_MMC_CTRL_ENABLE (0x1 << 31)
 
+#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
+#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
+/* There is no global phy clk gate on sun6i, define as 0 */
+#define CCM_USB_CTRL_PHYGATE 0
+#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
+#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
+
+#define MDFS_CLK_DEFAULT		0x81000002 /* PLL6 / 3 */
+
+#define CCM_DRAMCLK_CFG_DIV0(x)		((x - 1) << 8)
+#define CCM_DRAMCLK_CFG_DIV0_MASK	(0xf << 8)
+#define CCM_DRAMCLK_CFG_UPD		(0x1 << 16)
+#define CCM_DRAMCLK_CFG_RST		(0x1 << 31)
+
+#define MBUS_CLK_DEFAULT		0x81000001 /* PLL6 / 2 */
+
+#define AHB_RESET_OFFSET_MCTL		14
 #define AHB_RESET_OFFSET_MMC3		11
 #define AHB_RESET_OFFSET_MMC2		10
 #define AHB_RESET_OFFSET_MMC1		9
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index 0de79a0d50..bdee89e87d 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -37,16 +37,24 @@
 #define SUNXI_MMC1_BASE			0x01c10000
 #define SUNXI_MMC2_BASE			0x01c11000
 #define SUNXI_MMC3_BASE			0x01c12000
+#ifndef CONFIG_MACH_SUN6I
 #define SUNXI_USB0_BASE			0x01c13000
 #define SUNXI_USB1_BASE			0x01c14000
+#endif
 #define SUNXI_SS_BASE			0x01c15000
 #define SUNXI_HDMI_BASE			0x01c16000
 #define SUNXI_SPI2_BASE			0x01c17000
 #define SUNXI_SATA_BASE			0x01c18000
+#ifndef CONFIG_MACH_SUN6I
 #define SUNXI_PATA_BASE			0x01c19000
 #define SUNXI_ACE_BASE			0x01c1a000
 #define SUNXI_TVE1_BASE			0x01c1b000
 #define SUNXI_USB2_BASE			0x01c1c000
+#else
+#define SUNXI_USB0_BASE			0x01c19000
+#define SUNXI_USB1_BASE			0x01c1a000
+#define SUNXI_USB2_BASE			0x01c1b000
+#endif
 #define SUNXI_CSI1_BASE			0x01c1d000
 #define SUNXI_TZASC_BASE		0x01c1e000
 #define SUNXI_SPI3_BASE			0x01c1f000
@@ -70,7 +78,7 @@
 
 #define SUNXI_TP_BASE			0x01c25000
 #define SUNXI_PMU_BASE			0x01c25400
-#define SUNXI_CPUCFG_BASE              0x01c25c00
+#define SUN7I_CPUCFG_BASE              0x01c25c00
 
 #define SUNXI_UART0_BASE		0x01c28000
 #define SUNXI_UART1_BASE		0x01c28400
@@ -96,9 +104,10 @@
 #define SUNXI_GMAC_BASE			0x01c50000
 
 #define SUNXI_DRAM_COM_BASE		0x01c62000
-#define SUNXI_DRAM_CTL_BASE		0x01c63000
-#define SUNXI_DRAM_PHY_CH1_BASE		0x01c65000
-#define SUNXI_DRAM_PHY_CH2_BASE		0x01c66000
+#define SUNXI_DRAM_CTL0_BASE		0x01c63000
+#define SUNXI_DRAM_CTL1_BASE		0x01c64000
+#define SUNXI_DRAM_PHY0_BASE		0x01c65000
+#define SUNXI_DRAM_PHY1_BASE		0x01c66000
 
 /* module sram */
 #define SUNXI_SRAM_C_BASE		0x01d00000
@@ -110,7 +119,9 @@
 #define SUNXI_MP_BASE			0x01e80000
 #define SUNXI_AVG_BASE			0x01ea0000
 
+#define SUNXI_RTC_BASE			0x01f00000
 #define SUNXI_PRCM_BASE			0x01f01400
+#define SUN6I_CPUCFG_BASE		0x01f01c00
 #define SUNXI_R_UART_BASE		0x01f02800
 #define SUNXI_R_PIO_BASE		0x01f02c00
 #define SUNXI_P2WI_BASE			0x01f03400
diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h b/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
new file mode 100644
index 0000000000..e2a29cb181
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
@@ -0,0 +1,67 @@
+/*
+ * Sunxi A31 CPUCFG register definition.
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPUCFG_H
+#define _SUNXI_CPUCFG_H
+
+#ifndef __ASSEMBLY__
+
+struct sunxi_cpucfg_reg {
+	u8 res0[0x40];		/* 0x000 */
+	u32 cpu0_rst;		/* 0x040 */
+	u32 cpu0_ctrl;		/* 0x044 */
+	u32 cpu0_status;	/* 0x048 */
+	u8 res1[0x34];		/* 0x04c */
+	u32 cpu1_rst;		/* 0x080 */
+	u32 cpu1_ctrl;		/* 0x084 */
+	u32 cpu1_status;	/* 0x088 */
+	u8 res2[0x34];		/* 0x08c */
+	u32 cpu2_rst;		/* 0x0c0 */
+	u32 cpu2_ctrl;		/* 0x0c4 */
+	u32 cpu2_status;	/* 0x0c8 */
+	u8 res3[0x34];		/* 0x0cc */
+	u32 cpu3_rst;		/* 0x100 */
+	u32 cpu3_ctrl;		/* 0x104 */
+	u32 cpu3_status;	/* 0x108 */
+	u8 res4[0x78];		/* 0x10c */
+	u32 gen_ctrl;		/* 0x184 */
+	u32 l2_status;		/* 0x188 */
+	u8 res5[0x4];		/* 0x18c */
+	u32 event_in;		/* 0x190 */
+	u8 res6[0xc];		/* 0x194 */
+	u32 super_standy_flag;	/* 0x1a0 */
+	u32 priv0;		/* 0x1a4 */
+	u32 priv1;		/* 0x1a8 */
+	u8 res7[0x54];		/* 0x1ac */
+	u32 idle_cnt0_low;	/* 0x200 */
+	u32 idle_cnt0_high;	/* 0x204 */
+	u32 idle_cnt0_ctrl;	/* 0x208 */
+	u8 res8[0x4];		/* 0x20c */
+	u32 idle_cnt1_low;	/* 0x210 */
+	u32 idle_cnt1_high;	/* 0x214 */
+	u32 idle_cnt1_ctrl;	/* 0x218 */
+	u8 res9[0x4];		/* 0x21c */
+	u32 idle_cnt2_low;	/* 0x220 */
+	u32 idle_cnt2_high;	/* 0x224 */
+	u32 idle_cnt2_ctrl;	/* 0x228 */
+	u8 res10[0x4];		/* 0x22c */
+	u32 idle_cnt3_low;	/* 0x230 */
+	u32 idle_cnt3_high;	/* 0x234 */
+	u32 idle_cnt3_ctrl;	/* 0x238 */
+	u8 res11[0x4];		/* 0x23c */
+	u32 idle_cnt4_low;	/* 0x240 */
+	u32 idle_cnt4_high;	/* 0x244 */
+	u32 idle_cnt4_ctrl;	/* 0x248 */
+	u8 res12[0x34];		/* 0x24c */
+	u32 cnt64_ctrl;		/* 0x280 */
+	u32 cnt64_low;		/* 0x284 */
+	u32 cnt64_high;		/* 0x288 */
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* _SUNXI_CPUCFG_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h
index 1945f75441..9072e68229 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -14,172 +14,13 @@
 
 #include <linux/types.h>
 
-struct sunxi_dram_reg {
-	u32 ccr;		/* 0x00 controller configuration register */
-	u32 dcr;		/* 0x04 dram configuration register */
-	u32 iocr;		/* 0x08 i/o configuration register */
-	u32 csr;		/* 0x0c controller status register */
-	u32 drr;		/* 0x10 dram refresh register */
-	u32 tpr0;		/* 0x14 dram timing parameters register 0 */
-	u32 tpr1;		/* 0x18 dram timing parameters register 1 */
-	u32 tpr2;		/* 0x1c dram timing parameters register 2 */
-	u32 gdllcr;		/* 0x20 global dll control register */
-	u8 res0[0x28];
-	u32 rslr0;		/* 0x4c rank system latency register */
-	u32 rslr1;		/* 0x50 rank system latency register */
-	u8 res1[0x8];
-	u32 rdgr0;		/* 0x5c rank dqs gating register */
-	u32 rdgr1;		/* 0x60 rank dqs gating register */
-	u8 res2[0x34];
-	u32 odtcr;		/* 0x98 odt configuration register */
-	u32 dtr0;		/* 0x9c data training register 0 */
-	u32 dtr1;		/* 0xa0 data training register 1 */
-	u32 dtar;		/* 0xa4 data training address register */
-	u32 zqcr0;		/* 0xa8 zq control register 0 */
-	u32 zqcr1;		/* 0xac zq control register 1 */
-	u32 zqsr;		/* 0xb0 zq status register */
-	u32 idcr;		/* 0xb4 initializaton delay configure reg */
-	u8 res3[0x138];
-	u32 mr;			/* 0x1f0 mode register */
-	u32 emr;		/* 0x1f4 extended mode register */
-	u32 emr2;		/* 0x1f8 extended mode register */
-	u32 emr3;		/* 0x1fc extended mode register */
-	u32 dllctr;		/* 0x200 dll control register */
-	u32 dllcr[5];		/* 0x204 dll control register 0(byte 0) */
-	/* 0x208 dll control register 1(byte 1) */
-	/* 0x20c dll control register 2(byte 2) */
-	/* 0x210 dll control register 3(byte 3) */
-	/* 0x214 dll control register 4(byte 4) */
-	u32 dqtr0;		/* 0x218 dq timing register */
-	u32 dqtr1;		/* 0x21c dq timing register */
-	u32 dqtr2;		/* 0x220 dq timing register */
-	u32 dqtr3;		/* 0x224 dq timing register */
-	u32 dqstr;		/* 0x228 dqs timing register */
-	u32 dqsbtr;		/* 0x22c dqsb timing register */
-	u32 mcr;		/* 0x230 mode configure register */
-	u8 res[0x8];
-	u32 ppwrsctl;		/* 0x23c pad power save control */
-	u32 apr;		/* 0x240 arbiter period register */
-	u32 pldtr;		/* 0x244 priority level data threshold reg */
-	u8 res5[0x8];
-	u32 hpcr[32];		/* 0x250 host port configure register */
-	u8 res6[0x10];
-	u32 csel;		/* 0x2e0 controller select register */
-};
-
-struct dram_para {
-	u32 clock;
-	u32 mbus_clock;
-	u32 type;
-	u32 rank_num;
-	u32 density;
-	u32 io_width;
-	u32 bus_width;
-	u32 cas;
-	u32 zq;
-	u32 odt_en;
-	u32 size;
-	u32 tpr0;
-	u32 tpr1;
-	u32 tpr2;
-	u32 tpr3;
-	u32 tpr4;
-	u32 tpr5;
-	u32 emr1;
-	u32 emr2;
-	u32 emr3;
-	u32 dqs_gating_delay;
-	u32 active_windowing;
-};
-
-#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5)
-#define DRAM_CCR_DQS_GATE (0x1 << 14)
-#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17)
-#define DRAM_CCR_ITM_OFF (0x1 << 28)
-#define DRAM_CCR_DATA_TRAINING (0x1 << 30)
-#define DRAM_CCR_INIT (0x1 << 31)
-
-#define DRAM_MEMORY_TYPE_DDR1 1
-#define DRAM_MEMORY_TYPE_DDR2 2
-#define DRAM_MEMORY_TYPE_DDR3 3
-#define DRAM_MEMORY_TYPE_LPDDR2 4
-#define DRAM_MEMORY_TYPE_LPDDR 5
-#define DRAM_DCR_TYPE (0x1 << 0)
-#define DRAM_DCR_TYPE_DDR2 0x0
-#define DRAM_DCR_TYPE_DDR3 0x1
-#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1)
-#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3)
-#define DRAM_DCR_IO_WIDTH_8BIT 0x0
-#define DRAM_DCR_IO_WIDTH_16BIT 0x1
-#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3)
-#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7)
-#define DRAM_DCR_CHIP_DENSITY_256M 0x0
-#define DRAM_DCR_CHIP_DENSITY_512M 0x1
-#define DRAM_DCR_CHIP_DENSITY_1024M 0x2
-#define DRAM_DCR_CHIP_DENSITY_2048M 0x3
-#define DRAM_DCR_CHIP_DENSITY_4096M 0x4
-#define DRAM_DCR_CHIP_DENSITY_8192M 0x5
-#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6)
-#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7)
-#define DRAM_DCR_BUS_WIDTH_32BIT 0x3
-#define DRAM_DCR_BUS_WIDTH_16BIT 0x1
-#define DRAM_DCR_BUS_WIDTH_8BIT 0x0
-#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10)
-#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3)
-#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12)
-#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13)
-#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3)
-#define DRAM_DCR_MODE_SEQ 0x0
-#define DRAM_DCR_MODE_INTERLEAVE 0x1
-
-#define DRAM_CSR_DTERR  (0x1 << 20)
-#define DRAM_CSR_DTIERR (0x1 << 21)
-#define DRAM_CSR_FAILED (DRAM_CSR_DTERR | DRAM_CSR_DTIERR)
-
-#define DRAM_DRR_TRFC(n) ((n) & 0xff)
-#define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8)
-#define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24)
-
-#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0)
-#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3)
-#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2)
-#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3)
-#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4)
-#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3)
-#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6)
-#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3)
-#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8)
-#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7)
-#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11)
-#define DRAM_MCR_RESET (0x1 << 12)
-#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13)
-#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3)
-#define DRAM_MCR_DCLK_OUT (0x1 << 16)
-
-#define DRAM_DLLCR_NRESET (0x1 << 30)
-#define DRAM_DLLCR_DISABLE (0x1 << 31)
-
-#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20)
-#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff)
-#define DRAM_ZQCR0_ZCAL (1 << 31) /* Starts ZQ calibration when set to 1 */
-#define DRAM_ZQCR0_ZDEN (1 << 28) /* Uses ZDATA instead of doing calibration */
-
-#define DRAM_ZQSR_ZDONE (1 << 31) /* ZQ calibration completion flag */
-
-#define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0)
-#define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3)
-
-#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0)
-#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7)
-#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4)
-#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7)
-#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9)
-#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7)
-#define DRAM_MR_POWER_DOWN (0x1 << 12)
-
-#define DRAM_CSEL_MAGIC 0x16237495
+/* dram regs definition */
+#if defined(CONFIG_MACH_SUN6I)
+#include <asm/arch/dram_sun6i.h>
+#else
+#include <asm/arch/dram_sun4i.h>
+#endif
 
 unsigned long sunxi_dram_init(void);
-unsigned long dramc_init(struct dram_para *para);
 
 #endif /* _SUNXI_DRAM_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h
new file mode 100644
index 0000000000..6c1ec5be86
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h
@@ -0,0 +1,182 @@
+/*
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Sunxi platform dram register definition.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_DRAM_SUN4I_H
+#define _SUNXI_DRAM_SUN4I_H
+
+struct sunxi_dram_reg {
+	u32 ccr;		/* 0x00 controller configuration register */
+	u32 dcr;		/* 0x04 dram configuration register */
+	u32 iocr;		/* 0x08 i/o configuration register */
+	u32 csr;		/* 0x0c controller status register */
+	u32 drr;		/* 0x10 dram refresh register */
+	u32 tpr0;		/* 0x14 dram timing parameters register 0 */
+	u32 tpr1;		/* 0x18 dram timing parameters register 1 */
+	u32 tpr2;		/* 0x1c dram timing parameters register 2 */
+	u32 gdllcr;		/* 0x20 global dll control register */
+	u8 res0[0x28];
+	u32 rslr0;		/* 0x4c rank system latency register */
+	u32 rslr1;		/* 0x50 rank system latency register */
+	u8 res1[0x8];
+	u32 rdgr0;		/* 0x5c rank dqs gating register */
+	u32 rdgr1;		/* 0x60 rank dqs gating register */
+	u8 res2[0x34];
+	u32 odtcr;		/* 0x98 odt configuration register */
+	u32 dtr0;		/* 0x9c data training register 0 */
+	u32 dtr1;		/* 0xa0 data training register 1 */
+	u32 dtar;		/* 0xa4 data training address register */
+	u32 zqcr0;		/* 0xa8 zq control register 0 */
+	u32 zqcr1;		/* 0xac zq control register 1 */
+	u32 zqsr;		/* 0xb0 zq status register */
+	u32 idcr;		/* 0xb4 initializaton delay configure reg */
+	u8 res3[0x138];
+	u32 mr;			/* 0x1f0 mode register */
+	u32 emr;		/* 0x1f4 extended mode register */
+	u32 emr2;		/* 0x1f8 extended mode register */
+	u32 emr3;		/* 0x1fc extended mode register */
+	u32 dllctr;		/* 0x200 dll control register */
+	u32 dllcr[5];		/* 0x204 dll control register 0(byte 0) */
+	/* 0x208 dll control register 1(byte 1) */
+	/* 0x20c dll control register 2(byte 2) */
+	/* 0x210 dll control register 3(byte 3) */
+	/* 0x214 dll control register 4(byte 4) */
+	u32 dqtr0;		/* 0x218 dq timing register */
+	u32 dqtr1;		/* 0x21c dq timing register */
+	u32 dqtr2;		/* 0x220 dq timing register */
+	u32 dqtr3;		/* 0x224 dq timing register */
+	u32 dqstr;		/* 0x228 dqs timing register */
+	u32 dqsbtr;		/* 0x22c dqsb timing register */
+	u32 mcr;		/* 0x230 mode configure register */
+	u8 res[0x8];
+	u32 ppwrsctl;		/* 0x23c pad power save control */
+	u32 apr;		/* 0x240 arbiter period register */
+	u32 pldtr;		/* 0x244 priority level data threshold reg */
+	u8 res5[0x8];
+	u32 hpcr[32];		/* 0x250 host port configure register */
+	u8 res6[0x10];
+	u32 csel;		/* 0x2e0 controller select register */
+};
+
+struct dram_para {
+	u32 clock;
+	u32 mbus_clock;
+	u32 type;
+	u32 rank_num;
+	u32 density;
+	u32 io_width;
+	u32 bus_width;
+	u32 cas;
+	u32 zq;
+	u32 odt_en;
+	u32 size;
+	u32 tpr0;
+	u32 tpr1;
+	u32 tpr2;
+	u32 tpr3;
+	u32 tpr4;
+	u32 tpr5;
+	u32 emr1;
+	u32 emr2;
+	u32 emr3;
+	u32 dqs_gating_delay;
+	u32 active_windowing;
+};
+
+#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5)
+#define DRAM_CCR_DQS_GATE (0x1 << 14)
+#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17)
+#define DRAM_CCR_ITM_OFF (0x1 << 28)
+#define DRAM_CCR_DATA_TRAINING (0x1 << 30)
+#define DRAM_CCR_INIT (0x1 << 31)
+
+#define DRAM_MEMORY_TYPE_DDR1 1
+#define DRAM_MEMORY_TYPE_DDR2 2
+#define DRAM_MEMORY_TYPE_DDR3 3
+#define DRAM_MEMORY_TYPE_LPDDR2 4
+#define DRAM_MEMORY_TYPE_LPDDR 5
+#define DRAM_DCR_TYPE (0x1 << 0)
+#define DRAM_DCR_TYPE_DDR2 0x0
+#define DRAM_DCR_TYPE_DDR3 0x1
+#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1)
+#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3)
+#define DRAM_DCR_IO_WIDTH_8BIT 0x0
+#define DRAM_DCR_IO_WIDTH_16BIT 0x1
+#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3)
+#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7)
+#define DRAM_DCR_CHIP_DENSITY_256M 0x0
+#define DRAM_DCR_CHIP_DENSITY_512M 0x1
+#define DRAM_DCR_CHIP_DENSITY_1024M 0x2
+#define DRAM_DCR_CHIP_DENSITY_2048M 0x3
+#define DRAM_DCR_CHIP_DENSITY_4096M 0x4
+#define DRAM_DCR_CHIP_DENSITY_8192M 0x5
+#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6)
+#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7)
+#define DRAM_DCR_BUS_WIDTH_32BIT 0x3
+#define DRAM_DCR_BUS_WIDTH_16BIT 0x1
+#define DRAM_DCR_BUS_WIDTH_8BIT 0x0
+#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10)
+#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3)
+#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12)
+#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13)
+#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3)
+#define DRAM_DCR_MODE_SEQ 0x0
+#define DRAM_DCR_MODE_INTERLEAVE 0x1
+
+#define DRAM_CSR_DTERR  (0x1 << 20)
+#define DRAM_CSR_DTIERR (0x1 << 21)
+#define DRAM_CSR_FAILED (DRAM_CSR_DTERR | DRAM_CSR_DTIERR)
+
+#define DRAM_DRR_TRFC(n) ((n) & 0xff)
+#define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8)
+#define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24)
+
+#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0)
+#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3)
+#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2)
+#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3)
+#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4)
+#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3)
+#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6)
+#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3)
+#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8)
+#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7)
+#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11)
+#define DRAM_MCR_RESET (0x1 << 12)
+#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13)
+#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3)
+#define DRAM_MCR_DCLK_OUT (0x1 << 16)
+
+#define DRAM_DLLCR_NRESET (0x1 << 30)
+#define DRAM_DLLCR_DISABLE (0x1 << 31)
+
+#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20)
+#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff)
+#define DRAM_ZQCR0_ZCAL (1 << 31) /* Starts ZQ calibration when set to 1 */
+#define DRAM_ZQCR0_ZDEN (1 << 28) /* Uses ZDATA instead of doing calibration */
+
+#define DRAM_ZQSR_ZDONE (1 << 31) /* ZQ calibration completion flag */
+
+#define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0)
+#define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3)
+
+#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0)
+#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7)
+#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4)
+#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7)
+#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9)
+#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7)
+#define DRAM_MR_POWER_DOWN (0x1 << 12)
+
+#define DRAM_CSEL_MAGIC 0x16237495
+
+unsigned long dramc_init(struct dram_para *para);
+
+#endif /* _SUNXI_DRAM_SUN4I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun6i.h b/arch/arm/include/asm/arch-sunxi/dram_sun6i.h
new file mode 100644
index 0000000000..9b0b310c2e
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun6i.h
@@ -0,0 +1,359 @@
+/*
+ * Sun6i platform dram controller register and constant defines
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_DRAM_SUN6I_H
+#define _SUNXI_DRAM_SUN6I_H
+
+struct sunxi_mctl_com_reg {
+	u32 cr;			/* 0x00 */
+	u32 ccr;		/* 0x04 controller configuration register */
+	u32 dbgcr;		/* 0x08 */
+	u32 dbgcr1;		/* 0x0c */
+	u32 rmcr[8];		/* 0x10 */
+	u32 mmcr[16];		/* 0x30 */
+	u32 mbagcr[6];		/* 0x70 */
+	u32 maer;		/* 0x88 */
+	u8 res0[0x14];		/* 0x8c */
+	u32 mdfscr;		/* 0x100 */
+	u32 mdfsmer;		/* 0x104 */
+	u32 mdfsmrmr;		/* 0x108 */
+	u32 mdfstr0;		/* 0x10c */
+	u32 mdfstr1;		/* 0x110 */
+	u32 mdfstr2;		/* 0x114 */
+	u32 mdfstr3;		/* 0x118 */
+	u32 mdfsgcr;		/* 0x11c */
+	u8 res1[0x1c];		/* 0x120 */
+	u32 mdfsivr;		/* 0x13c */
+	u8 res2[0x0c];		/* 0x140 */
+	u32 mdfstcr;		/* 0x14c */
+};
+
+struct sunxi_mctl_ctl_reg {
+	u8 res0[0x04];		/* 0x00 */
+	u32 sctl;		/* 0x04 */
+	u32 sstat;		/* 0x08 */
+	u8 res1[0x34];		/* 0x0c */
+	u32 mcmd;		/* 0x40 */
+	u8 res2[0x08];		/* 0x44 */
+	u32 cmdstat;		/* 0x4c */
+	u32 cmdstaten;		/* 0x50 */
+	u8 res3[0x0c];		/* 0x54 */
+	u32 mrrcfg0;		/* 0x60 */
+	u32 mrrstat0;		/* 0x64 */
+	u32 mrrstat1;		/* 0x68 */
+	u8 res4[0x10];		/* 0x6c */
+	u32 mcfg1;		/* 0x7c */
+	u32 mcfg;		/* 0x80 */
+	u32 ppcfg;		/* 0x84 */
+	u32 mstat;		/* 0x88 */
+	u32 lp2zqcfg;		/* 0x8c */
+	u8 res5[0x04];		/* 0x90 */
+	u32 dtustat;		/* 0x94 */
+	u32 dtuna;		/* 0x98 */
+	u32 dtune;		/* 0x9c */
+	u32 dtuprd0;		/* 0xa0 */
+	u32 dtuprd1;		/* 0xa4 */
+	u32 dtuprd2;		/* 0xa8 */
+	u32 dtuprd3;		/* 0xac */
+	u32 dtuawdt;		/* 0xb0 */
+	u8 res6[0x0c];		/* 0xb4 */
+	u32 togcnt1u;		/* 0xc0 */
+	u8 res7[0x08];		/* 0xc4 */
+	u32 togcnt100n;		/* 0xcc */
+	u32 trefi;		/* 0xd0 */
+	u32 tmrd;		/* 0xd4 */
+	u32 trfc;		/* 0xd8 */
+	u32 trp;		/* 0xdc */
+	u32 trtw;		/* 0xe0 */
+	u32 tal;		/* 0xe4 */
+	u32 tcl;		/* 0xe8 */
+	u32 tcwl;		/* 0xec */
+	u32 tras;		/* 0xf0 */
+	u32 trc;		/* 0xf4 */
+	u32 trcd;		/* 0xf8 */
+	u32 trrd;		/* 0xfc */
+	u32 trtp;		/* 0x100 */
+	u32 twr;		/* 0x104 */
+	u32 twtr;		/* 0x108 */
+	u32 texsr;		/* 0x10c */
+	u32 txp;		/* 0x110 */
+	u32 txpdll;		/* 0x114 */
+	u32 tzqcs;		/* 0x118 */
+	u32 tzqcsi;		/* 0x11c */
+	u32 tdqs;		/* 0x120 */
+	u32 tcksre;		/* 0x124 */
+	u32 tcksrx;		/* 0x128 */
+	u32 tcke;		/* 0x12c */
+	u32 tmod;		/* 0x130 */
+	u32 trstl;		/* 0x134 */
+	u32 tzqcl;		/* 0x138 */
+	u32 tmrr;		/* 0x13c */
+	u32 tckesr;		/* 0x140 */
+	u32 tdpd;		/* 0x144 */
+	u8 res8[0xb8];		/* 0x148 */
+	u32 dtuwactl;		/* 0x200 */
+	u32 dturactl;		/* 0x204 */
+	u32 dtucfg;		/* 0x208 */
+	u32 dtuectl;		/* 0x20c */
+	u32 dtuwd0;		/* 0x210 */
+	u32 dtuwd1;		/* 0x214 */
+	u32 dtuwd2;		/* 0x218 */
+	u32 dtuwd3;		/* 0x21c */
+	u32 dtuwdm;		/* 0x220 */
+	u32 dturd0;		/* 0x224 */
+	u32 dturd1;		/* 0x228 */
+	u32 dturd2;		/* 0x22c */
+	u32 dturd3;		/* 0x230 */
+	u32 dtulfsrwd;		/* 0x234 */
+	u32 dtulfsrrd;		/* 0x238 */
+	u32 dtueaf;		/* 0x23c */
+	u32 dfitctldly;		/* 0x240 */
+	u32 dfiodtcfg;		/* 0x244 */
+	u32 dfiodtcfg1;		/* 0x248 */
+	u32 dfiodtrmap;		/* 0x24c */
+	u32 dfitphywrd;		/* 0x250 */
+	u32 dfitphywrl;		/* 0x254 */
+	u8 res9[0x08];		/* 0x258 */
+	u32 dfitrdden;		/* 0x260 */
+	u32 dfitphyrdl;		/* 0x264 */
+	u8 res10[0x08];		/* 0x268 */
+	u32 dfitphyupdtype0;	/* 0x270 */
+	u32 dfitphyupdtype1;	/* 0x274 */
+	u32 dfitphyupdtype2;	/* 0x278 */
+	u32 dfitphyupdtype3;	/* 0x27c */
+	u32 dfitctrlupdmin;	/* 0x280 */
+	u32 dfitctrlupdmax;	/* 0x284 */
+	u32 dfitctrlupddly;	/* 0x288 */
+	u8 res11[4];		/* 0x28c */
+	u32 dfiupdcfg;		/* 0x290 */
+	u32 dfitrefmski;	/* 0x294 */
+	u32 dfitcrlupdi;	/* 0x298 */
+	u8 res12[0x10];		/* 0x29c */
+	u32 dfitrcfg0;		/* 0x2ac */
+	u32 dfitrstat0;		/* 0x2b0 */
+	u32 dfitrwrlvlen;	/* 0x2b4 */
+	u32 dfitrrdlvlen;	/* 0x2b8 */
+	u32 dfitrrdlvlgateen;	/* 0x2bc */
+	u8 res13[0x04];		/* 0x2c0 */
+	u32 dfistcfg0;		/* 0x2c4 */
+	u32 dfistcfg1;		/* 0x2c8 */
+	u8 res14[0x04];		/* 0x2cc */
+	u32 dfitdramclken;	/* 0x2d0 */
+	u32 dfitdramclkdis;	/* 0x2d4 */
+	u8 res15[0x18];		/* 0x2d8 */
+	u32 dfilpcfg0;		/* 0x2f0 */
+};
+
+struct sunxi_mctl_phy_reg {
+	u8 res0[0x04];		/* 0x00 */
+	u32 pir;		/* 0x04 */
+	u32 pgcr;		/* 0x08 phy general configuration register */
+	u32 pgsr;		/* 0x0c */
+	u32 dllgcr;		/* 0x10 */
+	u32 acdllcr;		/* 0x14 */
+	u32 ptr0;		/* 0x18 */
+	u32 ptr1;		/* 0x1c */
+	u32 ptr2;		/* 0x20 */
+	u32 aciocr;		/* 0x24 */
+	u32 dxccr;		/* 0x28 DATX8 common configuration register */
+	u32 dsgcr;		/* 0x2c dram system general config register */
+	u32 dcr;		/* 0x30 */
+	u32 dtpr0;		/* 0x34 dram timing parameters register 0 */
+	u32 dtpr1;		/* 0x38 dram timing parameters register 1 */
+	u32 dtpr2;		/* 0x3c dram timing parameters register 2 */
+	u32 mr0;		/* 0x40 mode register 0 */
+	u32 mr1;		/* 0x44 mode register 1 */
+	u32 mr2;		/* 0x48 mode register 2 */
+	u32 mr3;		/* 0x4c mode register 3 */
+	u32 odtcr;		/* 0x50 */
+	u32 dtar;		/* 0x54 data training address register */
+	u32 dtd0;		/* 0x58 */
+	u32 dtd1;		/* 0x5c */
+	u8 res1[0x60];		/* 0x60 */
+	u32 dcuar;		/* 0xc0 */
+	u32 dcudr;		/* 0xc4 */
+	u32 dcurr;		/* 0xc8 */
+	u32 dculr;		/* 0xcc */
+	u32 dcugcr;		/* 0xd0 */
+	u32 dcutpr;		/* 0xd4 */
+	u32 dcusr0;		/* 0xd8 */
+	u32 dcusr1;		/* 0xdc */
+	u8 res2[0x20];		/* 0xe0 */
+	u32 bistrr;		/* 0x100 */
+	u32 bistmskr0;		/* 0x104 */
+	u32 bistmskr1;		/* 0x108 */
+	u32 bistwcr;		/* 0x10c */
+	u32 bistlsr;		/* 0x110 */
+	u32 bistar0;		/* 0x114 */
+	u32 bistar1;		/* 0x118 */
+	u32 bistar2;		/* 0x11c */
+	u32 bistupdr;		/* 0x120 */
+	u32 bistgsr;		/* 0x124 */
+	u32 bistwer;		/* 0x128 */
+	u32 bistber0;		/* 0x12c */
+	u32 bistber1;		/* 0x130 */
+	u32 bistber2;		/* 0x134 */
+	u32 bistwcsr;		/* 0x138 */
+	u32 bistfwr0;		/* 0x13c */
+	u32 bistfwr1;		/* 0x140 */
+	u8 res3[0x3c];		/* 0x144 */
+	u32 zq0cr0;		/* 0x180 zq 0 control register 0 */
+	u32 zq0cr1;		/* 0x184 zq 0 control register 1 */
+	u32 zq0sr0;		/* 0x188 zq 0 status register 0 */
+	u32 zq0sr1;		/* 0x18c zq 0 status register 1 */
+	u8 res4[0x30];		/* 0x190 */
+	u32 dx0gcr;		/* 0x1c0 */
+	u32 dx0gsr0;		/* 0x1c4 */
+	u32 dx0gsr1;		/* 0x1c8 */
+	u32 dx0dllcr;		/* 0x1cc */
+	u32 dx0dqtr;		/* 0x1d0 */
+	u32 dx0dqstr;		/* 0x1d4 */
+	u8 res5[0x28];		/* 0x1d8 */
+	u32 dx1gcr;		/* 0x200 */
+	u32 dx1gsr0;		/* 0x204 */
+	u32 dx1gsr1;		/* 0x208 */
+	u32 dx1dllcr;		/* 0x20c */
+	u32 dx1dqtr;		/* 0x210 */
+	u32 dx1dqstr;		/* 0x214 */
+	u8 res6[0x28];		/* 0x218 */
+	u32 dx2gcr;		/* 0x240 */
+	u32 dx2gsr0;		/* 0x244 */
+	u32 dx2gsr1;		/* 0x248 */
+	u32 dx2dllcr;		/* 0x24c */
+	u32 dx2dqtr;		/* 0x250 */
+	u32 dx2dqstr;		/* 0x254 */
+	u8 res7[0x28];		/* 0x258 */
+	u32 dx3gcr;		/* 0x280 */
+	u32 dx3gsr0;		/* 0x284 */
+	u32 dx3gsr1;		/* 0x288 */
+	u32 dx3dllcr;		/* 0x28c */
+	u32 dx3dqtr;		/* 0x290 */
+	u32 dx3dqstr;		/* 0x294 */
+};
+
+/*
+ * DRAM common (sunxi_mctl_com_reg) register constants.
+ */
+#define MCTL_CR_RANK_MASK		(3 << 0)
+#define MCTL_CR_RANK(x)			(((x) - 1) << 0)
+#define MCTL_CR_BANK_MASK		(3 << 2)
+#define MCTL_CR_BANK(x)			((x) << 2)
+#define MCTL_CR_ROW_MASK		(0xf << 4)
+#define MCTL_CR_ROW(x)			(((x) - 1) << 4)
+#define MCTL_CR_PAGE_SIZE_MASK		(0xf << 8)
+#define MCTL_CR_PAGE_SIZE(x)		((fls(x) - 4) << 8)
+#define MCTL_CR_BUSW_MASK		(3 << 12)
+#define MCTL_CR_BUSW16			(1 << 12)
+#define MCTL_CR_BUSW32			(3 << 12)
+#define MCTL_CR_SEQUENCE		(1 << 15)
+#define MCTL_CR_DDR3			(3 << 16)
+#define MCTL_CR_CHANNEL_MASK		(1 << 19)
+#define MCTL_CR_CHANNEL(x)		(((x) - 1) << 19)
+#define MCTL_CR_UNKNOWN			((1 << 22) | (1 << 20))
+#define MCTL_CCR_CH0_CLK_EN		(1 << 0)
+#define MCTL_CCR_CH1_CLK_EN		(1 << 1)
+#define MCTL_CCR_MASTER_CLK_EN		(1 << 2)
+
+/*
+ * DRAM control (sunxi_mctl_ctl_reg) register constants.
+ * Note that we use constant values for a lot of the timings, this is what
+ * the original boot0 bootloader does.
+ */
+#define MCTL_SCTL_CONFIG		1
+#define MCTL_SCTL_ACCESS		2
+#define MCTL_MCMD_NOP			0x88000000
+#define MCTL_MCMD_BUSY			0x80000000
+#define MCTL_MCFG_DDR3			0x70061
+#define MCTL_TREFI			78
+#define MCTL_TMRD			4
+#define MCTL_TRFC			115
+#define MCTL_TRP			9
+#define MCTL_TPREA			0
+#define MCTL_TRTW			2
+#define MCTL_TAL			0
+#define MCTL_TCL			9
+#define MCTL_TCWL			8
+#define MCTL_TRAS			18
+#define MCTL_TRC			23
+#define MCTL_TRCD			9
+#define MCTL_TRRD			4
+#define MCTL_TRTP			4
+#define MCTL_TWR			8
+#define MCTL_TWTR			4
+#define MCTL_TEXSR			512
+#define MCTL_TXP			4
+#define MCTL_TXPDLL			14
+#define MCTL_TZQCS			64
+#define MCTL_TZQCSI			0
+#define MCTL_TDQS			1
+#define MCTL_TCKSRE			5
+#define MCTL_TCKSRX			5
+#define MCTL_TCKE			4
+#define MCTL_TMOD			12
+#define MCTL_TRSTL			80
+#define MCTL_TZQCL			512
+#define MCTL_TMRR			2
+#define MCTL_TCKESR			5
+#define MCTL_TDPD			0
+#define MCTL_DFITPHYRDL			15
+#define MCTL_DFIUPDCFG_UPD		(1 << 1)
+#define MCTL_DFISTCFG0			5
+
+/*
+ * DRAM phy (sunxi_mctl_phy_reg) register values / constants.
+ */
+#define MCTL_PIR_CLEAR_STATUS		(1 << 28)
+#define MCTL_PIR_STEP1			0xe9
+#define MCTL_PIR_STEP2			0x81
+#define MCTL_PGCR_RANK			(1 << 19)
+#define MCTL_PGCR			0x018c0202
+#define MCTL_PGSR_TRAIN_ERR_MASK	(3 << 5)
+/* constants for both acdllcr as well as dx#dllcr */
+#define MCTL_DLLCR_NRESET		(1 << 30)
+#define MCTL_DLLCR_DISABLE		(1 << 31)
+/* ptr constants these are or-ed together to get the final ptr# values */
+#define MCTL_TITMSRST			10
+#define MCTL_TDLLLOCK			2250
+#define MCTL_TDLLSRST			23
+#define MCTL_TDINIT0			217000
+#define MCTL_TDINIT1			160
+#define MCTL_TDINIT2			87000
+#define MCTL_TDINIT3			433
+/* end ptr constants */
+#define MCTL_ACIOCR_DISABLE		((3 << 18) | (1 << 8) | (1 << 3))
+#define MCTL_DXCCR_DISABLE		((1 << 3) | (1 << 2))
+#define MCTL_DXCCR			0x800
+#define MCTL_DSGCR_ENABLE		(1 << 28)
+#define MCTL_DSGCR			0xf200001b
+#define MCTL_DCR_DDR3			0x0b
+/* dtpr constants these are or-ed together to get the final dtpr# values */
+#define MCTL_TCCD			0
+#define MCTL_TDQSCKMAX			1
+#define MCTL_TDQSCK			1
+#define MCTL_TRTODT			0
+#define MCTL_TFAW			20
+#define MCTL_TAOND			0
+#define MCTL_TDLLK			512
+/* end dtpr constants */
+#define MCTL_MR0			0x1a50
+#define MCTL_MR1			0x4
+#define MCTL_MR2			((MCTL_TCWL - 5) << 3)
+#define MCTL_MR3			0x0
+#define MCTL_DX_GCR_EN			(1 << 0)
+#define MCTL_DX_GCR			0x880
+#define MCTL_DX_GSR0_RANK0_TRAIN_DONE	(1 << 0)
+#define MCTL_DX_GSR0_RANK1_TRAIN_DONE	(1 << 1)
+#define MCTL_DX_GSR0_RANK0_TRAIN_ERR	(1 << 4)
+#define MCTL_DX_GSR0_RANK1_TRAIN_ERR	(1 << 5)
+
+#endif /* _SUNXI_DRAM_SUN6I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 437dd35b68..c734cf015e 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -172,6 +172,9 @@ enum sunxi_gpio_number {
 
 #define SUN4I_GPI4_SDC3		2
 
+#define SUNXI_GPL0_R_P2WI_SCK	3
+#define SUNXI_GPL1_R_P2WI_SDA	3
+
 #define SUN8I_GPL2_R_UART_TX	2
 #define SUN8I_GPL3_R_UART_RX	2
 
diff --git a/arch/arm/include/asm/arch-sunxi/p2wi.h b/arch/arm/include/asm/arch-sunxi/p2wi.h
new file mode 100644
index 0000000000..2cf2d51c61
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/p2wi.h
@@ -0,0 +1,140 @@
+/*
+ * Sunxi platform Push-Push i2c register definition.
+ *
+ * (c) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ *
+ * (c)Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_P2WI_H
+#define _SUNXI_P2WI_H
+
+#include <linux/types.h>
+
+#define P2WI_CTRL_RESET (0x1 << 0)
+#define P2WI_CTRL_IRQ_EN (0x1 << 1)
+#define P2WI_CTRL_TRANS_ABORT (0x1 << 6)
+#define P2WI_CTRL_TRANS_START (0x1 << 7)
+
+#define __P2WI_CC_CLK(n) (((n) & 0xff) << 0)
+#define P2WI_CC_CLK_MASK __P2WI_CC_CLK_DIV(0xff)
+#define __P2WI_CC_CLK_DIV(n) (((n) >> 1) - 1)
+#define P2WI_CC_CLK_DIV(n) \
+	__P2WI_CC_CLK(__P2WI_CC_CLK_DIV(n))
+#define P2WI_CC_SDA_OUT_DELAY(n) (((n) & 0x7) << 8)
+#define P2WI_CC_SDA_OUT_DELAY_MASK P2WI_CC_SDA_OUT_DELAY(0x7)
+
+#define P2WI_IRQ_TRANS_DONE (0x1 << 0)
+#define P2WI_IRQ_TRANS_ERR (0x1 << 1)
+#define P2WI_IRQ_LOAD_BUSY (0x1 << 2)
+
+#define P2WI_STAT_TRANS_DONE (0x1 << 0)
+#define P2WI_STAT_TRANS_ERR (0x1 << 1)
+#define P2WI_STAT_LOAD_BUSY (0x1 << 2)
+#define __P2WI_STAT_TRANS_ERR(n) (((n) & 0xff) << 8)
+#define P2WI_STAT_TRANS_ERR_MASK __P2WI_STAT_TRANS_ERR_ID(0xff)
+#define __P2WI_STAT_TRANS_ERR_BYTE_1 0x01
+#define __P2WI_STAT_TRANS_ERR_BYTE_2 0x02
+#define __P2WI_STAT_TRANS_ERR_BYTE_3 0x04
+#define __P2WI_STAT_TRANS_ERR_BYTE_4 0x08
+#define __P2WI_STAT_TRANS_ERR_BYTE_5 0x10
+#define __P2WI_STAT_TRANS_ERR_BYTE_6 0x20
+#define __P2WI_STAT_TRANS_ERR_BYTE_7 0x40
+#define __P2WI_STAT_TRANS_ERR_BYTE_8 0x80
+#define P2WI_STAT_TRANS_ERR_BYTE_1 \
+	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_1)
+#define P2WI_STAT_TRANS_ERR_BYTE_2 \
+	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_2)
+#define P2WI_STAT_TRANS_ERR_BYTE_3 \
+	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_3)
+#define P2WI_STAT_TRANS_ERR_BYTE_4 \
+	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_4)
+#define P2WI_STAT_TRANS_ERR_BYTE_5 \
+	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_5)
+#define P2WI_STAT_TRANS_ERR_BYTE_6 \
+	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_6)
+#define P2WI_STAT_TRANS_ERR_BYTE_7 \
+	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_7)
+#define P2WI_STAT_TRANS_ERR_BYTE_8 \
+	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_8)
+
+#define P2WI_DATADDR_BYTE_1(n) (((n) & 0xff) << 0)
+#define P2WI_DATADDR_BYTE_1_MASK P2WI_DATADDR_BYTE_1(0xff)
+#define P2WI_DATADDR_BYTE_2(n) (((n) & 0xff) << 8)
+#define P2WI_DATADDR_BYTE_2_MASK P2WI_DATADDR_BYTE_2(0xff)
+#define P2WI_DATADDR_BYTE_3(n) (((n) & 0xff) << 16)
+#define P2WI_DATADDR_BYTE_3_MASK P2WI_DATADDR_BYTE_3(0xff)
+#define P2WI_DATADDR_BYTE_4(n) (((n) & 0xff) << 24)
+#define P2WI_DATADDR_BYTE_4_MASK P2WI_DATADDR_BYTE_4(0xff)
+#define P2WI_DATADDR_BYTE_5(n) (((n) & 0xff) << 0)
+#define P2WI_DATADDR_BYTE_5_MASK P2WI_DATADDR_BYTE_5(0xff)
+#define P2WI_DATADDR_BYTE_6(n) (((n) & 0xff) << 8)
+#define P2WI_DATADDR_BYTE_6_MASK P2WI_DATADDR_BYTE_6(0xff)
+#define P2WI_DATADDR_BYTE_7(n) (((n) & 0xff) << 16)
+#define P2WI_DATADDR_BYTE_7_MASK P2WI_DATADDR_BYTE_7(0xff)
+#define P2WI_DATADDR_BYTE_8(n) (((n) & 0xff) << 24)
+#define P2WI_DATADDR_BYTE_8_MASK P2WI_DATADDR_BYTE_8(0xff)
+
+#define __P2WI_DATA_NUM_BYTES(n) (((n) & 0x7) << 0)
+#define P2WI_DATA_NUM_BYTES_MASK __P2WI_DATA_NUM_BYTES(0x7)
+#define P2WI_DATA_NUM_BYTES(n) __P2WI_DATA_NUM_BYTES((n) - 1)
+#define P2WI_DATA_NUM_BYTES_READ (0x1 << 4)
+
+#define P2WI_DATA_BYTE_1(n) (((n) & 0xff) << 0)
+#define P2WI_DATA_BYTE_1_MASK P2WI_DATA_BYTE_1(0xff)
+#define P2WI_DATA_BYTE_2(n) (((n) & 0xff) << 8)
+#define P2WI_DATA_BYTE_2_MASK P2WI_DATA_BYTE_2(0xff)
+#define P2WI_DATA_BYTE_3(n) (((n) & 0xff) << 16)
+#define P2WI_DATA_BYTE_3_MASK P2WI_DATA_BYTE_3(0xff)
+#define P2WI_DATA_BYTE_4(n) (((n) & 0xff) << 24)
+#define P2WI_DATA_BYTE_4_MASK P2WI_DATA_BYTE_4(0xff)
+#define P2WI_DATA_BYTE_5(n) (((n) & 0xff) << 0)
+#define P2WI_DATA_BYTE_5_MASK P2WI_DATA_BYTE_5(0xff)
+#define P2WI_DATA_BYTE_6(n) (((n) & 0xff) << 8)
+#define P2WI_DATA_BYTE_6_MASK P2WI_DATA_BYTE_6(0xff)
+#define P2WI_DATA_BYTE_7(n) (((n) & 0xff) << 16)
+#define P2WI_DATA_BYTE_7_MASK P2WI_DATA_BYTE_7(0xff)
+#define P2WI_DATA_BYTE_8(n) (((n) & 0xff) << 24)
+#define P2WI_DATA_BYTE_8_MASK P2WI_DATA_BYTE_8(0xff)
+
+#define P2WI_LINECTRL_SDA_CTRL_EN (0x1 << 0)
+#define P2WI_LINECTRL_SDA_OUT_HIGH (0x1 << 1)
+#define P2WI_LINECTRL_SCL_CTRL_EN (0x1 << 2)
+#define P2WI_LINECTRL_SCL_OUT_HIGH (0x1 << 3)
+#define P2WI_LINECTRL_SDA_STATE_HIGH (0x1 << 4)
+#define P2WI_LINECTRL_SCL_STATE_HIGH (0x1 << 5)
+
+#define P2WI_PM_DEV_ADDR(n) (((n) & 0xff) << 0)
+#define P2WI_PM_DEV_ADDR_MASK P2WI_PM_DEV_ADDR(0xff)
+#define P2WI_PM_CTRL_ADDR(n) (((n) & 0xff) << 8)
+#define P2WI_PM_CTRL_ADDR_MASK P2WI_PM_CTRL_ADDR(0xff)
+#define P2WI_PM_INIT_DATA(n) (((n) & 0xff) << 16)
+#define P2WI_PM_INIT_DATA_MASK P2WI_PM_INIT_DATA(0xff)
+#define P2WI_PM_INIT_SEND (0x1 << 31)
+
+struct sunxi_p2wi_reg {
+	u32 ctrl;	/* 0x00 control */
+	u32 cc;		/* 0x04 clock control */
+	u32 irq;	/* 0x08 interrupt */
+	u32 status;	/* 0x0c status */
+	u32 dataddr0;	/* 0x10 data address 0 */
+	u32 dataddr1;	/* 0x14 data address 1 */
+	u32 numbytes;	/* 0x18 num bytes */
+	u32 data0;	/* 0x1c data buffer 0 */
+	u32 data1;	/* 0x20 data buffer 1 */
+	u32 linectrl;	/* 0x24 line control */
+	u32 pm;		/* 0x28 power management */
+};
+
+void p2wi_init(void);
+int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data);
+int p2wi_read(const u8 addr, u8 *data);
+int p2wi_write(const u8 addr, u8 data);
+
+#endif /* _SUNXI_P2WI_H */
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
index 3d3bfa6cd1..88de1ff675 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -119,6 +119,7 @@
 #define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
 	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
 #define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
+#define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24)
 
 #define PRCM_CLK_1WIRE_GATE (0x1 << 31)