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authorTom Rini <trini@konsulko.com>2019-04-17 09:19:13 -0400
committerTom Rini <trini@konsulko.com>2019-04-17 09:19:13 -0400
commit14b8c420b88a90e7ca0c979a2ee413bf459941e8 (patch)
tree89805507eebb3a6b14c94fe62c95546bacbe7f5a /arch
parent88d5ab3d67c7507160792991e99bda9fff34d106 (diff)
parent350cfe79a8fb288e9066d5668af7c5ab6857edea (diff)
Merge tag 'xilinx-for-v2019.07' of git://git.denx.de/u-boot-microblaze
Xilinx/FPGA changes for v2019.07 fpga: - Add support for external data in FIT - Extend testing for external data case - Inform user about a need to run post config on Zynq arm: - Tune zynq command functions - Fix internal variable setting arm64: - Add support for zc39dr decoding - Disable WDT for zcu100 - Small changes in reset_reason() - Some DT changes (spi) - Tune qspi-mini configuration - Remove useless eeprom setting - Fix two sdhci boot case spi: - Fix tap delay programming clk: - Enable i2c in SPL net: - Fix gem phydev handling - Remove phy detection code from gem driver general: - Correct EXT_DTB usage for MULTI_DTB_FIT configuration
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/dts/zynqmp-mini-qspi.dts4
-rw-r--r--arch/arm/mach-zynqmp/spl.c3
2 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts
index c235a5f731..1716d5179d 100644
--- a/arch/arm/dts/zynqmp-mini-qspi.dts
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@@ -63,8 +63,8 @@
&qspi {
status = "okay";
- flash@0 {
- compatible = "n25q512a11";
+ flash0: flash@0 {
+ compatible = "n25q512a11", "spi-flash";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
index f6f5414201..b52ac17853 100644
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@@ -27,6 +27,7 @@ void board_init_f(ulong dummy)
/* Delay is required for clocks to be propagated */
udelay(1000000);
+ debug("Clearing BSS 0x%p - 0x%p\n", __bss_start, __bss_end);
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -85,7 +86,7 @@ u32 spl_boot_device(void)
case SD_MODE1:
case SD1_LSHFT_MODE: /* not working on silicon v1 */
/* if both controllers enabled, then these two are the second controller */
-#if defined(SPL_ZYNQMP_TWO_SDHCI)
+#ifdef CONFIG_SPL_ZYNQMP_TWO_SDHCI
return BOOT_DEVICE_MMC2;
/* else, fall through, the one SDHCI controller that is enabled is number 1 */
#endif