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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-08-09 16:48:34 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-08-09 16:48:34 +0200
commit1899fac925eda817e12234aef3d01d354788662e (patch)
treebaed464b3d9250361cd85e931a16d87b397cc36f /arch
parente76b933e02e1b38e48754c435e9dba1c0deeb3c6 (diff)
parent3340eab26d89176dd0bf543e6d2590665c577423 (diff)
Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/sunxi/Makefile3
-rw-r--r--arch/arm/cpu/armv7/sunxi/board.c5
-rw-r--r--arch/arm/cpu/armv7/sunxi/clock_sun4i.c4
-rw-r--r--arch/arm/cpu/armv7/sunxi/psci.S162
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun4i.h15
5 files changed, 185 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 6c706393d3..e9721b27b6 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -17,6 +17,9 @@ obj-$(CONFIG_SUN7I) += clock_sun4i.o
ifndef CONFIG_SPL_BUILD
obj-y += cpu_info.o
+ifdef CONFIG_ARMV7_PSCI
+obj-y += psci.o
+endif
endif
ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 8f2cef332f..f2cedbb156 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -129,6 +129,11 @@ int cpu_eth_init(bd_t *bis)
{
__maybe_unused int rc;
+#ifdef CONFIG_MACPWR
+ gpio_direction_output(CONFIG_MACPWR, 1);
+ mdelay(200);
+#endif
+
#ifdef CONFIG_SUNXI_EMAC
rc = sunxi_emac_initialize(bis);
if (rc < 0) {
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index b8b16cff95..ecbdb0162b 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -39,6 +39,10 @@ void clock_init_safe(void)
setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
#endif
writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+#ifdef CONFIG_SUNXI_AHCI
+ setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
+ setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);
+#endif
}
#endif
diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
new file mode 100644
index 0000000000..0084c811f3
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Based on code by Carl van Schaik <carl@ok-labs.com>.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <config.h>
+#include <asm/psci.h>
+#include <asm/arch/cpu.h>
+
+/*
+ * Memory layout:
+ *
+ * SECURE_RAM to text_end :
+ * ._secure_text section
+ * text_end to ALIGN_PAGE(text_end):
+ * nothing
+ * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
+ * 1kB of stack per CPU (4 CPUs max).
+ */
+
+ .pushsection ._secure.text, "ax"
+
+ .arch_extension sec
+
+#define ONE_MS (CONFIG_SYS_CLK_FREQ / 1000)
+#define TEN_MS (10 * ONE_MS)
+
+.macro timer_wait reg, ticks
+ @ Program CNTP_TVAL
+ movw \reg, #(\ticks & 0xffff)
+ movt \reg, #(\ticks >> 16)
+ mcr p15, 0, \reg, c14, c2, 0
+ isb
+ @ Enable physical timer, mask interrupt
+ mov \reg, #3
+ mcr p15, 0, \reg, c14, c2, 1
+ @ Poll physical timer until ISTATUS is on
+1: isb
+ mrc p15, 0, \reg, c14, c2, 1
+ ands \reg, \reg, #4
+ bne 1b
+ @ Disable timer
+ mov \reg, #0
+ mcr p15, 0, \reg, c14, c2, 1
+ isb
+.endm
+
+.globl psci_arch_init
+psci_arch_init:
+ mrc p15, 0, r5, c1, c1, 0 @ Read SCR
+ bic r5, r5, #1 @ Secure mode
+ mcr p15, 0, r5, c1, c1, 0 @ Write SCR
+ isb
+
+ mrc p15, 0, r4, c0, c0, 5 @ MPIDR
+ and r4, r4, #3 @ cpu number in cluster
+ mov r5, #400 @ 1kB of stack per CPU
+ mul r4, r4, r5
+
+ adr r5, text_end @ end of text
+ add r5, r5, #0x2000 @ Skip two pages
+ lsr r5, r5, #12 @ Align to start of page
+ lsl r5, r5, #12
+ sub sp, r5, r4 @ here's our stack!
+
+ bx lr
+
+ @ r1 = target CPU
+ @ r2 = target PC
+.globl psci_cpu_on
+psci_cpu_on:
+ adr r0, _target_pc
+ str r2, [r0]
+ dsb
+
+ movw r0, #(SUNXI_CPUCFG_BASE & 0xffff)
+ movt r0, #(SUNXI_CPUCFG_BASE >> 16)
+
+ @ CPU mask
+ and r1, r1, #3 @ only care about first cluster
+ mov r4, #1
+ lsl r4, r4, r1
+
+ adr r6, _sunxi_cpu_entry
+ str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
+
+ @ Assert reset on target CPU
+ mov r6, #0
+ lsl r5, r1, #6 @ 64 bytes per CPU
+ add r5, r5, #0x40 @ Offset from base
+ add r5, r5, r0 @ CPU control block
+ str r6, [r5] @ Reset CPU
+
+ @ l1 invalidate
+ ldr r6, [r0, #0x184]
+ bic r6, r6, r4
+ str r6, [r0, #0x184]
+
+ @ Lock CPU
+ ldr r6, [r0, #0x1e4]
+ bic r6, r6, r4
+ str r6, [r0, #0x1e4]
+
+ @ Release power clamp
+ movw r6, #0x1ff
+ movt r6, #0
+1: lsrs r6, r6, #1
+ str r6, [r0, #0x1b0]
+ bne 1b
+
+ timer_wait r1, TEN_MS
+
+ @ Clear power gating
+ ldr r6, [r0, #0x1b4]
+ bic r6, r6, #1
+ str r6, [r0, #0x1b4]
+
+ @ Deassert reset on target CPU
+ mov r6, #3
+ str r6, [r5]
+
+ @ Unlock CPU
+ ldr r6, [r0, #0x1e4]
+ orr r6, r6, r4
+ str r6, [r0, #0x1e4]
+
+ mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS
+ mov pc, lr
+
+_target_pc:
+ .word 0
+
+_sunxi_cpu_entry:
+ @ Set SMP bit
+ mrc p15, 0, r0, c1, c0, 1
+ orr r0, r0, #0x40
+ mcr p15, 0, r0, c1, c0, 1
+ isb
+
+ bl _nonsec_init
+ bl psci_arch_init
+
+ adr r0, _target_pc
+ ldr r0, [r0]
+ b _do_nonsec_entry
+
+text_end:
+ .popsection
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 928f3f2670..1ba997adf9 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -218,10 +218,13 @@ struct sunxi_ccm_reg {
#define CCM_PLL5_CTRL_BYPASS (0x1 << 30)
#define CCM_PLL5_CTRL_EN (0x1 << 31)
-#define CCM_PLL6_CTRL_N_SHIFT 8
-#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
-#define CCM_PLL6_CTRL_K_SHIFT 4
-#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
+#define CCM_PLL6_CTRL_EN 31
+#define CCM_PLL6_CTRL_BYPASS_EN 30
+#define CCM_PLL6_CTRL_SATA_EN_SHIFT 14
+#define CCM_PLL6_CTRL_N_SHIFT 8
+#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_K_SHIFT 4
+#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
#define CCM_GPS_CTRL_RESET (0x1 << 0)
#define CCM_GPS_CTRL_GATE (0x1 << 1)
@@ -253,4 +256,8 @@ struct sunxi_ccm_reg {
#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
+#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
+#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
+#define CCM_USB_CTRL_PHYGATE (0x1 << 8)
+
#endif /* _SUNXI_CLOCK_SUN4I_H */