Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

* 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/p3060: Add SoC related support for P3060 platform powerpc/85xx: Add support for setting up RAID engine liodns on P5020 powerpc/85xx: Refactor some defines out of corenet_ds.h fm-eth: Add ability for board code to disable a port powerpc/mpc8548: Add workaround for erratum NMG_LBC103 powerpc/mpc8548: Add workaround for erratum NMG_DDR120 powerpc/mpc85xxcds: Fix PCI speed powerpc/mpc8548cds: Fix booting message powerpc/p4080: Add support for secure boot flow powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards powerpc/p2041rdb: remove watch dog related codes powerpc/p2041rdb: updated description of cpld command powerpc/p2041rdb: add more ddr frequencies support powerpc/p2041rdb: set sysclk according to status of physical switch SW1 powerpc/p2041rdb: update cpld reset command according to CPLD 2.0 powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver powerpc/mpc8xxx: Add DDR2 to unified DDR driver powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps() powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en powerpc/85xx: Refactor P2041RDB to use common p_corenet files powerpc/85xx: refactor common P-Series CoreNet files for FSL boards powerpc/85xx: Enable CMD_REGINFO on corenet boards powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries powerpc/85xx: Fix USB protocol definitions for P1020RDB powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM powerpc/mpc8xxx: Move DDR RCW overriding to common code powerpc/mpc8xxx: Extend CWL table powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536 powerpc/85xx: Cleanup extern in corenet_ds board code powerpc/p2041rdb: Add ethernet support on P2041RDB board powerpc/85xx: Add networking support to P1023RDS powerpc/hydra: Add ethernet support on P5020/P3041 DS boards powerpc/85xx: Add FMan ethernet support to P4080DS powerpc/85xx: Add support for FMan ethernet in Independent mode powerpc/mpc8548cds: Cleanup mpc8548cds.c powerpc/mp: add support for discontiguous cores powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries fdt: Add new fdt_create_phandle helper fdt: Rename fdt_create_phandle to fdt_set_phandle powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010) powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC) fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010) powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB nand: Freescale Integrated Flash Controller NAND support powerpc/85xx: Add basic support for P1010RDB powerpc/85xx: Add support for new P102x/P2020 RDB style boards powerpc/85xx: relocate CCSR before creating the initial RAM area powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0 powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
author: Wolfgang Denk <wd@denx.de> 2011-10-04 22:08:13 +0200
committer: Wolfgang Denk <wd@denx.de> 2011-10-04 22:08:13 +0200
commit: 1fed668b3fb9c35932f58af00ff5539239fa4e1d (patch)
tree: eaaaead8ca19924af1823caae040f504be9b6d98 /arch
parent: c52575350fd6e794717f6bee4f81dbb8038fe22e (diff)
parent: 6d7b061af153bc5beb633c3bd15348284716a067 (diff)
43 files changed, 2283 insertions, 168 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile
index 3979b6fbab..b353036184 100644
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile
@@ -34,7 +34,6 @@ COBJS-y += cpu.o
 COBJS-y += cpu_init.o
 COBJS-y += speed.o
 COBJS-y += interrupts.o
-COBJS-y += spd_sdram.o
 COBJS-y += ecc.o
 COBJS-$(CONFIG_QE) += qe_io.o
 COBJS-$(CONFIG_FSL_SERDES) += serdes.o
@@ -42,6 +41,13 @@ COBJS-$(CONFIG_PCI) += pci.o
 COBJS-$(CONFIG_PCIE) += pcie.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 
+ifdef CONFIG_FSL_DDR2
+COBJS-$(CONFIG_MPC8349) += ddr-gen2.o
+else
+COBJS-y += spd_sdram.o
+endif
+COBJS-$(CONFIG_FSL_DDR2) += law.o
+
 COBJS	:= $(COBJS-y)
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
@@ -52,6 +58,18 @@ all:	$(obj).depend $(START) $(LIB)
 $(LIB):	$(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
+$(obj)ddr-gen1.c:
+	@rm -f $(obj)ddr-gen1.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen1.c $(obj)ddr-gen1.c
+
+$(obj)ddr-gen2.c:
+	@rm -f $(obj)ddr-gen2.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen2.c $(obj)ddr-gen2.c
+
+$(obj)ddr-gen3.c:
+	@rm -f $(obj)ddr-gen3.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen3.c $(obj)ddr-gen3.c
+
 #########################################################################
 
 # defines $(obj).depend target
diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c
index f8eab96b19..717365c8d1 100644
--- a/arch/powerpc/cpu/mpc83xx/ecc.c
+++ b/arch/powerpc/cpu/mpc83xx/ecc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
  *
  * Dave Liu <daveliu@freescale.com>
  * based on the contribution of Marian Balakowicz <m8@semihalf.com>
@@ -20,8 +20,12 @@
 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
 void ecc_print_status(void)
 {
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile ddr83xx_t *ddr = &immap->ddr;
+	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+#ifdef CONFIG_FSL_DDR2
+	ccsr_ddr_t *ddr = &immap->ddr;
+#else
+	ddr83xx_t *ddr = &immap->ddr;
+#endif
 
 	printf("\nECC mode: %s\n\n",
 	       (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
@@ -100,8 +104,12 @@ void ecc_print_status(void)
 
 int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 {
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile ddr83xx_t *ddr = &immap->ddr;
+	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+#ifdef CONFIG_FSL_DDR2
+	ccsr_ddr_t *ddr = &immap->ddr;
+#else
+	ddr83xx_t *ddr = &immap->ddr;
+#endif
 	volatile u32 val;
 	u64 *addr;
 	u32 count;
diff --git a/arch/powerpc/cpu/mpc83xx/law.c b/arch/powerpc/cpu/mpc83xx/law.c
new file mode 100644
index 0000000000..66c88b697e
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/law.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
+{
+	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
+	u64 start_align, law_sz;
+	int law_sz_enc;
+
+	if (start == 0)
+		start_align = 1ull << (LAW_SIZE_2G + 1);
+	else
+		start_align = 1ull << (ffs64(start) - 1);
+	law_sz = min(start_align, sz);
+	law_sz_enc = __ilog2_u64(law_sz) - 1;
+
+	/*
+	 * Set up LAWBAR for all of DDR.
+	 */
+	ecm->bar = start & 0xfffff000;
+	ecm->ar  = (LAWAR_EN | (id << 20) | (LAWAR_SIZE & law_sz_enc));
+	debug("DDR:bar=0x%08x\n", ecm->bar);
+	debug("DDR:ar=0x%08x\n", ecm->ar);
+
+	/* recalculate size based on what was actually covered by the law */
+	law_sz = 1ull << __ilog2_u64(law_sz);
+
+	/* do we still have anything to map */
+	sz = sz - law_sz;
+	if (sz) {
+		start += law_sz;
+
+		start_align = 1ull << (ffs64(start) - 1);
+		law_sz = min(start_align, sz);
+		law_sz_enc = __ilog2_u64(law_sz) - 1;
+		ecm = &immap->sysconf.ddrlaw[1];
+		ecm->bar = start & 0xfffff000;
+		ecm->ar  = (LAWAR_EN | (id << 20) | (LAWAR_SIZE & law_sz_enc));
+		debug("DDR:bar=0x%08x\n", ecm->bar);
+		debug("DDR:ar=0x%08x\n", ecm->ar);
+	} else {
+		return 0;
+	}
+
+	/* do we still have anything to map */
+	sz = sz - law_sz;
+	if (sz)
+		return 1;
+
+	return 0;
+}
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index 4542ab1ac4..f78099d2fe 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -507,6 +507,15 @@ ulong get_bus_freq(ulong dummy)
 	return gd->csb_clk;
 }
 
+/********************************************
+ * get_ddr_freq
+ * return ddr bus freq in Hz
+ *********************************************/
+ulong get_ddr_freq(ulong dummy)
+{
+	return gd->mem_clk;
+}
+
 int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 {
 	char buf[32];
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 7026bca609..058d609f17 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -67,6 +67,7 @@ COBJS-$(CONFIG_P2020)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P2040)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P2041)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P3041)	+= ddr-gen3.o
+COBJS-$(CONFIG_PPC_P3060)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P4080)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5020)	+= ddr-gen3.o
 
@@ -81,6 +82,7 @@ COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
 COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o
 COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
+COBJS-$(CONFIG_PPC_P3060) += p3060_ids.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
 
@@ -114,6 +116,7 @@ COBJS-$(CONFIG_P2020)	+= p2020_serdes.o
 COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o
 COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
+COBJS-$(CONFIG_PPC_P3060) += p3060_serdes.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
 
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 7b9f77362c..a09eb91406 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -87,6 +87,22 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	puts("Work-around for Erratum DDR111 enabled\n");
 	puts("Work-around for Erratum DDR134 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
+	puts("Work-around for Erratum IFC-A002769 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+	puts("Work-around for Erratum P1010-A003549 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+	puts("Work-around for Erratum IFC A-003399 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
+		puts("Work-around for Erratum NMG DDR120 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
+	puts("Work-around for Erratum NMG_LBC103 enabled\n");
+#endif
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 22fa4615cb..49c0551692 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -64,13 +64,11 @@ int checkcpu (void)
 	u32 ddr_ratio = 0;
 #endif /* CONFIG_FSL_CORENET */
 #endif /* CONFIG_DDR_CLK_FREQ */
-	int i;
+	unsigned int i, core, nr_cores = cpu_numcores();
+	u32 mask = cpu_mask();
 
 	svr = get_svr();
 	major = SVR_MAJ(svr);
-#ifdef CONFIG_MPC8536
-	major &= 0x7; /* the msb of this nibble is a mfg code */
-#endif
 	minor = SVR_MIN(svr);
 
 	if (cpu_numcores() > 1) {
@@ -119,11 +117,11 @@ int checkcpu (void)
 	get_sys_info(&sysinfo);
 
 	puts("Clock Configuration:");
-	for (i = 0; i < cpu_numcores(); i++) {
+	for_each_cpu(i, core, nr_cores, mask) {
 		if (!(i & 3))
 			printf ("\n       ");
-		printf("CPU%d:%-4s MHz, ",
-				i,strmhz(buf1, sysinfo.freqProcessor[i]));
+		printf("CPU%d:%-4s MHz, ", core,
+			strmhz(buf1, sysinfo.freqProcessor[core]));
 	}
 	printf("\n       CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 6aca166a98..0a4ce538f3 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -31,6 +31,7 @@
 #include <asm/processor.h>
 #include <ioports.h>
 #include <sata.h>
+#include <fm_eth.h>
 #include <asm/io.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
@@ -225,7 +226,9 @@ void cpu_init_f (void)
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
-
+#if defined(CONFIG_SECURE_BOOT)
+	struct law_entry law;
+#endif
 #ifdef CONFIG_MPC8548
 	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	uint svr = get_svr();
@@ -243,6 +246,13 @@ void cpu_init_f (void)
 	disable_tlb(14);
 	disable_tlb(15);
 
+#if defined(CONFIG_SECURE_BOOT)
+	/* Disable the LAW created for NOR flash by the PBI commands */
+	law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
+	if (law.index != -1)
+		disable_law(law.index);
+#endif
+
 #ifdef CONFIG_CPM2
 	config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
 #endif
@@ -453,6 +463,9 @@ skip_l2:
 	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
 	__raw_readl(&lbc->lcrr);
 	isync();
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
+	udelay(100);
+#endif
 #endif
 
 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
@@ -472,6 +485,10 @@ skip_l2:
 	}
 #endif
 
+#ifdef CONFIG_FMAN_ENET
+	fman_enet_init();
+#endif
+
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 32aa94b612..4ef3c9a8a5 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc
+ * Copyright 2009-2011 Freescale Semiconductor, Inc
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -21,59 +21,59 @@
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
-#ifdef CONFIG_FSL_CORENET
-static void setup_ccsrbar(void)
+#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+void setup_ifc(void)
 {
-	u32 temp;
-	volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
-	volatile ccsr_local_t *ccm;
+	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
+	phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
 
 	/*
-	 * We can't call set_law() because we haven't moved
-	 * CCSR yet.
+	 * Adjust the TLB we were running out of to match the phys addr of the
+	 * chip select we are adjusting and will return to.
 	 */
-	ccm = (void *)ccsr_virt;
-
-	out_be32(&ccm->law[0].lawbarh,
-		(u64)CONFIG_SYS_CCSRBAR_PHYS >> 32);
-	out_be32(&ccm->law[0].lawbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS);
-	out_be32(&ccm->law[0].lawar,
-		LAW_EN | (0x1e << 20) | LAW_SIZE_4K);
-
-	in_be32((u32 *)(ccsr_virt + 0));
-	in_be32((u32 *)(ccsr_virt + 1));
-	isync();
-
-	ccm = (void *)CONFIG_SYS_CCSRBAR;
-	/* Now use the temporary LAW to move CCSR */
-	out_be32(&ccm->ccsrbarh, (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32);
-	out_be32(&ccm->ccsrbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS);
-	out_be32(&ccm->ccsrar, CCSRAR_C);
-	temp = in_be32(&ccm->ccsrar);
-	disable_law(0);
-}
-#else
-static void setup_ccsrbar(void)
-{
-	u32 temp;
-	volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
+	flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024;
+
+	_mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
+	_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
+			MAS1_TSIZE(BOOKE_PAGESZ_4M);
+	_mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
+	_mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
+	_mas7 = FSL_BOOKE_MAS7(flash_phys);
+
+	mtspr(MAS0, _mas0);
+	mtspr(MAS1, _mas1);
+	mtspr(MAS2, _mas2);
+	mtspr(MAS3, _mas3);
+	mtspr(MAS7, _mas7);
 
-	temp = in_be32(ccsr_virt);
-	out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
-	temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR);
+	asm volatile("isync;msync;tlbwe;isync");
+
+	out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
+	out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
+	out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
+
+	return ;
 }
 #endif
-#endif
 
 /* We run cpu_init_early_f in AS = 1 */
 void cpu_init_early_f(void)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
 	int i;
+#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+	u32  *l2srbar, *dst, *src;
+	void (*setup_ifc_sram)(void);
+#endif
 
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@@ -85,28 +85,77 @@ void cpu_init_early_f(void)
 	for (i = 0; i < sizeof(gd_t); i++)
 		((char *)gd)[i] = 0;
 
-	mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0);
-	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K);
+	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
+	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
 	mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
 	mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
 	mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
 
 	write_tlb(mas0, mas1, mas2, mas3, mas7);
 
-	/* set up CCSR if we want it moved */
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
-	mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1);
-	/* mas1 is the same as above */
-	mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G);
-	mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, MAS3_SW|MAS3_SR);
-	mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT);
+/*
+ * Work Around for IFC Erratum A-003549. This issue is P1010
+ * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC
+ * Hence specifically selecting CS3.
+ */
+#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3);
+#endif
+
+	init_laws();
+
+/*
+ * Work Around for IFC Erratum A003399, issue will hit only when execution
+ * from NOR Flash
+ */
+#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+#define SRAM_BASE_ADDR	(0x00000000)
+	/* TLB for SRAM */
+	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
+	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS |
+		MAS1_TSIZE(BOOKE_PAGESZ_1M);
+	mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I);
+	mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR);
+	mas7 = FSL_BOOKE_MAS7(0);
 
 	write_tlb(mas0, mas1, mas2, mas3, mas7);
 
-	setup_ccsrbar();
+	out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR);
+
+	out_be32(&l2cache->l2errdis,
+		(MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
+
+	out_be32(&l2cache->l2ctl,
+		(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
+
+	/*
+	 * Copy the code in setup_ifc to L2SRAM. Do a word copy
+	 * because NOR Flash on P1010 does not support byte
+	 * access (Erratum IFC-A002769)
+	 */
+	setup_ifc_sram = (void *)SRAM_BASE_ADDR;
+	dst = (u32 *) SRAM_BASE_ADDR;
+	src = (u32 *) setup_ifc;
+	for (i = 0; i < 1024; i++)
+		*l2srbar++ = *src++;
+
+	setup_ifc_sram();
+
+	/* CLEANUP */
+	clrbits_be32(&l2cache->l2ctl,
+			(MPC85xx_L2CTL_L2E |
+			 MPC85xx_L2CTL_L2SRAM_ENTIRE));
+	out_be32(&l2cache->l2srbar0, 0x0);
+#endif
+
+	invalidate_tlb(1);
+
+#if defined(CONFIG_SECURE_BOOT)
+	/* Disable the TLBs created by ISBC */
+	for (i = CONFIG_SYS_ISBC_START_TLB;
+	     i < CONFIG_SYS_ISBC_START_TLB + CONFIG_SYS_ISBC_NUM_TLBS; i++)
+			disable_tlb(i);
 #endif
 
-	init_laws();
-	invalidate_tlb(0);
 	init_tlbs();
 }
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
index 796d398426..f33db021f1 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
@@ -21,10 +21,12 @@
  */
 
 #include <common.h>
+#include <asm/fsl_ifc.h>
 #include <asm/io.h>
 
 void cpu_init_f(void)
 {
+#ifdef CONFIG_FSL_LBC
 	fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	/*
@@ -39,6 +41,16 @@ void cpu_init_f(void)
 #else
 #error  CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM must be defined
 #endif
+#endif
+#ifdef CONFIG_FSL_IFC
+#ifndef	CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
+	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
+	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
+	set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
+#endif
+#endif
+#endif
 
 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
 	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
index 655f99c028..49000a19e8 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/processor.h>
 #include <asm/fsl_ddr_sdram.h>
 
 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
@@ -18,13 +19,36 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 			     unsigned int ctrl_num)
 {
 	unsigned int i;
-	volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+#ifdef CONFIG_MPC83xx
+	ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC83xx_DDR_ADDR;
+#else
+	ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	uint svr;
+#endif
+#endif
 
 	if (ctrl_num) {
 		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
 		return;
 	}
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+	/*
+	 * Set the DDR IO receiver to an acceptable bias point.
+	 * Fixed in Rev 2.1.
+	 */
+	svr = get_svr();
+	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
+		if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
+		   SDRAM_CFG_SDRAM_TYPE_DDR2)
+			out_be32(&gur->ddrioovcr, 0x90000000);
+		else
+			out_be32(&gur->ddrioovcr, 0xA8000000);
+	}
+#endif
+
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 		if (i == 0) {
 			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 8f13cd8ebf..d20c94c0f7 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -361,6 +361,7 @@ void fdt_add_enet_stashing(void *fdt)
 }
 
 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
+#ifdef CONFIG_SYS_DPAA_FMAN
 static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
 			  unsigned long freq)
 {
@@ -374,12 +375,14 @@ static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
 				"for %s: %s\n", compat, fdt_strerror(off));
 	}
 }
+#endif
 
 static void ft_fixup_dpaa_clks(void *blob)
 {
 	sys_info_t sysinfo;
 
 	get_sys_info(&sysinfo);
+#ifdef CONFIG_SYS_DPAA_FMAN
 	ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
 			sysinfo.freqFMan[0]);
 
@@ -387,6 +390,7 @@ static void ft_fixup_dpaa_clks(void *blob)
 	ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
 			sysinfo.freqFMan[1]);
 #endif
+#endif
 
 #ifdef CONFIG_SYS_DPAA_PME
 	do_fixup_by_compat_u32(blob, "fsl,pme",
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 4307a4ccbb..07e58ed024 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -482,6 +482,13 @@ static void wait_for_rstdone(unsigned int bank)
 		printf("SERDES: timeout resetting bank %u\n", bank + 1);
 }
 
+
+void __soc_serdes_init(void)
+{
+	/* Allow for SoC-specific initialization in <SOC>_serdes.c  */
+};
+void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init")));
+
 void fsl_serdes_init(void)
 {
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -570,6 +577,8 @@ void fsl_serdes_init(void)
 		}
 	}
 
+	soc_serdes_init();
+
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 	/*
 	 * Bank two uses the clock from bank three, so if bank two is enabled,
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index bd1909471c..e0ea502a05 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -120,6 +120,19 @@ static void setup_pme_liodn_base(void)
 #endif
 }
 
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+static void setup_raide_liodn_base(void)
+{
+	struct ccsr_raide *raide = (void *)CONFIG_SYS_FSL_RAID_ENGINE_ADDR;
+
+	/* setup raid engine liodn base for data/desc ; both set to 47 */
+	u32 base = (liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0] << 16) |
+			liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0];
+
+	out_be32(&raide->liodnbr, base);
+}
+#endif
+
 void set_liodns(void)
 {
 	/* setup general liodn offsets */
@@ -145,6 +158,12 @@ void set_liodns(void)
 #endif
 	/* setup PME liodn base */
 	setup_pme_liodn_base();
+
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+	/* raid engine ccr addr code for liodn */
+	set_liodn(raide_liodn_tbl, raide_liodn_tbl_sz);
+	setup_raide_liodn_base();
+#endif
 }
 
 static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz)
@@ -184,4 +203,8 @@ void fdt_fixup_liodn(void *blob)
 #endif
 #endif
 	fdt_fixup_liodn_tbl(blob, sec_liodn_tbl, sec_liodn_tbl_sz);
+
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+	fdt_fixup_liodn_tbl(blob, raide_liodn_tbl, raide_liodn_tbl_sz);
+#endif
 }
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 758e6d7045..ffc2a9ad65 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -221,14 +221,14 @@ ulong get_spin_virt_addr(void)
 #ifdef CONFIG_FSL_CORENET
 static void plat_mp_up(unsigned long bootpg)
 {
-	u32 up, cpu_up_mask, whoami;
+	u32 cpu_up_mask, whoami;
 	u32 *table = (u32 *)get_spin_virt_addr();
 	volatile ccsr_gur_t *gur;
 	volatile ccsr_local_t *ccm;
 	volatile ccsr_rcpm_t *rcpm;
 	volatile ccsr_pic_t *pic;
 	int timeout = 10;
-	u32 nr_cpus;
+	u32 mask = cpu_mask();
 	struct law_entry e;
 
 	gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -236,8 +236,6 @@ static void plat_mp_up(unsigned long bootpg)
 	rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
 	pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 
-	nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1;
-
 	whoami = in_be32(&pic->whoami);
 	cpu_up_mask = 1 << whoami;
 	out_be32(&ccm->bstrl, bootpg);
@@ -251,19 +249,18 @@ static void plat_mp_up(unsigned long bootpg)
 	/* disable time base at the platform */
 	out_be32(&rcpm->ctbenrl, cpu_up_mask);
 
-	/* release the hounds */
-	up = ((1 << nr_cpus) - 1);
-	out_be32(&gur->brrl, up);
+	out_be32(&gur->brrl, mask);
 
 	/* wait for everyone */
 	while (timeout) {
-		int i;
-		for (i = 0; i < nr_cpus; i++) {
-			if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
-				cpu_up_mask |= (1 << i);
-		};
+		unsigned int i, cpu, nr_cpus = cpu_numcores();
 
-		if ((cpu_up_mask & up) == up)
+		for_each_cpu(i, cpu, nr_cpus, mask) {
+			if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
+				cpu_up_mask |= (1 << cpu);
+		}
+
+		if ((cpu_up_mask & mask) == mask)
 			break;
 
 		udelay(100);
@@ -272,7 +269,7 @@ static void plat_mp_up(unsigned long bootpg)
 
 	if (timeout == 0)
 		printf("CPU up timeout. CPU up mask is %x should be %x\n",
-			cpu_up_mask, up);
+			cpu_up_mask, mask);
 
 	/* enable time base at the platform */
 	out_be32(&rcpm->ctbenrl, 0);
@@ -283,7 +280,7 @@ static void plat_mp_up(unsigned long bootpg)
 	mtspr(SPRN_TBWU, 0);
 	mtspr(SPRN_TBWL, 0);
 
-	out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
+	out_be32(&rcpm->ctbenrl, mask);
 
 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
 	/*
diff --git a/arch/powerpc/cpu/mpc85xx/p3060_ids.c b/arch/powerpc/cpu/mpc85xx/p3060_ids.c
new file mode 100644
index 0000000000..07703d44eb
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p3060_ids.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+	/* dqrr liodn, frame data liodn, liodn off, sdest */
+	SET_QP_INFO( 1,  2,  1, 0),
+	SET_QP_INFO( 3,  4,  2, 1),
+	SET_QP_INFO( 5,  6,  3, 2),
+	SET_QP_INFO( 7,  8,  4, 3),
+	SET_QP_INFO( 9, 10,  5, 4),
+	SET_QP_INFO(11, 12,  6, 5),
+	SET_QP_INFO(13, 14,  7, 6),
+	SET_QP_INFO(15, 16,  8, 7),
+	SET_QP_INFO(17, 18,  9, 0), /* for now sdest to 0 */
+	SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */
+};
+#endif
+
+struct liodn_id_table liodn_tbl[] = {
+	SET_USB_LIODN(1, "fsl-usb2-mph", 127),
+	SET_USB_LIODN(2, "fsl-usb2-dr", 157),
+
+	SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193),
+	SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194),
+
+	SET_DMA_LIODN(1, 196),
+	SET_DMA_LIODN(2, 197),
+
+	SET_GUTS_LIODN("fsl,rapidio-delta", 198, rio1liodnr, 0),
+	SET_GUTS_LIODN(NULL, 199, rio2liodnr, 0),
+	SET_GUTS_LIODN(NULL, 200, rmuliodnr, 0),
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	SET_QMAN_LIODN(31),
+	SET_BMAN_LIODN(32),
+#endif
+	SET_PME_LIODN(128),
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(1, 0, 11),
+	SET_FMAN_RX_1G_LIODN(1, 1, 12),
+	SET_FMAN_RX_1G_LIODN(1, 2, 13),
+	SET_FMAN_RX_1G_LIODN(1, 3, 14),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+struct liodn_id_table fman2_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(2, 0, 16),
+	SET_FMAN_RX_1G_LIODN(2, 1, 17),
+	SET_FMAN_RX_1G_LIODN(2, 2, 18),
+	SET_FMAN_RX_1G_LIODN(2, 3, 19),
+};
+int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
+#endif
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+	SET_SEC_JR_LIODN_ENTRY(0, 146, 154),
+	SET_SEC_JR_LIODN_ENTRY(1, 147, 155),
+	SET_SEC_JR_LIODN_ENTRY(2, 178, 186),
+	SET_SEC_JR_LIODN_ENTRY(3, 179, 187),
+	SET_SEC_RTIC_LIODN_ENTRY(a, 144),
+	SET_SEC_RTIC_LIODN_ENTRY(b, 145),
+	SET_SEC_RTIC_LIODN_ENTRY(c, 176),
+	SET_SEC_RTIC_LIODN_ENTRY(d, 177),
+	SET_SEC_DECO_LIODN_ENTRY(0, 129, 161),
+	SET_SEC_DECO_LIODN_ENTRY(1, 130, 162),
+	SET_SEC_DECO_LIODN_ENTRY(2, 131, 163),
+	SET_SEC_DECO_LIODN_ENTRY(3, 132, 164),
+	SET_SEC_DECO_LIODN_ENTRY(4, 133, 165),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+struct liodn_id_table liodn_bases[] = {
+	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(96, 106),
+#ifdef CONFIG_SYS_DPAA_FMAN
+	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	[FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64),
+#endif
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+	[FSL_HW_PORTAL_PME]   = SET_LIODN_BASE_2(116, 133),
+#endif
+};
diff --git a/arch/powerpc/cpu/mpc85xx/p3060_serdes.c b/arch/powerpc/cpu/mpc85xx/p3060_serdes.c
new file mode 100644
index 0000000000..6387276bab
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p3060_serdes.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet_serdes.h"
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+	[0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+		  SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC1,
+		  SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2,
+		  NONE, NONE, AURORA, AURORA},
+	[0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SGMII_FM2_DTSEC3,
+		  SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4,
+		  SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2,
+		  SGMII_FM1_DTSEC2, NONE, NONE, AURORA, AURORA},
+	[0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+		  AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1,
+		  SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3,
+		  SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
+	[0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+		  AURORA, AURORA, PCIE2, PCIE2, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
+		  SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
+	[0x1c] = {NONE, NONE, SRIO1, SRIO2,  NONE, NONE, NONE, NONE,
+		  AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1,
+		  SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3,
+		  SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
+};
+
+enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
+{
+	if (!serdes_lane_enabled(lane))
+		return NONE;
+
+	return serdes_cfg_tbl[cfg][lane];
+}
+
+int is_serdes_prtcl_valid(u32 prtcl)
+{
+	int i;
+
+	if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (serdes_cfg_tbl[prtcl][i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
+
+void soc_serdes_init(void)
+{
+	/*
+	 * On the P3060 the devdisr2 register does not correctly reflect
+	 * the state of the MACs based on the RCW fields. So disable the MACs
+	 * based on the srds_prtcl and ec1, ec2, ec3 fields
+	 */
+
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 devdisr2 = in_be32(&gur->devdisr2);
+	u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
+	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+	u32 ec1_ext, ec2_ext;
+
+	/* NOTE: Leave FM1-1,FM1-2 alone for MDIO access */
+
+	if (!is_serdes_configured(SGMII_FM1_DTSEC3))
+		devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_3;
+
+	if (!is_serdes_configured(SGMII_FM1_DTSEC4))
+		devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_4;
+
+	if (!is_serdes_configured(SGMII_FM2_DTSEC1))
+		devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_1;
+
+	if (!is_serdes_configured(SGMII_FM2_DTSEC2))
+		devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_2;
+
+	if (!is_serdes_configured(SGMII_FM2_DTSEC3))
+		devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_3;
+
+	if (!is_serdes_configured(SGMII_FM2_DTSEC4))
+		devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_4;
+
+	if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
+		FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) {
+		devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC1_2;
+	}
+
+	if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
+		FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1) {
+		devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_1;
+	}
+
+	ec1_ext = rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT;
+	if (ec1_ext) {
+		if ((ec1_ext == FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII) ||
+			(ec1_ext == FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII))
+			devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC1_4;
+	}
+
+	ec2_ext = rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT;
+	if (ec2_ext) {
+		if ((ec2_ext == FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII) ||
+			(ec2_ext == FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII))
+			devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_4;
+	}
+
+	if ((rcwsr13 & FSL_CORENET_RCWSR13_EC3) ==
+		FSL_CORENET_RCWSR13_EC3_FM2_DTSEC4_MII)
+		devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_4;
+
+	out_be32(&gur->devdisr2, devdisr2);
+}
diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c
index 98365888ae..2911c13884 100644
--- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c
@@ -97,6 +97,16 @@ struct liodn_id_table sec_liodn_tbl[] = {
 };
 int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
 
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+struct liodn_id_table raide_liodn_tbl[] = {
+	SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60),
+	SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61),
+	SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62),
+	SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63),
+};
+int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl);
+#endif
+
 struct liodn_id_table liodn_bases[] = {
 	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(64, 100),
 #ifdef CONFIG_SYS_DPAA_FMAN
@@ -105,4 +115,7 @@ struct liodn_id_table liodn_bases[] = {
 #ifdef CONFIG_SYS_DPAA_PME
 	[FSL_HW_PORTAL_PME]   = SET_LIODN_BASE_2(136, 172),
 #endif
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+	[FSL_HW_PORTAL_RAID_ENGINE]  = SET_LIODN_BASE_1(47),
+#endif
 };
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c
index ecaa30de84..418dd9d9ea 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -151,7 +151,7 @@ static int fdt_qportal(void *blob, int off, int id, char *name,
 			dev_handle = fdt_get_phandle(blob, dev_off);
 			if (dev_handle <= 0) {
 				dev_handle = fdt_alloc_phandle(blob);
-				ret = fdt_create_phandle(blob, dev_off,
+				ret = fdt_set_phandle(blob, dev_off,
 							 dev_handle);
 				if (ret < 0)
 					return ret;
@@ -198,7 +198,10 @@ void fdt_fixup_qportals(void *blob)
 		u32 liodns[2];
 #endif
 		const int *ci = fdt_getprop(blob, off, "cell-index", NULL);
-		int j, i = *ci;
+		int i = *ci;
+#ifdef CONFIG_SYS_DPAA_FMAN
+		int j;
+#endif
 
 		err = fdt_setprop(blob, off, "compatible", compat, compat_len);
 		if (err < 0)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index a83dfeb84c..ce47532455 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -41,6 +41,7 @@ void get_sys_info (sys_info_t * sysInfo)
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #ifdef CONFIG_FSL_CORENET
 	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
+	unsigned int cpu;
 
 	const u8 core_cplx_PLL[16] = {
 		[ 0] = 0,	/* CC1 PPL / 1 */
@@ -97,11 +98,11 @@ void get_sys_info (sys_info_t * sysInfo)
 			freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
 	}
 	rcw_tmp = in_be32(&gur->rcwsr[3]);
-	for (i = 0; i < cpu_numcores(); i++) {
-		u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;
+	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
+		u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
 		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
 
-		sysInfo->freqProcessor[i] =
+		sysInfo->freqProcessor[cpu] =
 			 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
 	}
 
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 878a3d67e8..5e0d78d006 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -83,6 +83,45 @@
 
 _start_e500:
 
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
+	/* ISBC uses L2 as stack.
+	 * Disable L2 cache here so that u-boot can enable it later
+	 * as part of it's normal flow
+	*/
+
+	/* Check if L2 is enabled */
+	mfspr	r3, SPRN_L2CSR0
+	lis	r2, L2CSR0_L2E@h
+	ori	r2, r2, L2CSR0_L2E@l
+	and.	r4, r3, r2
+	beq	l2_disabled
+
+	mfspr r3, SPRN_L2CSR0
+	/* Flush L2 cache */
+	lis     r2,(L2CSR0_L2FL)@h
+	ori     r2, r2, (L2CSR0_L2FL)@l
+	or      r3, r2, r3
+	sync
+	isync
+	mtspr   SPRN_L2CSR0,r3
+	isync
+1:
+	mfspr r3, SPRN_L2CSR0
+	and. r1, r3, r2
+	bne 1b
+
+	mfspr r3, SPRN_L2CSR0
+	lis r2, L2CSR0_L2E@h
+	ori r2, r2, L2CSR0_L2E@l
+	andc r4, r3, r2
+	sync
+	isync
+	mtspr SPRN_L2CSR0,r4
+	isync
+
+l2_disabled:
+#endif
+
 /* clear registers/arrays not reset by hardware */
 
 	/* L1 */
@@ -279,10 +318,244 @@ _start_e500:
 
 #endif /* CONFIG_MPC8569 */
 
+/*
+ * Relocate CCSR, if necessary.  We relocate CCSR if (obviously) the default
+ * location is not where we want it.  This typically happens on a 36-bit
+ * system, where we want to move CCSR to near the top of 36-bit address space.
+ *
+ * To move CCSR, we create two temporary TLBs, one for the old location, and
+ * another for the new location.  On CoreNet systems, we also need to create
+ * a special, temporary LAW.
+ *
+ * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
+ * long-term TLBs, so we use TLB0 here.
+ */
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
+
+#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
+#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
+#endif
+
+purge_old_ccsr_tlb:
+	lis	r8, CONFIG_SYS_CCSRBAR@h
+	ori	r8, r8, CONFIG_SYS_CCSRBAR@l
+	lis	r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
+	ori	r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
+
+	/*
+	 * In a multi-stage boot (e.g. NAND boot), a previous stage may have
+	 * created a TLB for CCSR, which will interfere with our relocation
+	 * code.  Since we're going to create a new TLB for CCSR anyway,
+	 * it should be safe to delete this old TLB here.  We have to search
+	 * for it, though.
+	 */
+
+	li	r1, 0
+	mtspr	MAS6, r1	/* Search the current address space and PID */
+	tlbsx	0, r8
+	mfspr	r1, MAS1
+	andis.  r2, r1, MAS1_VALID@h	/* Check for the Valid bit */
+	beq     1f			/* Skip if no TLB found */
+
+	rlwinm	r1, r1, 0, 1, 31	/* Clear Valid bit */
+	mtspr	MAS1, r1
+	tlbwe
+1:
+
+create_ccsr_new_tlb:
+	/*
+	 * Create a TLB for the new location of CCSR.  Register R8 is reserved
+	 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
+	 */
+	lis     r0, FSL_BOOKE_MAS0(0, 0, 0)@h
+	ori     r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
+	lis     r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
+	ori     r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
+	lis     r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
+	ori     r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
+	lis     r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
+	ori     r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
+	lis	r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
+	ori	r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
+	mtspr   MAS0, r0
+	mtspr   MAS1, r1
+	mtspr   MAS2, r2
+	mtspr   MAS3, r3
+	mtspr   MAS7, r7
+	isync
+	msync
+	tlbwe
+
+	/*
+	 * Create a TLB for the old location of CCSR.  Register R9 is reserved
+	 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
+	 */
+create_ccsr_old_tlb:
+	lis     r0, FSL_BOOKE_MAS0(0, 1, 0)@h
+	ori     r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
+	lis     r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
+	ori     r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
+	lis     r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h
+	ori     r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l
+	li	r7, 0	/* The default CCSR address is always a 32-bit number */
+	mtspr   MAS0, r0
+	/* MAS1 is the same as above */
+	mtspr   MAS2, r2
+	mtspr   MAS3, r3
+	mtspr   MAS7, r7
+	isync
+	msync
+	tlbwe
+
+#ifdef CONFIG_FSL_CORENET
+
+#define CCSR_LAWBARH0	(CONFIG_SYS_CCSRBAR + 0x1000)
+#define LAW_EN		0x80000000
+#define LAW_SIZE_4K	0xb
+#define CCSRBAR_LAWAR	(LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
+#define CCSRAR_C	0x80000000	/* Commit */
+
+create_temp_law:
+	/*
+	 * On CoreNet systems, we create the temporary LAW using a special LAW
+	 * target ID of 0x1e.  LAWBARH is at offset 0xc00 in CCSR.
+	 */
+	lis     r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
+	ori     r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
+	lis     r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
+	ori     r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
+	lis     r2, CCSRBAR_LAWAR@h
+	ori     r2, r2, CCSRBAR_LAWAR@l
+
+	stw     r0, 0xc00(r9)	/* LAWBARH0 */
+	stw     r1, 0xc04(r9)	/* LAWBARL0 */
+	sync
+	stw     r2, 0xc08(r9)	/* LAWAR0 */
+
+	/*
+	 * Read back from LAWAR to ensure the update is complete.  e500mc
+	 * cores also require an isync.
+	 */
+	lwz	r0, 0xc08(r9)	/* LAWAR0 */
+	isync
+
+	/*
+	 * Read the current CCSRBARH and CCSRBARL using load word instructions.
+	 * Follow this with an isync instruction. This forces any outstanding
+	 * accesses to configuration space to completion.
+	 */
+read_old_ccsrbar:
+	lwz	r0, 0(r9)	/* CCSRBARH */
+	lwz	r0, 4(r9)	/* CCSRBARH */
+	isync
+
+	/*
+	 * Write the new values for CCSRBARH and CCSRBARL to their old
+	 * locations.  The CCSRBARH has a shadow register. When the CCSRBARH
+	 * has a new value written it loads a CCSRBARH shadow register. When
+	 * the CCSRBARL is written, the CCSRBARH shadow register contents
+	 * along with the CCSRBARL value are loaded into the CCSRBARH and
+	 * CCSRBARL registers, respectively.  Follow this with a sync
+	 * instruction.
+	 */
+write_new_ccsrbar:
+	lis	r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
+	ori	r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
+	lis	r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
+	ori	r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
+	lis	r2, CCSRAR_C@h
+	ori	r2, r2, CCSRAR_C@l
+
+	stw	r0, 0(r9)	/* Write to CCSRBARH */
+	sync			/* Make sure we write to CCSRBARH first */
+	stw	r1, 4(r9)	/* Write to CCSRBARL */
+	sync
+
+	/*
+	 * Write a 1 to the commit bit (C) of CCSRAR at the old location.
+	 * Follow this with a sync instruction.
+	 */
+	stw	r2, 8(r9)
+	sync
+
+	/* Delete the temporary LAW */
+delete_temp_law:
+	li	r1, 0
+	stw	r1, 0xc08(r8)
+	sync
+	stw	r1, 0xc00(r8)
+	stw	r1, 0xc04(r8)
+	sync
+
+#else /* #ifdef CONFIG_FSL_CORENET */
+
+write_new_ccsrbar:
+	/*
+	 * Read the current value of CCSRBAR using a load word instruction
+	 * followed by an isync. This forces all accesses to configuration
+	 * space to complete.
+	 */
+	sync
+	lwz	r0, 0(r9)
+	isync
+
+/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
+#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
+			   (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
+
+	/* Write the new value to CCSRBAR. */
+	lis	r0, CCSRBAR_PHYS_RS12@h
+	ori	r0, r0, CCSRBAR_PHYS_RS12@l
+	stw	r0, 0(r9)
+	sync
+
+	/*
+	 * The manual says to perform a load of an address that does not
+	 * access configuration space or the on-chip SRAM using an existing TLB,
+	 * but that doesn't appear to be necessary.  We will do the isync,
+	 * though.
+	 */
+	isync
+
+	/*
+	 * Read the contents of CCSRBAR from its new location, followed by
+	 * another isync.
+	 */
+	lwz	r0, 0(r8)
+	isync
+
+#endif  /* #ifdef CONFIG_FSL_CORENET */
+
+	/* Delete the temporary TLBs */
+delete_temp_tlbs:
+	lis     r0, FSL_BOOKE_MAS0(0, 0, 0)@h
+	ori     r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
+	li	r1, 0
+	lis     r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
+	ori     r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
+	mtspr   MAS0, r0
+	mtspr   MAS1, r1
+	mtspr   MAS2, r2
+	isync
+	msync
+	tlbwe
+
+	lis     r0, FSL_BOOKE_MAS0(0, 1, 0)@h
+	ori     r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
+	lis     r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
+	ori     r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
+	mtspr   MAS0, r0
+	mtspr   MAS2, r2
+	isync
+	msync
+	tlbwe
+#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
+
+create_init_ram_area:
 	lis     r6,FSL_BOOKE_MAS0(1, 15, 0)@h
 	ori     r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
 
-#ifndef CONFIG_SYS_RAMBOOT
+#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
 	/* create a temp mapping in AS=1 to the 4M boot window */
 	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
 	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
@@ -293,6 +566,20 @@ _start_e500:
 	/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
 	lis     r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
 	ori     r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
+	/* create a temp mapping in AS = 1 for Flash mapping
+	 * created by PBL for ISBC code
+	*/
+	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
+	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
+
+	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
+	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
+
+	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
+						(MAS3_SX|MAS3_SW|MAS3_SR))@h
+	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
+						(MAS3_SX|MAS3_SW|MAS3_SR))@l
 #else
 	/*
 	 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
index 8410bd7979..852f9aa4a3 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
@@ -23,6 +23,8 @@
  * MA 02111-1307 USA
  */
 
+#include "config.h"	/* CONFIG_BOARDDIR */
+
 OUTPUT_ARCH(powerpc)
 SECTIONS
 {
@@ -52,8 +54,18 @@ SECTIONS
 	. = ALIGN(8);
 	__init_begin = .;
 	__init_end = .;
-
-	.resetvec ADDR(.text) + 0xffc : {
+#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
+	.bootpg ADDR(.text) + 0x1000 :
+	{
+		start.o	(.bootpg)
+	}
+#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
+#elif defined(CONFIG_FSL_ELBC)
+#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
+#else
+#error unknown NAND controller
+#endif
+	.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
 		KEEP(*(.resetvec))
 	} = 0xffff
 
@@ -64,4 +76,4 @@ SECTIONS
 	}
 	__bss_end__ = .;
 }
-ASSERT(__init_end <= 0xfff00ffc, "NAND bootstrap too big");
+ASSERT(__init_end <= (0xfff00000 + RESET_VECTOR_OFFSET), "NAND bootstrap too big");
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 767bc524d1..0365ca8aa2 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <command.h>
 #include <tsec.h>
+#include <fm_eth.h>
 #include <netdev.h>
 #include <asm/cache.h>
 #include <asm/io.h>
@@ -102,6 +103,8 @@ struct cpu_type cpu_type_list [] = {
 	CPU_TYPE_ENTRY(P2041, P2041_E, 4),
 	CPU_TYPE_ENTRY(P3041, P3041, 4),
 	CPU_TYPE_ENTRY(P3041, P3041_E, 4),
+	CPU_TYPE_ENTRY_MASK(P3060, P3060, 6, 0xf3),
+	CPU_TYPE_ENTRY_MASK(P3060, P3060_E, 6, 0xf3),
 	CPU_TYPE_ENTRY(P4040, P4040, 4),
 	CPU_TYPE_ENTRY(P4040, P4040_E, 4),
 	CPU_TYPE_ENTRY(P4080, P4080, 8),
@@ -129,13 +132,33 @@ struct cpu_type *identify_cpu(u32 ver)
 	return &cpu_type_unknown;
 }
 
+#define MPC8xxx_PICFRR_NCPU_MASK  0x00001f00
+#define MPC8xxx_PICFRR_NCPU_SHIFT 8
+
+/*
+ * Return a 32-bit mask indicating which cores are present on this SOC.
+ */
+u32 cpu_mask()
+{
+	ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
+	struct cpu_type *cpu = gd->cpu;
+
+	/* better to query feature reporting register than just assume 1 */
+	if (cpu == &cpu_type_unknown)
+	return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
+			MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
+
+	return cpu->mask;
+}
+
+/*
+ * Return the number of cores on this SOC.
+ */
 int cpu_numcores() {
 	ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
 	struct cpu_type *cpu = gd->cpu;
 
 	/* better to query feature reporting register than just assume 1 */
-#define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00
-#define MPC8xxx_PICFRR_NCPU_SHIFT 8
 	if (cpu == &cpu_type_unknown)
 		return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
 			MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
@@ -143,6 +166,18 @@ int cpu_numcores() {
 	return cpu->num_cores;
 }
 
+/*
+ * Check if the given core ID is valid
+ *
+ * Returns zero if it isn't, 1 if it is.
+ */
+int is_core_valid(unsigned int core)
+{
+	struct cpu_type *cpu = gd->cpu;
+
+	return !!((1 << core) & cpu->mask);
+}
+
 int probecpu (void)
 {
 	uint svr;
@@ -174,5 +209,8 @@ int cpu_eth_init(bd_t *bis)
 	tsec_standard_init(bis);
 #endif
 
+#ifdef CONFIG_FMAN_ENET
+	fm_standard_init(bis);
+#endif
 	return 0;
 }
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 3824aade89..15cd375ae3 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -18,7 +18,9 @@
 
 #include "ddr.h"
 
-#ifdef CONFIG_MPC85xx
+#ifdef CONFIG_MPC83xx
+	#define _DDR_ADDR CONFIG_SYS_MPC83xx_DDR_ADDR
+#elif defined(CONFIG_MPC85xx)
 	#define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
 #elif defined(CONFIG_MPC86xx)
 	#define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
@@ -94,6 +96,10 @@ static inline int fsl_ddr_get_rtt(void)
  *       6 if 2.5ns > tCK >= 1.875ns
  *       7 if 1.875ns > tCK >= 1.5ns
  *       8 if 1.5ns > tCK >= 1.25ns
+ *       9 if 1.25ns > tCK >= 1.07ns
+ *       10 if 1.07ns > tCK >= 0.935ns
+ *       11 if 0.935ns > tCK >= 0.833ns
+ *       12 if 0.833ns > tCK >= 0.75ns
  */
 static inline unsigned int compute_cas_write_latency(void)
 {
@@ -108,8 +114,18 @@ static inline unsigned int compute_cas_write_latency(void)
 		cwl = 7;
 	else if (mclk_ps >= 1250)
 		cwl = 8;
-	else
-		cwl = 8;
+	else if (mclk_ps >= 1070)
+		cwl = 9;
+	else if (mclk_ps >= 935)
+		cwl = 10;
+	else if (mclk_ps >= 833)
+		cwl = 11;
+	else if (mclk_ps >= 750)
+		cwl = 12;
+	else {
+		cwl = 12;
+		printf("Warning: CWL is out of range\n");
+	}
 	return cwl;
 }
 
@@ -146,7 +162,7 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 		break;
 	case 2:
 		if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
-		   (dimm_number > 1 && dimm_params[dimm_number].n_ranks > 0))
+		   (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 			go_config = 1;
 		break;
 	case 3:
@@ -617,7 +633,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int sr_ie = 0;		/* Self-refresh interrupt enable */
 	unsigned int dll_rst_dis;	/* DLL reset disable */
 	unsigned int dqs_cfg;		/* DQS configuration */
-	unsigned int odt_cfg;		/* ODT configuration */
+	unsigned int odt_cfg = 0;	/* ODT configuration */
 	unsigned int num_pr;		/* Number of posted refreshes */
 	unsigned int obc_cfg;		/* On-The-Fly Burst Chop Cfg */
 	unsigned int ap_en;		/* Address Parity Enable */
@@ -625,15 +641,16 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int rcw_en = 0;	/* Register Control Word Enable */
 	unsigned int md_en = 0;		/* Mirrored DIMM Enable */
 	unsigned int qd_en = 0;		/* quad-rank DIMM Enable */
+	int i;
 
 	dll_rst_dis = 1;	/* Make this configurable */
 	dqs_cfg = popts->DQS_config;
-	if (popts->cs_local_opts[0].odt_rd_cfg
-	    || popts->cs_local_opts[0].odt_wr_cfg) {
-		/* FIXME */
-		odt_cfg = 2;
-	} else {
-		odt_cfg = 0;
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (popts->cs_local_opts[i].odt_rd_cfg
+			|| popts->cs_local_opts[i].odt_wr_cfg) {
+			odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
+			break;
+		}
 	}
 
 	num_pr = 1;	/* Make this configurable */
@@ -1018,7 +1035,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 #if defined(CONFIG_FSL_DDR2)
 	const unsigned int mclk_ps = get_memory_clk_period_ps();
 #endif
-
+	dqs_en = !popts->DQS_config;
 	rtt = fsl_ddr_get_rtt();
 
 	al = additive_latency;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index 8132e68d9d..20c7db03ed 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -448,7 +448,8 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 
 #if defined(CONFIG_FSL_DDR2)
 	if (lowest_good_caslat < 4) {
-		additive_latency = picos_to_mclk(tRCD_ps) - lowest_good_caslat;
+		additive_latency = (picos_to_mclk(tRCD_ps) > lowest_good_caslat)
+			? picos_to_mclk(tRCD_ps) - lowest_good_caslat : 0;
 		if (mclk_to_picos(additive_latency) > tRCD_ps) {
 			additive_latency = picos_to_mclk(tRCD_ps);
 			debug("setting additive_latency to %u because it was "
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 249fd7dfb3..5699b0c2cc 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -34,14 +34,17 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
 	[0][0] = SPD_EEPROM_ADDRESS,
 };
-#endif
-#if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+#elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
+	[0][1] = SPD_EEPROM_ADDRESS2,	/* controller 1 */
+};
+#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
 	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
 	[1][0] = SPD_EEPROM_ADDRESS2,	/* controller 2 */
 };
-#endif
-#if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
 	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
 	[0][1] = SPD_EEPROM_ADDRESS2,	/* controller 1 */
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
index bd9c4663e7..4dc748b951 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
@@ -26,14 +26,15 @@ extern void fsl_ddr_board_options(memctl_options_t *popts,
 		dimm_params_t *pdimm,
 		unsigned int ctrl_num);
 
-typedef struct {
+struct dynamic_odt {
 	unsigned int odt_rd_cfg;
 	unsigned int odt_wr_cfg;
 	unsigned int odt_rtt_norm;
 	unsigned int odt_rtt_wr;
-} dynamic_odt_t;
+};
 
-static const dynamic_odt_t single_Q[4] = {
+#ifdef CONFIG_FSL_DDR3
+static const struct dynamic_odt single_Q[4] = {
 	{	/* cs0 */
 		FSL_DDR_ODT_NEVER,
 		FSL_DDR_ODT_CS_AND_OTHER_DIMM,
@@ -60,7 +61,7 @@ static const dynamic_odt_t single_Q[4] = {
 	}
 };
 
-static const dynamic_odt_t single_D[4] = {
+static const struct dynamic_odt single_D[4] = {
 	{	/* cs0 */
 		FSL_DDR_ODT_NEVER,
 		FSL_DDR_ODT_ALL,
@@ -77,7 +78,7 @@ static const dynamic_odt_t single_D[4] = {
 	{0, 0, 0, 0}
 };
 
-static const dynamic_odt_t single_S[4] = {
+static const struct dynamic_odt single_S[4] = {
 	{	/* cs0 */
 		FSL_DDR_ODT_NEVER,
 		FSL_DDR_ODT_ALL,
@@ -89,7 +90,7 @@ static const dynamic_odt_t single_S[4] = {
 	{0, 0, 0, 0},
 };
 
-static const dynamic_odt_t dual_DD[4] = {
+static const struct dynamic_odt dual_DD[4] = {
 	{	/* cs0 */
 		FSL_DDR_ODT_NEVER,
 		FSL_DDR_ODT_SAME_DIMM,
@@ -116,7 +117,7 @@ static const dynamic_odt_t dual_DD[4] = {
 	}
 };
 
-static const dynamic_odt_t dual_DS[4] = {
+static const struct dynamic_odt dual_DS[4] = {
 	{	/* cs0 */
 		FSL_DDR_ODT_NEVER,
 		FSL_DDR_ODT_SAME_DIMM,
@@ -137,7 +138,7 @@ static const dynamic_odt_t dual_DS[4] = {
 	},
 	{0, 0, 0, 0}
 };
-static const dynamic_odt_t dual_SD[4] = {
+static const struct dynamic_odt dual_SD[4] = {
 	{	/* cs0 */
 		FSL_DDR_ODT_OTHER_DIMM,
 		FSL_DDR_ODT_ALL,
@@ -159,7 +160,7 @@ static const dynamic_odt_t dual_SD[4] = {
 	}
 };
 
-static const dynamic_odt_t dual_SS[4] = {
+static const struct dynamic_odt dual_SS[4] = {
 	{	/* cs0 */
 		FSL_DDR_ODT_OTHER_DIMM,
 		FSL_DDR_ODT_ALL,
@@ -176,7 +177,7 @@ static const dynamic_odt_t dual_SS[4] = {
 	{0, 0, 0, 0}
 };
 
-static const dynamic_odt_t dual_D0[4] = {
+static const struct dynamic_odt dual_D0[4] = {
 	{	/* cs0 */
 		FSL_DDR_ODT_NEVER,
 		FSL_DDR_ODT_SAME_DIMM,
@@ -193,7 +194,7 @@ static const dynamic_odt_t dual_D0[4] = {
 	{0, 0, 0, 0}
 };
 
-static const dynamic_odt_t dual_0D[4] = {
+static const struct dynamic_odt dual_0D[4] = {
 	{0, 0, 0, 0},
 	{0, 0, 0, 0},
 	{	/* cs2 */
@@ -210,7 +211,7 @@ static const dynamic_odt_t dual_0D[4] = {
 	}
 };
 
-static const dynamic_odt_t dual_S0[4] = {
+static const struct dynamic_odt dual_S0[4] = {
 	{	/* cs0 */
 		FSL_DDR_ODT_NEVER,
 		FSL_DDR_ODT_CS,
@@ -223,7 +224,7 @@ static const dynamic_odt_t dual_S0[4] = {
 
 };
 
-static const dynamic_odt_t dual_0S[4] = {
+static const struct dynamic_odt dual_0S[4] = {
 	{0, 0, 0, 0},
 	{0, 0, 0, 0},
 	{	/* cs2 */
@@ -236,7 +237,7 @@ static const dynamic_odt_t dual_0S[4] = {
 
 };
 
-static const dynamic_odt_t odt_unknown[4] = {
+static const struct dynamic_odt odt_unknown[4] = {
 	{	/* cs0 */
 		FSL_DDR_ODT_NEVER,
 		FSL_DDR_ODT_CS,
@@ -262,7 +263,218 @@ static const dynamic_odt_t odt_unknown[4] = {
 		DDR3_RTT_OFF
 	}
 };
+#else	/* CONFIG_FSL_DDR3 */
+static const struct dynamic_odt single_Q[4] = {
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0}
+};
+
+static const struct dynamic_odt single_D[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_ALL,
+		DDR2_RTT_150_OHM,
+		DDR2_RTT_OFF
+	},
+	{	/* cs1 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR2_RTT_OFF,
+		DDR2_RTT_OFF
+	},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0}
+};
 
+static const struct dynamic_odt single_S[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_ALL,
+		DDR2_RTT_150_OHM,
+		DDR2_RTT_OFF
+	},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+};
+
+static const struct dynamic_odt dual_DD[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{	/* cs1 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR2_RTT_OFF,
+		DDR2_RTT_OFF
+	},
+	{	/* cs2 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{	/* cs3 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR2_RTT_OFF,
+		DDR2_RTT_OFF
+	}
+};
+
+static const struct dynamic_odt dual_DS[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{	/* cs1 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR2_RTT_OFF,
+		DDR2_RTT_OFF
+	},
+	{	/* cs2 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{0, 0, 0, 0}
+};
+
+static const struct dynamic_odt dual_SD[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{0, 0, 0, 0},
+	{	/* cs2 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{	/* cs3 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR2_RTT_OFF,
+		DDR2_RTT_OFF
+	}
+};
+
+static const struct dynamic_odt dual_SS[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{0, 0, 0, 0},
+	{	/* cs2 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{0, 0, 0, 0}
+};
+
+static const struct dynamic_odt dual_D0[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_ALL,
+		DDR2_RTT_150_OHM,
+		DDR2_RTT_OFF
+	},
+	{	/* cs1 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR2_RTT_OFF,
+		DDR2_RTT_OFF
+	},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0}
+};
+
+static const struct dynamic_odt dual_0D[4] = {
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+	{	/* cs2 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_ALL,
+		DDR2_RTT_150_OHM,
+		DDR2_RTT_OFF
+	},
+	{	/* cs3 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR2_RTT_OFF,
+		DDR2_RTT_OFF
+	}
+};
+
+static const struct dynamic_odt dual_S0[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_CS,
+		DDR2_RTT_150_OHM,
+		DDR2_RTT_OFF
+	},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0}
+
+};
+
+static const struct dynamic_odt dual_0S[4] = {
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+	{	/* cs2 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_CS,
+		DDR2_RTT_150_OHM,
+		DDR2_RTT_OFF
+	},
+	{0, 0, 0, 0}
+
+};
+
+static const struct dynamic_odt odt_unknown[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_CS,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{	/* cs1 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR2_RTT_OFF,
+		DDR2_RTT_OFF
+	},
+	{	/* cs2 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_CS,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{	/* cs3 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR2_RTT_OFF,
+		DDR2_RTT_OFF
+	}
+};
+#endif
 unsigned int populate_memctl_options(int all_DIMMs_registered,
 			memctl_options_t *popts,
 			dimm_params_t *pdimm,
@@ -271,7 +483,8 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	unsigned int i;
 	char buffer[HWCONFIG_BUFFER_SIZE];
 	char *buf = NULL;
-	const dynamic_odt_t *pdodt = odt_unknown;
+	const struct dynamic_odt *pdodt = odt_unknown;
+	ulong ddr_freq;
 
 	/*
 	 * Extract hwconfig from environment since we have not properly setup
@@ -336,7 +549,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 
 	/* Pick chip-select local options. */
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-#if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
 		popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
 		popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
 		popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
@@ -716,6 +929,20 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	if (pdimm[0].n_ranks == 4)
 		popts->quad_rank_present = 1;
 
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	if (popts->registered_dimm_en) {
+		popts->rcw_override = 1;
+		popts->rcw_1 = 0x000a5a00;
+		if (ddr_freq <= 800)
+			popts->rcw_2 = 0x00000000;
+		else if (ddr_freq <= 1066)
+			popts->rcw_2 = 0x00100000;
+		else if (ddr_freq <= 1333)
+			popts->rcw_2 = 0x00200000;
+		else
+			popts->rcw_2 = 0x00300000;
+	}
+
 	fsl_ddr_board_options(popts, pdimm, ctrl_num);
 
 	return 0;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
index 104d360a5f..eb6a17a850 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
@@ -20,7 +20,8 @@
 #define ULL_8FS 0xFFFFFFFFULL
 
 /*
- * Round mclk_ps to nearest 10 ps in memory controller code.
+ * Round up mclk_ps to nearest 1 ps in memory controller code
+ * if the error is 0.5ps or more.
  *
  * If an imprecise data rate is too high due to rounding error
  * propagation, compute a suitably rounded mclk_ps to compute
@@ -32,42 +33,37 @@ unsigned int get_memory_clk_period_ps(void)
 	unsigned int result;
 
 	/* Round to nearest 10ps, being careful about 64-bit multiply/divide */
-	unsigned long long mclk_ps = ULL_2E12;
-
-	/* Add 5*data_rate, for rounding */
-	mclk_ps += 5*(unsigned long long)data_rate;
+	unsigned long long rem, mclk_ps = ULL_2E12;
 
 	/* Now perform the big divide, the result fits in 32-bits */
-	do_div(mclk_ps, data_rate);
-	result = mclk_ps;
+	rem = do_div(mclk_ps, data_rate);
+	result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
 
-	/* We still need to round to 10ps */
-	return 10 * (result/10);
+	return result;
 }
 
 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
 unsigned int picos_to_mclk(unsigned int picos)
 {
 	unsigned long long clks, clks_rem;
+	unsigned long data_rate = get_ddr_freq(0);
 
 	/* Short circuit for zero picos */
 	if (!picos)
 		return 0;
 
 	/* First multiply the time by the data rate (32x32 => 64) */
-	clks = picos * (unsigned long long)get_ddr_freq(0);
-
+	clks = picos * (unsigned long long)data_rate;
 	/*
 	 * Now divide by 5^12 and track the 32-bit remainder, then divide
 	 * by 2*(2^12) using shifts (and updating the remainder).
 	 */
 	clks_rem = do_div(clks, UL_5POW12);
-	clks_rem <<= 13;
-	clks_rem |= clks & (UL_2POW13-1);
+	clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
 	clks >>= 13;
 
-	/* If we had a remainder, then round up */
-	if (clks_rem)
+	/* If we had a remainder greater than the 1ps error, then round up */
+	if (clks_rem > data_rate)
 		clks++;
 
 	/* Clamp to the maximum representable value */
@@ -133,10 +129,13 @@ fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
 
 void board_add_ram_info(int use_default)
 {
-#if defined(CONFIG_MPC85xx)
-	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+#if defined(CONFIG_MPC83xx)
+	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	ccsr_ddr_t *ddr = (void *)&immap->ddr;
+#elif defined(CONFIG_MPC85xx)
+	ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 #elif defined(CONFIG_MPC86xx)
-	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
+	ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
 #endif
 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 	uint32_t cs0_config = in_be32(&ddr->cs0_config);
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 285051d96c..5bb9f53542 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -63,7 +63,7 @@ void ft_fixup_num_cores(void *blob) {
 	while (off != -FDT_ERR_NOTFOUND) {
 		u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
 
-		if ((*reg > num_cores-1) || (is_core_disabled(*reg))) {
+		if (!is_core_valid(*reg) || is_core_disabled(*reg)) {
 			int ph = fdt_get_phandle(blob, off);
 
 			/* Delete the cpu node once there are no cpu handles */
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
index e79482130e..66824960d3 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
@@ -43,10 +43,12 @@ void init_early_memctl_regs(void)
 	set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
 	set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
 
+#if !defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) || defined(CONFIG_SYS_RAMBOOT)
 	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
 	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
 	set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
 #endif
+#endif
 
 #if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
 	set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 9aad9be1b0..d138636939 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -42,7 +42,10 @@
 #define CONFIG_SYS_BOOT_GET_KBD
 
 #ifndef CONFIG_MAX_MEM_MAPPED
-#if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if	defined(CONFIG_4xx)		|| \
+	defined(CONFIG_E500)		|| \
+	defined(CONFIG_MPC86xx)		|| \
+	defined(CONFIG_E300)
 #define CONFIG_MAX_MEM_MAPPED	((phys_size_t)2 << 30)
 #else
 #define CONFIG_MAX_MEM_MAPPED	(256 << 20)
@@ -96,6 +99,11 @@
 #endif /* TSEC_ENET */
 #endif /* !CONFIG_PHYLIB */
 
+/* The FMAN driver uses the PHYLIB infrastructure */
+#if defined(CONFIG_FMAN_ENET)
+#define CONFIG_PHYLIB
+#endif
+
 /* All PPC boards must swap IDE bytes */
 #define CONFIG_IDE_SWAP_IO
 
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 04ca989b0e..c3d6ba9e99 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -23,6 +23,10 @@
 
 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
 
+#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
+#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
+#endif
+
 /* Number of TLB CAM entries we have on FSL Book-E chips */
 #if defined(CONFIG_E500MC)
 #define CONFIG_SYS_NUM_TLBCAMS		64
@@ -34,34 +38,43 @@
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8540)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		8
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8541)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		8
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8544)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		10
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8548)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		10
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
+#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 
 #elif defined(CONFIG_MPC8555)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		8
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8560)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		8
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8568)
 #define CONFIG_MAX_CPUS			1
@@ -70,6 +83,7 @@
 #define QE_MURAM_SIZE			0x10000UL
 #define MAX_QE_RISC			2
 #define QE_NUM_OF_SNUM			28
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8569)
 #define CONFIG_MAX_CPUS			1
@@ -78,11 +92,13 @@
 #define QE_MURAM_SIZE			0x20000UL
 #define MAX_QE_RISC			4
 #define QE_NUM_OF_SNUM			46
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8572)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 
@@ -97,6 +113,10 @@
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
+#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 
 /* P1011 is single core version of P1020 */
 #elif defined(CONFIG_P1011)
@@ -105,6 +125,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
@@ -115,6 +136,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define QE_MURAM_SIZE			0x6000UL
@@ -127,6 +149,7 @@
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_FSL_SATA_ERRATUM_A001
@@ -141,6 +164,10 @@
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
+#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 
 /* P1015 is single core version of P1024 */
 #elif defined(CONFIG_P1015)
@@ -149,6 +176,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
@@ -164,6 +192,7 @@
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 /* P1017 is single core version of P1023 */
 #elif defined(CONFIG_P1017)
@@ -177,6 +206,7 @@
 #define CONFIG_SYS_BMAN_NUM_PORTALS	3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff600000
 
 #elif defined(CONFIG_P1020)
 #define CONFIG_MAX_CPUS			2
@@ -184,6 +214,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
@@ -193,6 +224,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define QE_MURAM_SIZE			0x6000UL
@@ -204,6 +236,7 @@
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_FSL_SATA_ERRATUM_A001
@@ -219,6 +252,7 @@
 #define CONFIG_SYS_BMAN_NUM_PORTALS	3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff600000
 
 /* P1024 is lower end variant of P1020 */
 #elif defined(CONFIG_P1024)
@@ -227,6 +261,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
@@ -237,6 +272,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define QE_MURAM_SIZE			0x6000UL
@@ -248,6 +284,7 @@
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 
@@ -255,6 +292,7 @@
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 
@@ -269,8 +307,10 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #elif defined(CONFIG_PPC_P2041)
@@ -285,8 +325,10 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #elif defined(CONFIG_PPC_P3041)
@@ -301,10 +343,27 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
+#elif defined(CONFIG_PPC_P3060)
+#define CONFIG_MAX_CPUS			8
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	4
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		2
+#define CONFIG_SYS_NUM_FM1_DTSEC	4
+#define CONFIG_SYS_NUM_FM2_DTSEC	4
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
+
 #elif defined(CONFIG_PPC_P4040)
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
@@ -313,6 +372,7 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,p4080-pcie"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 
 #elif defined(CONFIG_PPC_P4080)
 #define CONFIG_MAX_CPUS			8
@@ -328,6 +388,7 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,p4080-pcie"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
@@ -354,8 +415,10 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #elif defined(CONFIG_PPC_P5020)
@@ -370,12 +433,18 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #else
 #error Processor type not defined for this platform
 #endif
 
+#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
+#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
+#endif
+
 #endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index bc063ea892..93639ba851 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -31,6 +31,11 @@
 #define DDR3_RTT_20_OHM		4 /* RTT_Nom = RZQ/12 */
 #define DDR3_RTT_30_OHM		5 /* RTT_Nom = RZQ/8 */
 
+#define DDR2_RTT_OFF		0
+#define DDR2_RTT_75_OHM		1
+#define DDR2_RTT_150_OHM	2
+#define DDR2_RTT_50_OHM		3
+
 #if defined(CONFIG_FSL_DDR1)
 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(1)
 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
@@ -92,6 +97,10 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 
 #define SDRAM_CFG2_D_INIT		0x00000010
 #define SDRAM_CFG2_ODT_CFG_MASK		0x00600000
+#define SDRAM_CFG2_ODT_NEVER		0
+#define SDRAM_CFG2_ODT_ONLY_WRITE	1
+#define SDRAM_CFG2_ODT_ONLY_READ	2
+#define SDRAM_CFG2_ODT_ALWAYS		3
 
 #define TIMING_CFG_2_CPO_MASK	0x0F800000
 
diff --git a/arch/powerpc/include/asm/fsl_dtsec.h b/arch/powerpc/include/asm/fsl_dtsec.h
new file mode 100644
index 0000000000..d1d993c5ac
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_dtsec.h
@@ -0,0 +1,244 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __DTSEC_H__
+#define __DTSEC_H__
+
+#include <asm/types.h>
+
+struct dtsec {
+	u32	tsec_id;	/* controller ID and version */
+	u32	tsec_id2;	/* controller ID and configuration */
+	u32	ievent;		/* interrupt event */
+	u32	imask;		/* interrupt mask */
+	u32	res0;
+	u32	ecntrl;		/* ethernet control and configuration */
+	u32	ptv;		/* pause time value */
+	u32	tbipa;		/* TBI PHY address */
+	u32	res1[8];
+	u32	tctrl;		/* Transmit control register */
+	u32	res2[3];
+	u32	rctrl;		/* Receive control register */
+	u32	res3[11];
+	u32	igaddr[8];	/* Individual group address */
+	u32	gaddr[8];	/* group address */
+	u32	res4[16];
+	u32	maccfg1;	/* MAC configuration register 1 */
+	u32	maccfg2;	/* MAC configuration register 2 */
+	u32	ipgifg;		/* inter-packet/inter-frame gap */
+	u32	hafdup;		/* half-duplex control */
+	u32	maxfrm;		/* Maximum frame size */
+	u32	res5[3];
+	u32	miimcfg;	/* MII management configuration */
+	u32	miimcom;	/* MII management command */
+	u32	miimadd;	/* MII management address */
+	u32	miimcon;	/* MII management control */
+	u32	miimstat;	/* MII management status */
+	u32	miimind;	/* MII management indicator */
+	u32	res6;
+	u32	ifstat;		/* Interface status */
+	u32	macstnaddr1;	/* MAC station address 1 */
+	u32	macstnaddr2;	/* MAC station address 2 */
+	u32	res7[46];
+	/* transmit and receive counter */
+	u32	tr64;		/* Tx and Rx 64 bytes frame */
+	u32	tr127;		/* Tx and Rx 65 to 127 bytes frame */
+	u32	tr255;		/* Tx and Rx 128 to 255 bytes frame */
+	u32	tr511;		/* Tx and Rx 256 to 511 bytes frame */
+	u32	tr1k;		/* Tx and Rx 512 to 1023 bytes frame */
+	u32	trmax;		/* Tx and Rx 1024 to 1518 bytes frame */
+	u32	trmgv;		/* Tx and Rx 1519 to 1522 good VLAN frame */
+	/* receive counters */
+	u32	rbyt;		/* Receive byte counter */
+	u32	rpkt;		/* Receive packet counter */
+	u32	rfcs;		/* Receive FCS error */
+	u32	rmca;		/* Receive multicast packet */
+	u32	rbca;		/* Receive broadcast packet */
+	u32	rxcf;		/* Receive control frame */
+	u32	rxpf;		/* Receive pause frame */
+	u32	rxuo;		/* Receive unknown OP code */
+	u32	raln;		/* Receive alignment error */
+	u32	rflr;		/* Receive frame length error */
+	u32	rcde;		/* Receive code error */
+	u32	rcse;		/* Receive carrier sense error */
+	u32	rund;		/* Receive undersize packet */
+	u32	rovr;		/* Receive oversize packet */
+	u32	rfrg;		/* Receive fragments counter */
+	u32	rjbr;		/* Receive jabber counter */
+	u32	rdrp;		/* Receive drop counter */
+	/* transmit counters */
+	u32	tbyt;		/* Transmit byte counter */
+	u32	tpkt;		/* Transmit packet */
+	u32	tmca;		/* Transmit multicast packet */
+	u32	tbca;		/* Transmit broadcast packet */
+	u32	txpf;		/* Transmit pause control frame */
+	u32	tdfr;		/* Transmit deferral packet */
+	u32	tedf;		/* Transmit excessive deferral pkt */
+	u32	tscl;		/* Transmit single collision pkt */
+	u32	tmcl;		/* Transmit multiple collision pkt */
+	u32	tlcl;		/* Transmit late collision pkt */
+	u32	txcl;		/* Transmit excessive collision */
+	u32	tncl;		/* Transmit total collision */
+	u32	res8;
+	u32	tdrp;		/* Transmit drop frame */
+	u32	tjbr;		/* Transmit jabber frame */
+	u32	tfcs;		/* Transmit FCS error */
+	u32	txcf;		/* Transmit control frame */
+	u32	tovr;		/* Transmit oversize frame */
+	u32	tund;		/* Transmit undersize frame */
+	u32	tfrg;		/* Transmit fragments frame */
+	/* counter controls */
+	u32	car1;		/* carry register 1 */
+	u32	car2;		/* carry register 2 */
+	u32	cam1;		/* carry register 1 mask */
+	u32	cam2;		/* carry register 2 mask */
+	u32	res9[80];
+};
+
+
+/* TBI register addresses */
+#define TBI_CR			0x00
+#define TBI_SR			0x01
+#define TBI_ANA			0x04
+#define TBI_ANLPBPA		0x05
+#define TBI_ANEX		0x06
+#define TBI_TBICON		0x11
+
+/* TBI MDIO register bit fields*/
+#define TBICON_CLK_SELECT	0x0020
+#define TBIANA_ASYMMETRIC_PAUSE 0x0100
+#define TBIANA_SYMMETRIC_PAUSE  0x0080
+#define TBIANA_HALF_DUPLEX	0x0040
+#define TBIANA_FULL_DUPLEX	0x0020
+#define TBICR_PHY_RESET		0x8000
+#define TBICR_ANEG_ENABLE	0x1000
+#define TBICR_RESTART_ANEG	0x0200
+#define TBICR_FULL_DUPLEX	0x0100
+#define TBICR_SPEED1_SET	0x0040
+
+/* IEVENT - interrupt events register */
+#define IEVENT_BABR	0x80000000 /* Babbling receive error */
+#define IEVENT_RXC	0x40000000 /* pause control frame received */
+#define IEVENT_MSRO	0x04000000 /* MIB counter overflow */
+#define IEVENT_GTSC	0x02000000 /* Graceful transmit stop complete */
+#define IEVENT_BABT	0x01000000 /* Babbling transmit error */
+#define IEVENT_TXC	0x00800000 /* control frame transmitted */
+#define IEVENT_TXE	0x00400000 /* Transmit channel error */
+#define IEVENT_LC	0x00040000 /* Late collision occurred */
+#define IEVENT_CRL	0x00020000 /* Collision retry exceed limit */
+#define IEVENT_XFUN	0x00010000 /* Transmit FIFO underrun */
+#define IEVENT_ABRT	0x00008000 /* Transmit packet abort */
+#define IEVENT_MMRD	0x00000400 /* MII management read complete */
+#define IEVENT_MMWR	0x00000200 /* MII management write complete */
+#define IEVENT_GRSC	0x00000100 /* Graceful stop complete */
+#define IEVENT_TDPE	0x00000002 /* Internal data parity error on Tx */
+#define IEVENT_RDPE	0x00000001 /* Internal data parity error on Rx */
+
+#define IEVENT_CLEAR_ALL	0xffffffff
+
+/* IMASK - interrupt mask register */
+#define IMASK_BREN	0x80000000 /* Babbling receive enable */
+#define IMASK_RXCEN	0x40000000 /* receive control enable */
+#define IMASK_MSROEN	0x04000000 /* MIB counter overflow enable */
+#define IMASK_GTSCEN	0x02000000 /* Graceful Tx stop complete enable */
+#define IMASK_BTEN	0x01000000 /* Babbling transmit error enable */
+#define IMASK_TXCEN	0x00800000 /* control frame transmitted enable */
+#define IMASK_TXEEN	0x00400000 /* Transmit channel error enable */
+#define IMASK_LCEN	0x00040000 /* Late collision interrupt enable */
+#define IMASK_CRLEN	0x00020000 /* Collision retry exceed limit */
+#define IMASK_XFUNEN	0x00010000 /* Transmit FIFO underrun enable */
+#define IMASK_ABRTEN	0x00008000 /* Transmit packet abort enable */
+#define IMASK_MMRDEN	0x00000400 /* MII management read complete enable */
+#define IMASK_MMWREN	0x00000200 /* MII management write complete enable */
+#define IMASK_GRSCEN	0x00000100 /* Graceful stop complete interrupt enable */
+#define IMASK_TDPEEN	0x00000002 /* Internal data parity error on Tx enable */
+#define IMASK_RDPEEN	0x00000001 /* Internal data parity error on Rx enable */
+
+#define IMASK_MASK_ALL	0x00000000
+
+/* ECNTRL - ethernet control register */
+#define ECNTRL_CFG_RO	0x80000000 /* GMIIM, RPM, R100M, SGMIIM bits are RO */
+#define ECNTRL_CLRCNT	0x00004000 /* clear all statistics */
+#define ECNTRL_AUTOZ	0x00002000 /* auto zero MIB counter */
+#define ECNTRL_STEN	0x00001000 /* enable internal counters to update */
+#define ECNTRL_GMIIM	0x00000040 /* 1- GMII or RGMII interface mode */
+#define ECNTRL_TBIM	0x00000020 /* 1- Ten-bit interface mode */
+#define ECNTRL_RPM	0x00000010 /* 1- RGMII reduced-pin mode */
+#define ECNTRL_R100M	0x00000008 /* 1- RGMII 100 Mbps, SGMII 100 Mbps
+				      0- RGMII 10 Mbps, SGMII 10 Mbps */
+#define ECNTRL_SGMIIM	0x00000002 /* 1- SGMII interface mode */
+#define ECNTRL_TBIM	0x00000020 /* 1- TBI Interface mode (for SGMII) */
+
+#define ECNTRL_DEFAULT	(ECNTRL_TBIM | ECNTRL_R100M | ECNTRL_SGMIIM)
+
+/* TCTRL - Transmit control register */
+#define TCTRL_THDF	0x00000800 /* Transmit half-duplex flow control */
+#define TCTRL_TTSE	0x00000040 /* Transmit time-stamp enable */
+#define TCTRL_GTS	0x00000020 /* Graceful transmit stop */
+#define TCTRL_RFC_PAUSE	0x00000010 /* Receive flow control pause frame */
+
+/* RCTRL - Receive control register */
+#define RCTRL_PAL_MASK	0x001f0000 /* packet alignment padding length */
+#define RCTRL_PAL_SHIFT	16
+#define RCTRL_CFA	0x00008000 /* control frame accept enable */
+#define RCTRL_GHTX	0x00000800 /* group address hash table extend */
+#define RCTRL_RTSE	0x00000040 /* receive 1588 time-stamp enable */
+#define RCTRL_GRS	0x00000020 /* graceful receive stop */
+#define RCTRL_BC_REJ	0x00000010 /* broadcast frame reject */
+#define RCTRL_BC_MPROM	0x00000008 /* all multicast/broadcast frames received */
+#define RCTRL_RSF	0x00000004 /* receive short frame(17~63 bytes) enable */
+#define RCTRL_EMEN	0x00000002 /* Exact match MAC address enable */
+#define RCTRL_UPROM	0x00000001 /* all unicast frame received */
+
+/* MACCFG1 - MAC configuration 1 register */
+#define MACCFG1_SOFT_RST	0x80000000 /* place the MAC in reset */
+#define MACCFG1_RST_RXMAC	0x00080000 /* reset receive MAC control block */
+#define MACCFG1_RST_TXMAC	0x00040000 /* reet transmit MAC control block */
+#define MACCFG1_RST_RXFUN	0x00020000 /* reset receive function block */
+#define MACCFG1_RST_TXFUN	0x00010000 /* reset transmit function block */
+#define MACCFG1_LOOPBACK	0x00000100 /* MAC loopback */
+#define MACCFG1_RX_FLOW		0x00000020 /* Receive flow */
+#define MACCFG1_TX_FLOW		0x00000010 /* Transmit flow */
+#define MACCFG1_SYNC_RXEN	0x00000008 /* Frame reception enabled */
+#define MACCFG1_RX_EN		0x00000004 /* Rx enable */
+#define MACCFG1_SYNC_TXEN	0x00000002 /* Frame transmission is enabled */
+#define MACCFG1_TX_EN		0x00000001 /* Tx enable */
+#define MACCFG1_RXTX_EN		(MACCFG1_RX_EN | MACCFG1_TX_EN)
+
+/* MACCFG2 - MAC configuration 2 register */
+#define MACCFG2_PRE_LEN_MASK	0x0000f000 /* preamble length */
+#define MACCFG2_PRE_LEN(x)	((x << 12) & MACCFG2_PRE_LEN_MASK)
+#define MACCFG2_IF_MODE_MASK	0x00000300
+#define MACCFG2_IF_MODE_NIBBLE	0x00000100 /* MII, 10/100 Mbps MII/RMII */
+#define MACCFG2_IF_MODE_BYTE	0x00000200 /* GMII/TBI, 1000 GMII/TBI */
+#define MACCFG2_PRE_RX_EN	0x00000080 /* receive preamble enable */
+#define MACCFG2_PRE_TX_EN	0x00000040 /* tx preable enable */
+#define MACCFG2_HUGE_FRAME	0x00000020 /* >= max frame len enable */
+#define MACCFG2_LEN_CHECK	0x00000010 /* MAC check frame's length Rx */
+#define MACCFG2_MAG_EN		0x00000008 /* magic packet enable */
+#define MACCFG2_PAD_CRC		0x00000004 /* pad and append CRC */
+#define MACCFG2_CRC_EN		0x00000002 /* MAC appends a CRC on all frames */
+#define MACCFG2_FULL_DUPLEX	0x00000001 /* Full deplex mode */
+
+struct fsl_enet_mac;
+
+void init_dtsec(struct fsl_enet_mac *mac, void *base, void *phyregs,
+		int max_rx_len);
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_fman.h b/arch/powerpc/include/asm/fsl_fman.h
index 6c01ffc41b..fddc0cc8cb 100644
--- a/arch/powerpc/include/asm/fsl_fman.h
+++ b/arch/powerpc/include/asm/fsl_fman.h
@@ -1,7 +1,7 @@
 /*
  * MPC85xx Internal Memory Map
  *
- * Copyright 2010 Freescale Semiconductor, Inc.
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -82,6 +82,189 @@ typedef struct fm_qmi {
 	u8	res[1024];
 } fm_qmi_t;
 
+struct fm_bmi_rx_port {
+	u32 fmbm_rcfg;	/* Rx configuration */
+	u32 fmbm_rst;	/* Rx status */
+	u32 fmbm_rda;	/* Rx DMA attributes */
+	u32 fmbm_rfp;	/* Rx FIFO parameters */
+	u32 fmbm_rfed;	/* Rx frame end data */
+	u32 fmbm_ricp;	/* Rx internal context parameters */
+	u32 fmbm_rim;	/* Rx internal margins */
+	u32 fmbm_rebm;	/* Rx external buffer margins */
+	u32 fmbm_rfne;	/* Rx frame next engine */
+	u32 fmbm_rfca;	/* Rx frame command attributes */
+	u32 fmbm_rfpne;	/* Rx frame parser next engine */
+	u32 fmbm_rpso;	/* Rx parse start offset */
+	u32 fmbm_rpp;	/* Rx policer profile */
+	u32 fmbm_rccb;	/* Rx coarse classification base */
+	u32 res1[0x2];
+	u32 fmbm_rprai[0x8];	/* Rx parse results array Initialization */
+	u32 fmbm_rfqid;		/* Rx frame queue ID */
+	u32 fmbm_refqid;	/* Rx error frame queue ID */
+	u32 fmbm_rfsdm;		/* Rx frame status discard mask */
+	u32 fmbm_rfsem;		/* Rx frame status error mask */
+	u32 fmbm_rfene;		/* Rx frame enqueue next engine */
+	u32 res2[0x23];
+	u32 fmbm_ebmpi[0x8];	/* buffer manager pool information */
+	u32 fmbm_acnt[0x8];	/* allocate counter */
+	u32 res3[0x8];
+	u32 fmbm_cgm[0x8];	/* congestion group map */
+	u32 fmbm_mpd;		/* BMan pool depletion */
+	u32 res4[0x1F];
+	u32 fmbm_rstc;		/* Rx statistics counters */
+	u32 fmbm_rfrc;		/* Rx frame counters */
+	u32 fmbm_rfbc;		/* Rx bad frames counter */
+	u32 fmbm_rlfc;		/* Rx large frames counter */
+	u32 fmbm_rffc;		/* Rx filter frames counter */
+	u32 fmbm_rfdc;		/* Rx frame discard counter */
+	u32 fmbm_rfldec;	/* Rx frames list DMA error counter */
+	u32 fmbm_rodc;		/* Rx out of buffers discard counter */
+	u32 fmbm_rbdc;		/* Rx buffers deallocate counter */
+	u32 res5[0x17];
+	u32 fmbm_rpc;		/* Rx performance counters */
+	u32 fmbm_rpcp;		/* Rx performance count parameters */
+	u32 fmbm_rccn;		/* Rx cycle counter */
+	u32 fmbm_rtuc;		/* Rx tasks utilization counter */
+	u32 fmbm_rrquc;		/* Rx receive queue utilization counter */
+	u32 fmbm_rduc;		/* Rx DMA utilization counter */
+	u32 fmbm_rfuc;		/* Rx FIFO utilization counter */
+	u32 fmbm_rpac;		/* Rx pause activation counter */
+	u32 res6[0x18];
+	u32 fmbm_rdbg;		/* Rx debug configuration */
+};
+
+/* FMBM_RCFG - Rx configuration */
+#define FMBM_RCFG_EN		0x80000000 /* port is enabled to receive data */
+#define FMBM_RCFG_FDOVR		0x02000000 /* frame discard override */
+#define FMBM_RCFG_IM		0x01000000 /* independent mode */
+
+/* FMBM_RST - Rx status */
+#define FMBM_RST_BSY		0x80000000 /* Rx port is busy */
+
+/* FMBM_RFCA - Rx frame command attributes */
+#define FMBM_RFCA_ORDER		0x80000000
+#define FMBM_RFCA_MR_MASK	0x003f0000
+#define FMBM_RFCA_MR(x)		((x << 16) & FMBM_RFCA_MR_MASK)
+
+/* FMBM_RSTC - Rx statistics */
+#define FMBM_RSTC_EN		0x80000000 /* statistics counters enable */
+
+struct fm_bmi_tx_port {
+	u32 fmbm_tcfg;	/* Tx configuration */
+	u32 fmbm_tst;	/* Tx status */
+	u32 fmbm_tda;	/* Tx DMA attributes */
+	u32 fmbm_tfp;	/* Tx FIFO parameters */
+	u32 fmbm_tfed;	/* Tx frame end data */
+	u32 fmbm_ticp;	/* Tx internal context parameters */
+	u32 fmbm_tfne;	/* Tx frame next engine */
+	u32 fmbm_tfca;	/* Tx frame command attributes */
+	u32 fmbm_tcfqid;/* Tx confirmation frame queue ID */
+	u32 fmbm_tfeqid;/* Tx error frame queue ID */
+	u32 fmbm_tfene;	/* Tx frame enqueue next engine */
+	u32 fmbm_trlmts;/* Tx rate limiter scale */
+	u32 fmbm_trlmt;	/* Tx rate limiter */
+	u32 res0[0x73];
+	u32 fmbm_tstc;	/* Tx statistics counters */
+	u32 fmbm_tfrc;	/* Tx frame counter */
+	u32 fmbm_tfdc;	/* Tx frames discard counter */
+	u32 fmbm_tfledc;/* Tx frame length error discard counter */
+	u32 fmbm_tfufdc;/* Tx frame unsupported format discard counter */
+	u32 fmbm_tbdc;	/* Tx buffers deallocate counter */
+	u32 res1[0x1a];
+	u32 fmbm_tpc;	/* Tx performance counters */
+	u32 fmbm_tpcp;	/* Tx performance count parameters */
+	u32 fmbm_tccn;	/* Tx cycle counter */
+	u32 fmbm_ttuc;	/* Tx tasks utilization counter */
+	u32 fmbm_ttcquc;/* Tx transmit confirm queue utilization counter */
+	u32 fmbm_tduc;	/* Tx DMA utilization counter */
+	u32 fmbm_tfuc;	/* Tx FIFO utilization counter */
+	u32 res2[0x19];
+	u32 fmbm_tdcfg;	/* Tx debug configuration */
+};
+
+/* FMBM_TCFG - Tx configuration */
+#define FMBM_TCFG_EN	0x80000000 /* port is enabled to transmit data */
+#define FMBM_TCFG_IM	0x01000000 /* independent mode enable */
+
+/* FMBM_TST - Tx status */
+#define FMBM_TST_BSY		0x80000000 /* Tx port is busy */
+
+/* FMBM_TFCA - Tx frame command attributes */
+#define FMBM_TFCA_ORDER		0x80000000
+#define FMBM_TFCA_MR_MASK	0x003f0000
+#define FMBM_TFCA_MR(x)		((x << 16) & FMBM_TFCA_MR_MASK)
+
+/* FMBM_TSTC - Tx statistics counters */
+#define FMBM_TSTC_EN		0x80000000
+
+/* FMBM_INIT - BMI initialization register */
+#define FMBM_INIT_START		0x80000000 /* init internal buffers */
+
+/* FMBM_CFG1 - BMI configuration 1 */
+#define FMBM_CFG1_FBPS_MASK	0x03ff0000 /* Free buffer pool size */
+#define FMBM_CFG1_FBPS_SHIFT	16
+#define FMBM_CFG1_FBPO_MASK	0x000003ff /* Free buffer pool offset */
+
+/* FMBM_IEVR - interrupt event */
+#define FMBM_IEVR_PEC		0x80000000 /* pipeline table ECC err detected */
+#define FMBM_IEVR_LEC		0x40000000 /* linked list RAM ECC error */
+#define FMBM_IEVR_SEC		0x20000000 /* statistics count RAM ECC error */
+#define FMBM_IEVR_CLEAR_ALL	(FMBM_IEVR_PEC | FMBM_IEVR_LEC | FMBM_IEVR_SEC)
+
+/* FMBM_IER - interrupt enable */
+#define FMBM_IER_PECE		0x80000000 /* PEC interrupt enable */
+#define FMBM_IER_LECE		0x40000000 /* LEC interrupt enable */
+#define FMBM_IER_SECE		0x20000000 /* SEC interrupt enable */
+
+#define FMBM_IER_DISABLE_ALL	0x00000000
+
+/* FMBM_PP - BMI Port Parameters */
+#define FMBM_PP_MXT_MASK	0x3f000000 /* Max # tasks */
+#define FMBM_PP_MXT(x)		(((x-1) << 24) & FMBM_PP_MXT_MASK)
+#define FMBM_PP_MXD_MASK	0x00000f00 /* Max DMA */
+#define FMBM_PP_MXD(x)		(((x-1) << 8) & FMBM_PP_MXD_MASK)
+
+/* FMBM_PFS - BMI Port FIFO Size */
+#define FMBM_PFS_IFSZ_MASK	0x000003ff /* Internal Fifo Size */
+#define FMBM_PFS_IFSZ(x)	(x & FMBM_PFS_IFSZ_MASK)
+
+/* FMQM_GC - global configuration */
+#define FMQM_GC_ENQ_EN		0x80000000 /* enqueue enable */
+#define FMQM_GC_DEQ_EN		0x40000000 /* dequeue enable */
+#define FMQM_GC_STEN		0x10000000 /* enable global stat counters */
+#define FMQM_GC_ENQ_THR_MASK	0x00003f00 /* max number of enqueue Tnum */
+#define FMQM_GC_ENQ(x)		((x << 8) &  FMQM_GC_ENQ_THR_MAS)
+#define FMQM_GC_DEQ_THR_MASK	0x0000003f /* max number of dequeue Tnum */
+#define FMQM_GC_DEQ(x)		(x & FMQM_GC_DEQ_THR_MASK)
+
+/* FMQM_EIE - error interrupt event register */
+#define FMQM_EIE_DEE		0x80000000 /* double-bit ECC error */
+#define FMQM_EIE_DFUPE		0x40000000 /* dequeue from unknown PortID */
+#define FMQM_EIE_CLEAR_ALL	(FMQM_EIE_DEE | FMQM_EIE_DFUPE)
+
+/* FMQM_EIEN - error interrupt enable register */
+#define FMQM_EIEN_DEEN		0x80000000 /* double-bit ECC error */
+#define FMQM_EIEN_DFUPEN	0x40000000 /* dequeue from unknown PortID */
+#define FMQM_EIEN_DISABLE_ALL	0x00000000
+
+/* FMQM_IE - interrupt event register */
+#define FMQM_IE_SEE		0x80000000 /* single-bit ECC error detected */
+#define FMQM_IE_CLEAR_ALL	FMQM_IE_SEE
+
+/* FMQM_IEN - interrupt enable register */
+#define FMQM_IEN_SEE		0x80000000 /* single-bit ECC err IRQ enable */
+#define FMQM_IEN_DISABLE_ALL	0x00000000
+
+/* NIA - next invoked action */
+#define NIA_ENG_RISC		0x00000000
+#define NIA_ENG_MASK		0x007c0000
+
+/* action code */
+#define NIA_RISC_AC_CC		0x00000006
+#define NIA_RISC_AC_IM_TX	0x00000008 /* independent mode Tx */
+#define NIA_RISC_AC_IM_RX	0x0000000a /* independent mode Rx */
+#define NIA_RISC_AC_HC		0x0000000c
+
 typedef struct fm_parser {
 	u8	res[1024];
 } fm_parser_t;
@@ -113,6 +296,27 @@ typedef struct fm_dma {
 	u32	res[0x3c8];
 } fm_dma_t;
 
+/* FMDMSR - Fman DMA status register */
+#define FMDMSR_CMDQNE		0x10000000 /* command queue not empty */
+#define FMDMSR_BER		0x08000000 /* bus err event occurred on bus */
+#define FMDMSR_RDB_ECC		0x04000000 /* read buffer ECC error */
+#define FMDMSR_WRB_SECC		0x02000000 /* write buf ECC err sys side */
+#define FMDMSR_WRB_FECC		0x01000000 /* write buf ECC err Fman side */
+#define FMDMSR_DPEXT_SECC	0x00800000 /* DP external ECC err sys side */
+#define FMDMSR_DPEXT_FECC	0x00400000 /* DP external ECC err Fman side */
+#define FMDMSR_DPDAT_SECC	0x00200000 /* DP data ECC err on sys side */
+#define FMDMSR_DPDAT_FECC	0x00100000 /* DP data ECC err on Fman side */
+#define FMDMSR_SPDAT_FECC	0x00080000 /* SP data ECC error Fman side */
+
+#define FMDMSR_CLEAR_ALL	(FMDMSR_BER | FMDMSR_RDB_ECC \
+				| FMDMSR_WRB_SECC | FMDMSR_WRB_FECC \
+				| FMDMSR_DPEXT_SECC | FMDMSR_DPEXT_FECC \
+				| FMDMSR_DPDAT_SECC | FMDMSR_DPDAT_FECC \
+				| FMDMSR_SPDAT_FECC)
+
+/* FMDMMR - FMan DMA mode register */
+#define FMDMMR_SBER		0x10000000 /* stop the DMA if a bus error */
+
 typedef struct fm_fpm {
 	u32	fpmtnc;		/* TNUM control */
 	u32	fpmprc;		/* Port_ID control */
@@ -141,7 +345,7 @@ typedef struct fm_fpm {
 	u32	fmcld;		/* classifier debug control */
 	u32	fmnpi;		/* normal pending interrupts */
 	u32	res5;
-	u32	fmnee;		/* event and enable */
+	u32	fmfpee;		/* event and enable */
 	u32	fpmcev[0x4];	/* CPU event 0-3 */
 	u32	res6[0x4];
 	u32	fmfp_ps[0x40];	/* port status */
@@ -150,9 +354,47 @@ typedef struct fm_fpm {
 	u32	res8[0xa0];
 } fm_fpm_t;
 
+/* FMFP_PRC - FPM Port_ID Control Register */
+#define FMFPPRC_PORTID_MASK	0x3f000000
+#define FMFPPRC_PORTID_SHIFT	24
+#define FMFPPRC_ORA_SHIFT	16
+#define FMFPPRC_RISC1		0x00000001
+#define FMFPPRC_RISC2		0x00000002
+#define FMFPPRC_RISC_ALL	(FMFPPRC_RISC1 | FMFPPRC_RSIC2)
+
+/* FPM Flush Control Register */
+#define FMFP_FLC_DISP_LIM_NONE	0x00000000 /* no dispatch limitation */
+
+/* FMFP_EE - FPM event and enable register */
+#define FMFPEE_DECC		0x80000000 /* double ECC err on FPM ram */
+#define FMFPEE_STL		0x40000000 /* stall of task ... */
+#define FMFPEE_SECC		0x20000000 /* single ECC error */
+#define FMFPEE_RFM		0x00010000 /* release FMan */
+#define FMFPEE_DECC_EN		0x00008000 /* double ECC interrupt enable */
+#define FMFPEE_STL_EN		0x00004000 /* stall of task interrupt enable */
+#define FMFPEE_SECC_EN		0x00002000 /* single ECC err interrupt enable */
+#define FMFPEE_EHM		0x00000008 /* external halt enable */
+#define FMFPEE_UEC		0x00000004 /* FMan is not halted */
+#define FMFPEE_CER		0x00000002 /* only errornous task stalled */
+#define FMFPEE_DER		0x00000001 /* DMA error is just reported */
+
+#define FMFPEE_CLEAR_EVENT	(FMFPEE_DECC | FMFPEE_STL | FMFPEE_SECC | \
+				 FMFPEE_EHM | FMFPEE_UEC | FMFPEE_CER | \
+				 FMFPEE_DER | FMFPEE_RFM)
+
+/* FMFP_RCR - FMan Rams Control and Event */
+#define FMFP_RCR_MDEC		0x00008000 /* double ECC error in muram */
+#define FMFP_RCR_IDEC		0x00004000 /* double ECC error in iram */
+
 typedef struct fm_imem {
-	u8	res[4*1024];
+	u32	iadd;		/* instruction address register */
+	u32	idata;		/* instruction data register */
+	u32	itcfg;		/* timing config register */
+	u32	iready;		/* ready register */
+	u8	res[0xff0];
 } fm_imem_t;
+#define IRAM_IADD_AIE		0x80000000 /* address auto increase enable */
+#define IRAM_READY		0x80000000 /* ready to use */
 
 typedef struct fm_soft_parser {
 	u8	res[4*1024];
@@ -200,10 +442,11 @@ typedef struct ccsr_fman {
 	struct {
 		fm_dtsec_t	fm_dtesc;
 		fm_mdio_t	fm_mdio;
-	} mac[4];
-	u8			res3[32*1024];
-	fm_10gec_t		fm_10gec;
-	fm_10gec_mdio_t		fm_10gec_mdio;
+	} mac_1g[8];		/* support up to 8 1g controllers */
+	struct {
+		fm_10gec_t		fm_10gec;
+		fm_10gec_mdio_t		fm_10gec_mdio;
+	} mac_10g[1];
 	u8			res4[48*1024];
 	fm_1588_t		fm_1588;
 	u8			res5[4*1024];
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
index d4d9809055..7d95eb4416 100644
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -69,6 +69,7 @@
  */
 /* Enable ECC Encoder */
 #define CSOR_NAND_ECC_ENC_EN		0x80000000
+#define CSOR_NAND_ECC_MODE_MASK		0x30000000
 /* 4 bit correction per 520 Byte sector */
 #define CSOR_NAND_ECC_MODE_4		0x00000000
 /* 8 bit correction per 528 Byte sector */
@@ -857,10 +858,7 @@ struct fsl_ifc_nand {
 	u32 res19[0x10];
 	u32 nand_fsr;
 	u32 res20;
-	u32 nand_eccstat0;
-	u32 nand_eccstat1;
-	u32 nand_eccstat2;
-	u32 nand_eccstat3;
+	u32 nand_eccstat[4];
 	u32 res21[0x20];
 	u32 nanndcr;
 	u32 res22[0x2];
@@ -953,5 +951,10 @@ struct fsl_ifc {
 	struct fsl_ifc_gpcm ifc_gpcm;
 };
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
+#undef CSPR_MSEL_NOR
+#define CSPR_MSEL_NOR	CSPR_MSEL_GPCM
+#endif
+
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_PPC_FSL_IFC_H */
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index 801571f9eb..9ad104eb8a 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -147,9 +147,18 @@ extern void fdt_fixup_liodn(void *blob);
 		offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
 		CONFIG_SYS_FSL_SEC_OFFSET, 0)
 
+#define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \
+	SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \
+	liodnA, \
+	offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg1) + \
+	CONFIG_SYS_FSL_RAID_ENGINE_OFFSET, \
+	offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \
+	CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
+
 extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
+extern struct liodn_id_table raide_liodn_tbl[];
 extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[];
-extern int liodn_tbl_sz, sec_liodn_tbl_sz;
+extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz;
 extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz;
 
 #endif
diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h
index e1c1212c38..8c3ea0bac4 100644
--- a/arch/powerpc/include/asm/fsl_portals.h
+++ b/arch/powerpc/include/asm/fsl_portals.h
@@ -35,6 +35,9 @@ enum fsl_dpaa_dev {
 #ifdef CONFIG_SYS_DPAA_PME
 	FSL_HW_PORTAL_PME,
 #endif
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+	FSL_HW_PORTAL_RAID_ENGINE,
+#endif
 };
 
 struct qportal_info {
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
new file mode 100644
index 0000000000..d1c1967d1d
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSL_SECURE_BOOT_H
+#define __FSL_SECURE_BOOT_H
+
+/* Starting TLB number for the TLB entried for 3.5 G space created by ISBC */
+#if defined(CONFIG_FSL_CORENET)
+#define CONFIG_SYS_ISBC_START_TLB		3
+#else
+#define CONFIG_SYS_ISBC_START_TLB		0
+#endif
+
+/* Number fo TLB's created by ISBC */
+#define CONFIG_SYS_ISBC_NUM_TLBS		5
+
+#if defined(CONFIG_FSL_CORENET)
+#define CONFIG_SYS_PBI_FLASH_BASE		0xc0000000
+#else
+#define CONFIG_SYS_PBI_FLASH_BASE		0xce000000
+#endif
+#define CONFIG_SYS_PBI_FLASH_WINDOW		0xcff80000
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_tgec.h b/arch/powerpc/include/asm/fsl_tgec.h
new file mode 100644
index 0000000000..8de37c9e52
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_tgec.h
@@ -0,0 +1,215 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *	Dave Liu <daveliu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __TGEC_H__
+#define __TGEC_H__
+
+#include <phy.h>
+
+struct tgec {
+	/* 10GEC general control and status registers */
+	u32	tgec_id;	/* Controller ID register */
+	u32	res0;
+	u32	command_config;	/* Control and configuration register */
+	u32	mac_addr_0;	/* Lower 32 bits of 48-bit MAC address */
+	u32	mac_addr_1;	/* Upper 16 bits of 48-bit MAC address */
+	u32	maxfrm;		/* Maximum frame length register */
+	u32	pause_quant;	/* Pause quanta register */
+	u32	res1[4];
+	u32	hashtable_ctrl;	/* Hash table control register */
+	u32	res2[4];
+	u32	status;		/* MAC status register */
+	u32	tx_ipg_length;	/* Transmitter inter-packet-gap register */
+	u32	mac_addr_2;	/* Lower 32 bits of the 2nd 48-bit MAC addr */
+	u32	mac_addr_3;	/* Upper 16 bits of the 2nd 48-bit MAC addr */
+	u32	res3[4];
+	u32	imask;		/* Interrupt mask register */
+	u32	ievent;		/* Interrupt event register */
+	u32	res4[6];
+	/* 10GEC statistics counter registers */
+	u32	tx_frame_u;	/* Tx frame counter upper */
+	u32	tx_frame_l;	/* Tx frame counter lower */
+	u32	rx_frame_u;	/* Rx frame counter upper */
+	u32	rx_frame_l;	/* Rx frame counter lower */
+	u32	rx_frame_crc_err_u; /* Rx frame check sequence error upper */
+	u32	rx_frame_crc_err_l; /* Rx frame check sequence error lower */
+	u32	rx_align_err_u;	/* Rx alignment error upper */
+	u32	rx_align_err_l;	/* Rx alignment error lower */
+	u32	tx_pause_frame_u; /* Tx valid pause frame upper */
+	u32	tx_pause_frame_l; /* Tx valid pause frame lower */
+	u32	rx_pause_frame_u; /* Rx valid pause frame upper */
+	u32	rx_pause_frame_l; /* Rx valid pause frame upper */
+	u32	rx_long_err_u;	/* Rx too long frame error upper */
+	u32	rx_long_err_l;	/* Rx too long frame error lower */
+	u32	rx_frame_err_u;	/* Rx frame length error upper */
+	u32	rx_frame_err_l;	/* Rx frame length error lower */
+	u32	tx_vlan_u;	/* Tx VLAN frame upper */
+	u32	tx_vlan_l;	/* Tx VLAN frame lower */
+	u32	rx_vlan_u;	/* Rx VLAN frame upper */
+	u32	rx_vlan_l;	/* Rx VLAN frame lower */
+	u32	tx_oct_u;	/* Tx octets upper */
+	u32	tx_oct_l;	/* Tx octets lower */
+	u32	rx_oct_u;	/* Rx octets upper */
+	u32	rx_oct_l;	/* Rx octets lower */
+	u32	rx_uni_u;	/* Rx unicast frame upper */
+	u32	rx_uni_l;	/* Rx unicast frame lower */
+	u32	rx_multi_u;	/* Rx multicast frame upper */
+	u32	rx_multi_l;	/* Rx multicast frame lower */
+	u32	rx_brd_u;	/* Rx broadcast frame upper */
+	u32	rx_brd_l;	/* Rx broadcast frame lower */
+	u32	tx_frame_err_u;	/* Tx frame error upper */
+	u32	tx_frame_err_l;	/* Tx frame error lower */
+	u32	tx_uni_u;	/* Tx unicast frame upper */
+	u32	tx_uni_l;	/* Tx unicast frame lower */
+	u32	tx_multi_u;	/* Tx multicast frame upper */
+	u32	tx_multi_l;	/* Tx multicast frame lower */
+	u32	tx_brd_u;	/* Tx broadcast frame upper */
+	u32	tx_brd_l;	/* Tx broadcast frame lower */
+	u32	rx_drop_u;	/* Rx dropped packets upper */
+	u32	rx_drop_l;	/* Rx dropped packets lower */
+	u32	rx_eoct_u;	/* Rx ethernet octets upper */
+	u32	rx_eoct_l;	/* Rx ethernet octets lower */
+	u32	rx_pkt_u;	/* Rx packets upper */
+	u32	rx_pkt_l;	/* Rx packets lower */
+	u32	tx_undsz_u;	/* Undersized packet upper */
+	u32	tx_undsz_l;	/* Undersized packet lower */
+	u32	rx_64_u;	/* Rx 64 oct packet upper */
+	u32	rx_64_l;	/* Rx 64 oct packet lower */
+	u32	rx_127_u;	/* Rx 65 to 127 oct packet upper */
+	u32	rx_127_l;	/* Rx 65 to 127 oct packet lower */
+	u32	rx_255_u;	/* Rx 128 to 255 oct packet upper */
+	u32	rx_255_l;	/* Rx 128 to 255 oct packet lower */
+	u32	rx_511_u;	/* Rx 256 to 511 oct packet upper */
+	u32	rx_511_l;	/* Rx 256 to 511 oct packet lower */
+	u32	rx_1023_u;	/* Rx 512 to 1023 oct packet upper */
+	u32	rx_1023_l;	/* Rx 512 to 1023 oct packet lower */
+	u32	rx_1518_u;	/* Rx 1024 to 1518 oct packet upper */
+	u32	rx_1518_l;	/* Rx 1024 to 1518 oct packet lower */
+	u32	rx_1519_u;	/* Rx 1519 to max oct packet upper */
+	u32	rx_1519_l;	/* Rx 1519 to max oct packet lower */
+	u32	tx_oversz_u;	/* oversized packet upper */
+	u32	tx_oversz_l;	/* oversized packet lower */
+	u32	tx_jabber_u;	/* Jabber packet upper */
+	u32	tx_jabber_l;	/* Jabber packet lower */
+	u32	tx_frag_u;	/* Fragment packet upper */
+	u32	tx_frag_l;	/* Fragment packet lower */
+	u32	rx_err_u;	/* Rx frame error upper */
+	u32	rx_err_l;	/* Rx frame error lower */
+	u32	res5[0x39a];
+};
+
+/* EC10G_ID - 10-gigabit ethernet MAC controller ID */
+#define EC10G_ID_VER_MASK	0x0000ff00
+#define EC10G_ID_VER_SHIFT	8
+#define EC10G_ID_REV_MASK	0x000000ff
+
+/* COMMAND_CONFIG - command and configuration register */
+#define TGEC_CMD_CFG_EN_TIMESTAMP	0x00100000 /* enable IEEE1588 */
+#define TGEC_CMD_CFG_TX_ADDR_INS_SEL	0x00080000 /* Tx mac addr w/ second */
+#define TGEC_CMD_CFG_NO_LEN_CHK		0x00020000 /* payload len chk disable */
+#define TGEC_CMD_CFG_SEND_IDLE		0x00010000 /* send XGMII idle seqs */
+#define TGEC_CMD_CFG_RX_ER_DISC		0x00004000 /* Rx err frm discard enb */
+#define TGEC_CMD_CFG_CMD_FRM_EN		0x00002000 /* CMD frame RX enable */
+#define TGEC_CMD_CFG_STAT_CLR		0x00001000 /* clear stats */
+#define TGEC_CMD_CFG_TX_ADDR_INS	0x00000200 /* overwrite src MAC addr */
+#define TGEC_CMD_CFG_PAUSE_IGNORE	0x00000100 /* ignore pause frames */
+#define TGEC_CMD_CFG_PAUSE_FWD		0x00000080 /* fwd pause frames */
+#define TGEC_CMD_CFG_CRC_FWD		0x00000040 /* fwd Rx CRC frames */
+#define TGEC_CMD_CFG_PAD_EN		0x00000020 /* MAC remove Rx padding */
+#define TGEC_CMD_CFG_PROM_EN		0x00000010 /* promiscuous mode enable */
+#define TGEC_CMD_CFG_WAN_MODE		0x00000008 /* WAN mode enable */
+#define TGEC_CMD_CFG_RX_EN		0x00000002 /* MAC Rx path enable */
+#define TGEC_CMD_CFG_TX_EN		0x00000001 /* MAC Tx path enable */
+#define TGEC_CMD_CFG_RXTX_EN	(TGEC_CMD_CFG_RX_EN | TGEC_CMD_CFG_TX_EN)
+
+/* HASHTABLE_CTRL - Hashtable control register */
+#define HASHTABLE_CTRL_MCAST_EN	0x00000200 /* enable mulitcast Rx hash */
+#define HASHTABLE_CTRL_ADDR_MASK	0x000001ff
+
+/* TX_IPG_LENGTH - Transmit inter-packet gap length register */
+#define TX_IPG_LENGTH_IPG_LEN_MASK	0x000003ff
+
+/* IMASK - interrupt mask register */
+#define IMASK_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event mask */
+#define IMASK_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion mask */
+#define IMASK_REM_FAULT		0x00004000 /* remote fault mask */
+#define IMASK_LOC_FAULT		0x00002000 /* local fault mask */
+#define IMASK_TX_ECC_ER		0x00001000 /* Tx frame ECC error mask */
+#define IMASK_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow mask */
+#define IMASK_TX_ER		0x00000200 /* Tx frame error mask */
+#define IMASK_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow mask */
+#define IMASK_RX_ECC_ER		0x00000080 /* Rx frame ECC error mask */
+#define IMASK_RX_JAB_FRM	0x00000040 /* Rx jabber frame mask */
+#define IMASK_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame mask */
+#define IMASK_RX_RUNT_FRM	0x00000010 /* Rx runt frame mask */
+#define IMASK_RX_FRAG_FRM	0x00000008 /* Rx fragment frame mask */
+#define IMASK_RX_LEN_ER		0x00000004 /* Rx payload length error mask */
+#define IMASK_RX_CRC_ER		0x00000002 /* Rx CRC error mask */
+#define IMASK_RX_ALIGN_ER	0x00000001 /* Rx alignment error mask */
+
+#define IMASK_MASK_ALL		0x00000000
+
+/* IEVENT - interrupt event register */
+#define IEVENT_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event */
+#define IEVENT_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion */
+#define IEVENT_REM_FAULT	0x00004000 /* remote fault */
+#define IEVENT_LOC_FAULT	0x00002000 /* local fault */
+#define IEVENT_TX_ECC_ER	0x00001000 /* Tx frame ECC error */
+#define IEVENT_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow */
+#define IEVENT_TX_ER		0x00000200 /* Tx frame error */
+#define IEVENT_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow */
+#define IEVENT_RX_ECC_ER	0x00000080 /* Rx frame ECC error */
+#define IEVENT_RX_JAB_FRM	0x00000040 /* Rx jabber frame */
+#define IEVENT_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame */
+#define IEVENT_RX_RUNT_FRM	0x00000010 /* Rx runt frame */
+#define IEVENT_RX_FRAG_FRM	0x00000008 /* Rx fragment frame */
+#define IEVENT_RX_LEN_ER	0x00000004 /* Rx payload length error */
+#define IEVENT_RX_CRC_ER	0x00000002 /* Rx CRC error */
+#define IEVENT_RX_ALIGN_ER	0x00000001 /* Rx alignment error */
+
+#define IEVENT_CLEAR_ALL	0xffffffff
+
+struct tgec_mdio_controller {
+	u32	res0[0xc];
+	u32	mdio_stat;	/* MDIO configuration and status */
+	u32	mdio_ctl;	/* MDIO control */
+	u32	mdio_data;	/* MDIO data */
+	u32	mdio_addr;	/* MDIO address */
+};
+
+#define MDIO_STAT_CLKDIV(x)	(((x>>1) & 0xff) << 8)
+#define MDIO_STAT_BSY		(1 << 0)
+#define MDIO_STAT_RD_ER		(1 << 1)
+#define MDIO_CTL_DEV_ADDR(x)	(x & 0x1f)
+#define MDIO_CTL_PORT_ADDR(x)	((x & 0x1f) << 5)
+#define MDIO_CTL_PRE_DIS	(1 << 10)
+#define MDIO_CTL_SCAN_EN	(1 << 11)
+#define MDIO_CTL_POST_INC	(1 << 14)
+#define MDIO_CTL_READ		(1 << 15)
+
+#define MDIO_DATA(x)		(x & 0xffff)
+#define MDIO_DATA_BSY		(1 << 31)
+
+struct fsl_enet_mac;
+
+void init_tgec(struct fsl_enet_mac *mac, void *base, void *phyregs,
+		int max_rx_len);
+
+#endif
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index cc0293acd4..8d4c9cb4f7 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004-2011 Freescale Semiconductor, Inc.
  *
  * MPC83xx Internal Memory Map
  *
@@ -285,6 +285,105 @@ typedef struct qesba83xx {
 /*
  * DDR Memory Controller Memory Map
  */
+#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
+typedef struct ccsr_ddr {
+	u32	cs0_bnds;		/* Chip Select 0 Memory Bounds */
+	u8	res1[4];
+	u32	cs1_bnds;		/* Chip Select 1 Memory Bounds */
+	u8	res2[4];
+	u32	cs2_bnds;		/* Chip Select 2 Memory Bounds */
+	u8	res3[4];
+	u32	cs3_bnds;		/* Chip Select 3 Memory Bounds */
+	u8	res4[100];
+	u32	cs0_config;		/* Chip Select Configuration */
+	u32	cs1_config;		/* Chip Select Configuration */
+	u32	cs2_config;		/* Chip Select Configuration */
+	u32	cs3_config;		/* Chip Select Configuration */
+	u8	res4a[48];
+	u32	cs0_config_2;		/* Chip Select Configuration 2 */
+	u32	cs1_config_2;		/* Chip Select Configuration 2 */
+	u32	cs2_config_2;		/* Chip Select Configuration 2 */
+	u32	cs3_config_2;		/* Chip Select Configuration 2 */
+	u8	res5[48];
+	u32	timing_cfg_3;		/* SDRAM Timing Configuration 3 */
+	u32	timing_cfg_0;		/* SDRAM Timing Configuration 0 */
+	u32	timing_cfg_1;		/* SDRAM Timing Configuration 1 */
+	u32	timing_cfg_2;		/* SDRAM Timing Configuration 2 */
+	u32	sdram_cfg;		/* SDRAM Control Configuration */
+	u32	sdram_cfg_2;		/* SDRAM Control Configuration 2 */
+	u32	sdram_mode;		/* SDRAM Mode Configuration */
+	u32	sdram_mode_2;		/* SDRAM Mode Configuration 2 */
+	u32	sdram_md_cntl;		/* SDRAM Mode Control */
+	u32	sdram_interval;		/* SDRAM Interval Configuration */
+	u32	sdram_data_init;	/* SDRAM Data initialization */
+	u8	res6[4];
+	u32	sdram_clk_cntl;		/* SDRAM Clock Control */
+	u8	res7[20];
+	u32	init_addr;		/* training init addr */
+	u32	init_ext_addr;		/* training init extended addr */
+	u8	res8_1[16];
+	u32	timing_cfg_4;		/* SDRAM Timing Configuration 4 */
+	u32	timing_cfg_5;		/* SDRAM Timing Configuration 5 */
+	u8	reg8_1a[8];
+	u32	ddr_zq_cntl;		/* ZQ calibration control*/
+	u32	ddr_wrlvl_cntl;		/* write leveling control*/
+	u8	reg8_1aa[4];
+	u32	ddr_sr_cntr;		/* self refresh counter */
+	u32	ddr_sdram_rcw_1;	/* Control Words 1 */
+	u32	ddr_sdram_rcw_2;	/* Control Words 2 */
+	u8	reg_1ab[8];
+	u32	ddr_wrlvl_cntl_2;	/* write leveling control 2 */
+	u32	ddr_wrlvl_cntl_3;	/* write leveling control 3 */
+	u8	res8_1b[104];
+	u32	sdram_mode_3;		/* SDRAM Mode Configuration 3 */
+	u32	sdram_mode_4;		/* SDRAM Mode Configuration 4 */
+	u32	sdram_mode_5;		/* SDRAM Mode Configuration 5 */
+	u32	sdram_mode_6;		/* SDRAM Mode Configuration 6 */
+	u32	sdram_mode_7;		/* SDRAM Mode Configuration 7 */
+	u32	sdram_mode_8;		/* SDRAM Mode Configuration 8 */
+	u8	res8_1ba[0x908];
+	u32	ddr_dsr1;		/* Debug Status 1 */
+	u32	ddr_dsr2;		/* Debug Status 2 */
+	u32	ddr_cdr1;		/* Control Driver 1 */
+	u32	ddr_cdr2;		/* Control Driver 2 */
+	u8	res8_1c[200];
+	u32	ip_rev1;		/* IP Block Revision 1 */
+	u32	ip_rev2;		/* IP Block Revision 2 */
+	u32	eor;			/* Enhanced Optimization Register */
+	u8	res8_2[252];
+	u32	mtcr;			/* Memory Test Control Register */
+	u8	res8_3[28];
+	u32	mtp1;			/* Memory Test Pattern 1 */
+	u32	mtp2;			/* Memory Test Pattern 2 */
+	u32	mtp3;			/* Memory Test Pattern 3 */
+	u32	mtp4;			/* Memory Test Pattern 4 */
+	u32	mtp5;			/* Memory Test Pattern 5 */
+	u32	mtp6;			/* Memory Test Pattern 6 */
+	u32	mtp7;			/* Memory Test Pattern 7 */
+	u32	mtp8;			/* Memory Test Pattern 8 */
+	u32	mtp9;			/* Memory Test Pattern 9 */
+	u32	mtp10;			/* Memory Test Pattern 10 */
+	u8	res8_4[184];
+	u32	data_err_inject_hi;	/* Data Path Err Injection Mask High */
+	u32	data_err_inject_lo;	/* Data Path Err Injection Mask Low */
+	u32	ecc_err_inject;		/* Data Path Err Injection Mask ECC */
+	u8	res9[20];
+	u32	capture_data_hi;	/* Data Path Read Capture High */
+	u32	capture_data_lo;	/* Data Path Read Capture Low */
+	u32	capture_ecc;		/* Data Path Read Capture ECC */
+	u8	res10[20];
+	u32	err_detect;		/* Error Detect */
+	u32	err_disable;		/* Error Disable */
+	u32	err_int_en;
+	u32	capture_attributes;	/* Error Attrs Capture */
+	u32	capture_address;	/* Error Addr Capture */
+	u32	capture_ext_address;	/* Error Extended Addr Capture */
+	u32	err_sbe;		/* Single-Bit ECC Error Management */
+	u8	res11[164];
+	u32	debug[32];		/* debug_1 to debug_32 */
+	u8	res12[128];
+} ccsr_ddr_t;
+#else
 typedef struct ddr_cs_bnds {
 	u32 csbnds;
 	u8 res0[4];
@@ -334,6 +433,7 @@ typedef struct ddr83xx {
 	u32 debug_reg;
 	u8 res9[0xFC];
 } ddr83xx_t;
+#endif
 
 /*
  * DUART
@@ -641,7 +741,11 @@ typedef struct immap {
 	u8			dll_ddr[0x100];
 	u8			dll_lbc[0x100];
 	u8			res1[0xE00];
-	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
+	ccsr_ddr_t		ddr;	/* DDR Memory Controller Memory */
+#else
+	ddr83xx_t		ddr;	/* DDR Memory Controller Memory */
+#endif
 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
 	u8			res2[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
@@ -869,10 +973,15 @@ typedef struct immap {
 } immap_t;
 #endif
 
+#define CONFIG_SYS_MPC83xx_DDR_OFFSET	(0x2000)
+#define CONFIG_SYS_MPC83xx_DDR_ADDR \
+			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DDR_OFFSET)
 #define CONFIG_SYS_MPC83xx_DMA_OFFSET	(0x8000)
-#define CONFIG_SYS_MPC83xx_DMA_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
+#define CONFIG_SYS_MPC83xx_DMA_ADDR \
+			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
 #define CONFIG_SYS_MPC83xx_ESDHC_OFFSET	(0x2e000)
-#define CONFIG_SYS_MPC83xx_ESDHC_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
+#define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
+			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
 
 #ifndef CONFIG_SYS_MPC83xx_USB_OFFSET
 #define CONFIG_SYS_MPC83xx_USB_OFFSET  0x23000
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 6aaade076e..fb5ef916cc 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1700,12 +1700,34 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR8_HOST_AGT_B1		0x00e00000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B2		0x00100000
 #define FSL_CORENET_RCWSR11_EC1			0x00c00000 /* bits 360..361 */
-#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1	0x00000000
-#define FSL_CORENET_RCWSR11_EC1_FM1_USB1	0x00800000
+#if defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P3060)
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1		0x00000000
+#define FSL_CORENET_RCWSR11_EC1_FM1_USB1		0x00800000
 #define FSL_CORENET_RCWSR11_EC2			0x001c0000 /* bits 363..365 */
-#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1	0x00000000
-#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2	0x00080000
-#define FSL_CORENET_RCWSR11_EC2_USB2		0x00100000
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1		0x00000000
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2		0x00080000
+#define FSL_CORENET_RCWSR11_EC2_USB2			0x00100000
+#endif
+#if defined(CONFIG_PPC_P3060)
+#define FSL_CORENET_RCWSR13_EC1_EXT			0x1c000000
+#define FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII	0x04000000
+#define FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII	0x08000000
+#define FSL_CORENET_RCWSR13_EC2_EXT			0x01c00000
+#define FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII	0x00400000
+#define FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII	0x00800000
+#define FSL_CORENET_RCWSR13_EC3				0x00380000
+#define FSL_CORENET_RCWSR13_EC3_FM2_DTSEC4_MII		0x00100000
+#endif
+#if defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P2041) \
+	|| defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII	0x00000000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII		0x00800000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE		0x00c00000
+#define FSL_CORENET_RCWSR11_EC2			0x00180000 /* bits 363..364 */
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII	0x00000000
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII		0x00100000
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE		0x00180000
+#endif
 	u8	res18[192];
 	u32	scratchrw[4];	/* Scratch Read/Write */
 	u8	res19[240];
@@ -1873,6 +1895,7 @@ typedef struct ccsr_gur {
 #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
 #define MPC85xx_PORDEVSR_SGMII1_DIS	0x10000000
 #define MPC85xx_PORDEVSR_SGMII2_DIS	0x08000000
+#define MPC85xx_PORDEVSR_TSEC1_PRTC	0x02000000
 #else
 #define MPC85xx_PORDEVSR_SGMII1_DIS	0x20000000
 #define MPC85xx_PORDEVSR_SGMII2_DIS	0x10000000
@@ -1971,6 +1994,9 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_CAN2_TDM			0x00000002
 #define MPC85xx_PMUXCR_CAN2_RES			0x00000003
 #endif
+#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#define MPC85xx_PMUXCR_TSEC1_1		0x10000000
+#else
 #define MPC85xx_PMUXCR_SD_DATA		0x80000000
 #define MPC85xx_PMUXCR_SDHC_CD		0x40000000
 #define MPC85xx_PMUXCR_SDHC_WP		0x20000000
@@ -1989,6 +2015,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_QE10		0x00000020
 #define MPC85xx_PMUXCR_QE11		0x00000010
 #define MPC85xx_PMUXCR_QE12		0x00000008
+#endif
 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
 #define MPC85xx_PMUXCR_TDM_MASK		0x0001cc00
 #define MPC85xx_PMUXCR_TDM		0x00014800
@@ -2301,6 +2328,22 @@ typedef struct ccsr_usb_phy {
 } ccsr_usb_phy_t;
 #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
 
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+struct ccsr_raide {
+	u8	res0[0x543];
+	u32	liodnbr;			/* LIODN Base Register */
+	u8	res1[0xab8];
+	struct {
+		struct {
+			u32	cfg0;		/* cfg register 0 */
+			u32	cfg1;		/* cfg register 1 */
+			u8	res1[0x3f8];
+		} ring[2];
+		u8	res[0x800];
+	} jq[2];
+};
+#endif
+
 #ifdef CONFIG_FSL_CORENET
 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET	0x0000
 #define CONFIG_SYS_MPC85xx_DDR_OFFSET		0x8000
@@ -2331,6 +2374,7 @@ typedef struct ccsr_usb_phy {
 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET	0x316000
 #define CONFIG_SYS_FSL_QMAN_OFFSET		0x318000
 #define CONFIG_SYS_FSL_BMAN_OFFSET		0x31a000
+#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET	0x320000
 #define CONFIG_SYS_FSL_FM1_OFFSET		0x400000
 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0x488000
 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0x489000
@@ -2379,6 +2423,8 @@ typedef struct ccsr_usb_phy {
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
+#define CONFIG_SYS_SNVS_OFFSET			0xE6000
+#define CONFIG_SYS_SFP_OFFSET			0xE7000
 #define CONFIG_SYS_MPC85xx_CPM_OFFSET		0x80000
 #define CONFIG_SYS_FSL_QMAN_OFFSET		0x88000
 #define CONFIG_SYS_FSL_BMAN_OFFSET		0x8a000
@@ -2399,6 +2445,8 @@ typedef struct ccsr_usb_phy {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
+#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 0c4cc2554b..1b96b84dcb 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1022,7 +1022,11 @@
 #define SVR_FAM(svr)	(((svr) >> 20) & 0xFFF)	/* Family field */
 #define SVR_MEM(svr)	(((svr) >> 16) & 0xF)	/* Member field */
 
+#ifdef CONFIG_MPC8536
+#define SVR_MAJ(svr)	(((svr) >>  4) & 0x7)	/* Major revision field*/
+#else
 #define SVR_MAJ(svr)	(((svr) >>  4) & 0xF)	/* Major revision field*/
+#endif
 #define SVR_MIN(svr)	(((svr) >>  0) & 0xF)	/* Minor revision field*/
 
 /* Some parts define SVR[0:23] as the SOC version */
@@ -1111,6 +1115,8 @@
 #define SVR_P2041_E	0x821801
 #define SVR_P3041	0x821103
 #define SVR_P3041_E	0x821903
+#define SVR_P3060	0x820002
+#define SVR_P3060_E	0x820802
 #define SVR_P4040	0x820100
 #define SVR_P4040_E	0x820900
 #define SVR_P4080	0x820000
@@ -1176,13 +1182,17 @@ struct cpu_type {
 	char name[15];
 	u32 soc_ver;
 	u32 num_cores;
+	u32 mask;	/* which cpu(s) actually exist */
 };
 
 struct cpu_type *identify_cpu(u32 ver);
 
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
 #define CPU_TYPE_ENTRY(n, v, nc) \
-	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), }
+	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), \
+	  .mask = (1 << (nc)) - 1 }
+#define CPU_TYPE_ENTRY_MASK(n, v, nc, m) \
+	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), .mask = (m) }
 #else
 #if defined(CONFIG_MPC83xx)
 #define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
author	Wolfgang Denk <wd@denx.de>	2011-10-04 22:08:13 +0200
committer	Wolfgang Denk <wd@denx.de>	2011-10-04 22:08:13 +0200
commit	1fed668b3fb9c35932f58af00ff5539239fa4e1d (patch)
tree	eaaaead8ca19924af1823caae040f504be9b6d98 /arch
parent	c52575350fd6e794717f6bee4f81dbb8038fe22e (diff)
parent	6d7b061af153bc5beb633c3bd15348284716a067 (diff)