diff options
| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2019-11-27 15:55:21 +0800 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2020-01-07 14:38:33 +0100 |
| commit | 20322cea64e471c777627622e9ccb1096b5db167 (patch) | |
| tree | f36ad30afa9a90b995ab15b45186808e9863ddab /arch | |
| parent | 38229994affe422ef202c574759a08a97e44317c (diff) | |
arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz
CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz.
Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h index 3b4bb62ca5..71fbaa7667 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h @@ -13,9 +13,7 @@ const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); const unsigned int cm_get_intosc_clk_hz(void); const unsigned int cm_get_fpga_clk_hz(void); -#define CLKMGR_EOSC1_HZ 25000000 -#define CLKMGR_INTOSC_HZ 460000000 -#define CLKMGR_FPGA_CLK_HZ 50000000 +#define CLKMGR_INTOSC_HZ 400000000 /* Clock configuration accessors */ const struct cm_config * const cm_get_default_config(void); |