summaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
authorSekhar Nori <nsekhar@ti.com>2017-06-02 18:07:12 +0530
committerTom Rini <trini@konsulko.com>2017-06-09 11:24:01 -0400
commit264e420f365cd673a0076adfcb975ead7139aedc (patch)
tree1d8b00fb66eb811ec767484f7e11ee7bb242b6f8 /arch
parent314f6362c47c8e43b1fd216fcf1dbed355608b05 (diff)
davinci: omapl138_lcdk: fix tXSNR DDR2 timing value
As per the datasheet[1] available for DDR2 part on board the OMAP-L138 LCDK, the tXSNR (exit self refresh to a non-read command) is 137.5 ns. This corresponds to a value of 20 to be written to T_XSNR register field of OMAP-L138's DDR configuration. The DDR2 is at 150 MHz. Fix this. The correct value also appears on the initialization scripts (called CCS GEL files) available on TI's wiki pages[2] [1] http://www.samsung.com/global/business/semiconductor/file/product/ds_k4t1gxx4qf_rev12-0.pdf [2] http://processors.wiki.ti.com/index.php/L138/C6748_Development_Kit_(LCDK)#CCS_XML_.26_GEL_Files Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch')
0 files changed, 0 insertions, 0 deletions