diff options
| author | Simon Glass <sjg@chromium.org> | 2019-12-06 21:42:30 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2019-12-15 11:44:19 +0800 |
| commit | 28d7d76a86a4e73db27b521d034fb6170df95672 (patch) | |
| tree | 29d92af5fbea9ec478d3ec4786d90ba9c1ac2cf0 /arch | |
| parent | b31129528e7dbbfb67a93116b40fbb1b1d4d724b (diff) | |
x86: Add an option to control the position of SPL
For Apollo Lake SPL is run from CAR (cache-as-RAM) which is in a different
location from where SPL must be placed in ROM. In other words, although
SPL runs before SDRAM is set up, it is not execute-in-place (XIP).
Add a Kconfig option for the ROM position.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/Kconfig | 5 | ||||
| -rw-r--r-- | arch/x86/dts/u-boot.dtsi | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 9d7ff3c07a..1d08cb24fb 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -904,4 +904,9 @@ config X86_OFFSET_U_BOOT depends on HAVE_SYS_TEXT_BASE default SYS_TEXT_BASE +config X86_OFFSET_SPL + hex "Offset of SPL in ROM image" + depends on SPL && X86 + default SPL_TEXT_BASE + endmenu diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index d84c64880a..fad3e7c951 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -45,7 +45,7 @@ }; #endif u-boot-spl { - offset = <CONFIG_SPL_TEXT_BASE>; + offset = <CONFIG_X86_OFFSET_SPL>; }; u-boot-spl-dtb { }; @@ -54,7 +54,7 @@ }; #elif defined(CONFIG_SPL) u-boot-spl-with-ucode-ptr { - offset = <CONFIG_SPL_TEXT_BASE>; + offset = <CONFIG_X86_OFFSET_SPL>; }; u-boot-dtb-with-ucode2 { type = "u-boot-dtb-with-ucode"; |