Merge git://git.denx.de/u-boot-x86

12 files changed, 64 insertions, 78 deletions

diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index 392c258945..93f61f2fa4 100644
--- a/arch/x86/cpu/coreboot/Kconfig
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -3,26 +3,26 @@ if TARGET_COREBOOT
 config SYS_COREBOOT
 	bool
 	default y
+	imply SYS_NS16550
+	imply SCSI
+	imply SCSI_AHCI
 	imply AHCI_PCI
-	imply E1000
-	imply ICH_SPI
 	imply MMC
 	imply MMC_PCI
 	imply MMC_SDHCI
 	imply MMC_SDHCI_SDMA
-	imply SCSI
-	imply SCSI_AHCI
-	imply SPI_FLASH
-	imply SYS_NS16550
 	imply USB
 	imply USB_EHCI_HCD
 	imply USB_XHCI_HCD
+	imply USB_STORAGE
+	imply USB_KEYBOARD
 	imply VIDEO_COREBOOT
+	imply E1000
+	imply ETH_DESIGNWARE
+	imply PCH_GBE
+	imply RTL8169
 	imply CMD_CBFS
 	imply FS_CBFS
-
-config CBMEM_CONSOLE
-	bool
-	default y
+	imply CBMEM_CONSOLE
 
 endif
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 69025c1537..a6fd3a849a 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -7,6 +7,7 @@
 
 #include <common.h>
 #include <fdtdec.h>
+#include <usb.h>
 #include <asm/io.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
@@ -75,12 +76,10 @@ int last_stage_init(void)
 	if (gd->flags & GD_FLG_COLD_BOOT)
 		timestamp_add_to_bootstage();
 
-	board_final_cleanup();
+	/* start usb so that usb keyboard can be used as input device */
+	usb_init();
 
-	return 0;
-}
+	board_final_cleanup();
 
-int misc_init_r(void)
-{
 	return 0;
 }
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 37e4fdc760..fa717bc096 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -6,6 +6,7 @@ dtb-y += bayleybay.dtb \
 	chromebox_panther.dtb \
 	chromebook_samus.dtb \
 	conga-qeval20-qa3-e3845.dtb \
+	coreboot.dtb \
 	cougarcanyon2.dtb \
 	crownbay.dtb \
 	dfi-bt700-q7x-151.dtb \
@@ -17,7 +18,6 @@ dtb-y += bayleybay.dtb \
 	qemu-x86_i440fx.dtb \
 	qemu-x86_q35.dtb \
 	theadorable-x86-dfi-bt700.dtb \
-	broadwell_som-6896.dtb \
 	baytrail_som-db5800-som-6867.dtb
 
 targets += $(dtb-y)
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 9683c525a7..291dc07ff6 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -15,7 +15,6 @@
 /include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
-/include/ "coreboot_fb.dtsi"
 
 / {
 	model = "Intel Bayley Bay";
diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts
deleted file mode 100644
index ec691f136a..0000000000
--- a/arch/x86/dts/broadwell_som-6896.dts
+++ /dev/null
@@ -1,52 +0,0 @@
-/dts-v1/;
-
-/include/ "skeleton.dtsi"
-/include/ "serial.dtsi"
-/include/ "reset.dtsi"
-/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
-/include/ "coreboot_fb.dtsi"
-
-/ {
-	model = "Advantech SOM-6896";
-	compatible = "advantech,som-6896", "intel,broadwell";
-
-	aliases {
-		spi0 = &spi;
-	};
-
-	config {
-	       silent_console = <0>;
-	};
-
-	chosen {
-		stdout-path = "/serial";
-	};
-
-	pci {
-		compatible = "pci-x86";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		u-boot,dm-pre-reloc;
-		ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
-			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
-			0x01000000 0x0 0x2000 0x2000 0 0xe000>;
-
-		pch@1f,0 {
-			reg = <0x0000f800 0 0 0 0>;
-			compatible = "intel,pch9";
-
-			spi: spi {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "intel,ich9-spi";
-				spi-flash@0 {
-					reg = <0>;
-					compatible = "winbond,w25q128", "spi-flash";
-					memory-map = <0xff000000 0x01000000>;
-				};
-			};
-		};
-	};
-
-};
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 115a088a7a..f9f0979730 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -8,7 +8,6 @@
 /include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
-/include/ "coreboot_fb.dtsi"
 
 / {
 	model = "Google Link";
diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
index 9c48c9a3fa..b58936b4ac 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -8,7 +8,6 @@
 /include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
-/include/ "coreboot_fb.dtsi"
 
 / {
 	model = "Google Samus";
diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
index a72a85ef9c..f56e482944 100644
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -5,7 +5,6 @@
 /include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
-/include/ "coreboot_fb.dtsi"
 
 / {
 	model = "Google Panther";
diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
new file mode 100644
index 0000000000..e212f3dc7d
--- /dev/null
+++ b/arch/x86/dts/coreboot.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Generic coreboot payload device tree for x86 targets
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+/include/ "keyboard.dtsi"
+/include/ "reset.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+	model = "coreboot x86 payload";
+	compatible = "coreboot,x86-payload";
+
+	aliases {
+		serial0 = &serial;
+	};
+
+	config {
+		silent_console = <0>;
+	};
+
+	chosen {
+		stdout-path = "/serial";
+	};
+
+	tsc-timer {
+		clock-frequency = <1000000000>;
+	};
+
+	pci {
+		compatible = "pci-x86";
+		u-boot,dm-pre-reloc;
+	};
+
+	coreboot-fb {
+		compatible = "coreboot-fb";
+	};
+};
diff --git a/arch/x86/dts/coreboot_fb.dtsi b/arch/x86/dts/coreboot_fb.dtsi
deleted file mode 100644
index 7d72f18537..0000000000
--- a/arch/x86/dts/coreboot_fb.dtsi
+++ /dev/null
@@ -1,5 +0,0 @@
-/ {
-	coreboot-fb {
-		compatible = "coreboot-fb";
-	};
-};
diff --git a/arch/x86/dts/efi-x86_payload.dts b/arch/x86/dts/efi-x86_payload.dts
index 19f253064b..5ccb986774 100644
--- a/arch/x86/dts/efi-x86_payload.dts
+++ b/arch/x86/dts/efi-x86_payload.dts
@@ -30,6 +30,10 @@
 		stdout-path = "/serial";
 	};
 
+	tsc-timer {
+		clock-frequency = <1000000000>;
+	};
+
 	pci {
 		compatible = "pci-x86";
 		u-boot,dm-pre-reloc;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 02ab4c160a..6c65fb9611 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -14,7 +14,6 @@
 /include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
-/include/ "coreboot_fb.dtsi"
 
 / {
 	model = "Intel Minnowboard Max";