diff options
| author | Bai Ping <ping.bai@nxp.com> | 2019-07-22 01:24:45 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-10-08 16:35:16 +0200 |
| commit | 3ed6734e698e4280361f1a509856c50b07861c99 (patch) | |
| tree | 2167028c54a52fb6cd19a5b57be02c2099e2407c /arch | |
| parent | 7777406a8a023bdfe18d106138c61eeaa15dd5b4 (diff) | |
i.MX7ULP: Correct the clock index
On i.MX7ULP, value zero is reserved in SCG1 RCCR register,
so the val should be decreased by 1 to get the correct clock
source index.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/mx7ulp/scg.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index b4f2ea875a..85d726fe30 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -440,7 +440,7 @@ static u32 scg_sys_get_rate(enum scg_clk clk) case SCG_SCS_SLOW_IRC: case SCG_SCS_FAST_IRC: case SCG_SCS_RTC_OSC: - rate = scg_src_get_rate(scg_scs_array[val]); + rate = scg_src_get_rate(scg_scs_array[val - 1]); break; case 5: rate = scg_apll_get_rate(); |