diff options
| author | Yuan Yao <yao.yuan@nxp.com> | 2016-06-08 18:24:57 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-06-10 13:45:00 -0700 |
| commit | 453418f2d2df33f370754582b7e21d2513e2ee28 (patch) | |
| tree | eaabfae1d46c54df5b1ba7b402c2e77807c4e164 /arch | |
| parent | 95ab851de0de317e07a843d23bfaeb89d94575f8 (diff) | |
armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index f75bd391e3..8d12d6cb93 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -129,6 +129,8 @@ #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 #define DCFG_RCWSR13 0x130 #define DCFG_RCWSR13_DSPI (0 << 8) +#define DCFG_RCWSR15 0x138 +#define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3 #define DCFG_DCSR_BASE 0X700100000ULL #define DCFG_DCSR_PORCR1 0x000 |