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authorSuneel Garapati <sgarapati@marvell.com>2019-10-19 17:10:20 -0700
committerStefan Roese <sr@denx.de>2020-08-25 08:01:16 +0200
commit4cf56ec07f673f99c87862dbb7e72bc077685474 (patch)
treed40e8b752e61d666aab70f047b008e6ef30634c3 /arch
parentbc30140d20d041a6ed5d52175e9953c36f8f5473 (diff)
pci: pci-uclass: Add multi entry support for memory regions
Enable PCI memory regions in ranges property to be of multiple entry. This helps to add support for SoC's like OcteonTX/TX2 where every peripheral is on PCI bus. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/sandbox/dts/test.dts5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 1d8956abbe..9f45c48e4e 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -666,8 +666,9 @@
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
- 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
+ ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
+ 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
+ 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
sandbox,dev-info = <0x08 0x00 0x1234 0x5678
0x0c 0x00 0x1234 0x5678
0x10 0x00 0x1234 0x5678>;