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| author | Tom Rini <trini@konsulko.com> | 2018-12-21 13:38:09 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-12-21 13:38:09 -0500 |
| commit | 562a63e86bc7b308a328a7bbdf0db237855c39a8 (patch) | |
| tree | 4a43bc9ed8e360e64bf130224c599e866af18194 /arch | |
| parent | 5c676780e116dc79c1819d6c49a2aa53e1053e04 (diff) | |
| parent | 7a147220c6459aeb7c6b6f7afe4330dcce077c9b (diff) | |
Merge git://git.denx.de/u-boot-marvell
- Fix breakage in helios4: Change U-Boot offset on SPI Flash
- Enable CONFIG_BLK for db-88f6820-amc
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mvebu/cpu.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index aa1be8ebab..919d05c88c 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -283,10 +283,8 @@ int print_cpuinfo(void) * and sets the correct windows sizes and base addresses accordingly. * * These values are set in the scratch registers by the Marvell - * DDR3 training code, which is executed by the BootROM before the - * main payload (U-Boot) is executed. This training code is currently - * only available in the Marvell U-Boot version. It needs to be - * ported to mainline U-Boot SPL at some point. + * DDR3 training code, which is executed by the SPL before the + * main payload (U-Boot) is executed. */ static void update_sdram_window_sizes(void) { |