Merge branch 'master' of git://git.denx.de/u-boot-nios

* 'master' of git://git.denx.de/u-boot-nios:
  nios2 - adjust gbl data off to account for bd_info
  nios2: implement get_ticks and get_tbclk
  nios2: add flush_dcache_range function

2 files changed, 31 insertions, 0 deletions

diff --git a/arch/nios2/cpu/interrupts.c b/arch/nios2/cpu/interrupts.c
index 0a97fa6b6b..2ce689f63f 100644
--- a/arch/nios2/cpu/interrupts.c
+++ b/arch/nios2/cpu/interrupts.c
@@ -98,6 +98,27 @@ ulong get_timer (ulong base)
 	return (timestamp - base);
 }
 
+/*
+ * This function is derived from Blackfin code (read timebase as long long).
+ * On Nios2 it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from Blackfin code.
+ * On Nios2 it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+	return tbclk;
+}
+
 /* The board must handle this interrupt if a timer is not
  * provided.
  */
diff --git a/arch/nios2/lib/cache.S b/arch/nios2/lib/cache.S
index ee3b4b79bf..b952d0c901 100644
--- a/arch/nios2/lib/cache.S
+++ b/arch/nios2/lib/cache.S
@@ -48,6 +48,16 @@ flush_icache:
 	bltu	r4, r5, 1b
 	ret
 
+	.global flush_dcache_range
+
+flush_dcache_range:
+	movhi	r8, %hi(CONFIG_SYS_DCACHELINE_SIZE)
+	ori	r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE)
+0:	flushd	0(r4)
+	add	r4, r4, r8
+	bltu	r4, r5, 0b
+	ret
+
 	.global flush_cache
 
 flush_cache: