Merge git://git.denx.de/u-boot

author: Stefano Babic <sbabic@denx.de> 2015-11-12 17:13:26 +0100
committer: Stefano Babic <sbabic@denx.de> 2015-11-12 17:13:26 +0100
commit: 5f5620ab2679608f94b3a77e51c77d0a770103bd (patch)
tree: ec983c06d2f62384909968bb870add121b8a1502 /arch
parent: 78e9ca52edaab74ad645d719676ff4c24d2f462c (diff)
parent: 038be18fd95aa6283eafb85ceabc0b880976424b (diff)
208 files changed, 4699 insertions, 1954 deletions
diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile
index 5bc6f44c1a..d481fcdc69 100644
--- a/arch/arc/dts/Makefile
+++ b/arch/arc/dts/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 dtb-$(CONFIG_TARGET_ARCANGEL4) +=  arcangel4.dtb
 dtb-$(CONFIG_TARGET_TB100) +=  abilis_tb100.dtb
 
diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h
index 85721aaee3..370cb46e9f 100644
--- a/arch/arc/include/asm/bitops.h
+++ b/arch/arc/include/asm/bitops.h
@@ -16,4 +16,9 @@
 #define hweight16(x) generic_hweight16(x)
 #define hweight8(x) generic_hweight8(x)
 
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
 #endif /* __ASM_ARC_BITOPS_H */
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2632099874..5ab0254f3b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -10,6 +10,9 @@ config ARM64
 config HAS_VBAR
         bool
 
+config HAS_THUMB2
+        bool
+
 config CPU_ARM720T
         bool
 
@@ -32,9 +35,11 @@ config CPU_ARM1176
 config CPU_V7
         bool
         select HAS_VBAR
+        select HAS_THUMB2
 
 config CPU_V7M
 	bool
+        select HAS_THUMB2
 
 config CPU_PXA
         bool
@@ -543,13 +548,20 @@ config ARCH_ZYNQ
 	select CPU_V7
 	select SUPPORT_SPL
 	select OF_CONTROL
+	select SPL_OF_CONTROL
 	select DM
+	select SPL_DM
 	select DM_SPI
+	select DM_SERIAL
 	select DM_SPI_FLASH
+	select SPL_SEPARATE_BSS
 
 config ARCH_ZYNQMP
 	bool "Support Xilinx ZynqMP Platform"
 	select ARM64
+	select DM
+	select OF_CONTROL
+	select DM_SERIAL
 
 config TEGRA
 	bool "NVIDIA Tegra"
@@ -627,6 +639,14 @@ config TARGET_LS1021ATWR
 	select CPU_V7
 	select SUPPORT_SPL
 
+config TARGET_LS1043ARDB
+	bool "Support ls1043ardb"
+	select ARM64
+	select ARMV8_MULTIENTRY
+	select SUPPORT_SPL
+	help
+	  Support for Freescale LS1043ARDB platform.
+
 config TARGET_H2200
 	bool "Support h2200"
 	select CPU_PXA
@@ -743,6 +763,7 @@ source "board/freescale/ls2085aqds/Kconfig"
 source "board/freescale/ls2085ardb/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
+source "board/freescale/ls1043ardb/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index 6bea3d3a2d..950e680c7a 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -1 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 obj- += dummy.o
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 63fa159db6..fe78922170 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -20,3 +20,14 @@ obj-$(CONFIG_MX25) += mx25/
 obj-$(CONFIG_MX27) += mx27/
 obj-$(if $(filter mxs,$(SOC)),y) += mxs/
 obj-$(if $(filter spear,$(SOC)),y) += spear/
+
+# some files can only build in ARM or THUMB2, not THUMB1
+
+ifdef CONFIG_SYS_THUMB_BUILD
+ifndef CONFIG_HAS_THUMB2
+
+CFLAGS_cpu.o := -marm
+CFLAGS_cache.o := -marm
+
+endif
+endif
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index e5c1a6ae6c..2839c863e8 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -82,4 +82,9 @@ void flush_dcache_all(void)
 /*
  * Stub implementations for l2 cache operations
  */
+
 __weak void l2_cache_disable(void) {}
+
+#if defined CONFIG_SYS_THUMB_BUILD
+__weak void invalidate_l2_cache(void) {}
+#endif
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile
index 2d55782749..2311468ac9 100644
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -9,6 +9,7 @@ obj-y	+= clock.o
 obj-y	+= timer.o
 obj-y	+= fsl_epu.o
 
+obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
 obj-$(CONFIG_SPL) += spl.o
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index e2eb5f383a..df2e1b76f1 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -301,6 +301,7 @@ int arch_cpu_init(void)
 	void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 	void *rcpm2_base =
 		(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+	struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
 	u32 state;
 
 	/*
@@ -328,6 +329,8 @@ int arch_cpu_init(void)
 	 */
 	fsl_epu_clean(epu_base);
 
+	setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
+
 	return 0;
 }
 
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index e01d911780..856abed941 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -171,7 +171,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
 			       "clock-frequency", busclk / 2, 1);
 
-#ifdef CONFIG_QSPI_BOOT
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 	off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
 					    CONFIG_SYS_IFC_ADDR);
 	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
new file mode 100644
index 0000000000..deeb674c69
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <ahci.h>
+#include <scsi.h>
+
+/* port register default value */
+#define AHCI_PORT_PHY_1_CFG	0xa003fffe
+#define AHCI_PORT_PHY_2_CFG	0x28183411
+#define AHCI_PORT_PHY_3_CFG	0x0e081004
+#define AHCI_PORT_PHY_4_CFG	0x00480811
+#define AHCI_PORT_PHY_5_CFG	0x192c96a4
+#define AHCI_PORT_TRANS_CFG	0x08000025
+
+#define SATA_ECC_REG_ADDR	0x20220520
+#define SATA_ECC_DISABLE	0x00020000
+
+int ls1021a_sata_init(void)
+{
+	struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
+	out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE);
+#endif
+
+	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
+	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
+	out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG);
+	out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG);
+	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+	ahci_init((void __iomem *)AHCI_BASE_ADDR);
+	scsi_scan(0);
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/s5p-common/cpu_info.c b/arch/arm/cpu/armv7/s5p-common/cpu_info.c
index 154d67490d..764c6614ea 100644
--- a/arch/arm/cpu/armv7/s5p-common/cpu_info.c
+++ b/arch/arm/cpu/armv7/s5p-common/cpu_info.c
@@ -5,9 +5,12 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include <fdtdec.h>
 #include <asm/io.h>
 #include <asm/arch/clk.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Default is s5pc100 */
 unsigned int s5p_cpu_id = 0xC100;
 /* Default is EVT1 */
@@ -30,7 +33,16 @@ u32 get_device_type(void)
 #ifdef CONFIG_DISPLAY_CPUINFO
 int print_cpuinfo(void)
 {
-	printf("CPU:   %s%X @ ", s5p_get_cpu_name(), s5p_cpu_id);
+	const char *cpu_model;
+	int len;
+
+	/* For SoC with no real CPU ID in naming convention. */
+	cpu_model = fdt_getprop(gd->fdt_blob, 0, "cpu-model", &len);
+	if (cpu_model)
+		printf("CPU:   %.*s @ ", len, cpu_model);
+	else
+		printf("CPU:   %s%X @ ", s5p_get_cpu_name(), s5p_cpu_id);
+
 	print_freq(get_arm_clk(), "\n");
 
 	return 0;
diff --git a/arch/arm/cpu/armv7m/stm32f4/flash.c b/arch/arm/cpu/armv7m/stm32f4/flash.c
index e5c6111330..dd058bd643 100644
--- a/arch/arm/cpu/armv7m/stm32f4/flash.c
+++ b/arch/arm/cpu/armv7m/stm32f4/flash.c
@@ -97,6 +97,9 @@ int flash_erase(flash_info_t *info, int first, int last)
 		while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
 			;
 
+		/* clear old sector number before writing a new one */
+		clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SNB_MASK);
+
 		if (bank == 0) {
 			setbits_le32(&STM32_FLASH->cr,
 				     (i << STM32_FLASH_CR_SNB_OFFSET));
@@ -114,9 +117,9 @@ int flash_erase(flash_info_t *info, int first, int last)
 			;
 
 		clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
-		stm32f4_flash_lock(1);
 	}
 
+	stm32f4_flash_lock(1);
 	return 0;
 }
 
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index adb11b3bda..48c041bb9b 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -15,6 +15,6 @@ obj-y	+= cache.o
 obj-y	+= tlb.o
 obj-y	+= transition.o
 
-obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
+obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
 obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index b1ea8227cb..1ece6a2c12 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -32,7 +32,7 @@ inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr)
 }
 
 /* to activate the MMU we need to set up virtual memory */
-static void mmu_setup(void)
+__weak void mmu_setup(void)
 {
 	bd_t *bd = gd->bd;
 	u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
new file mode 100644
index 0000000000..6fa08c8f3c
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -0,0 +1,30 @@
+#
+# Copyright 2014-2015, Freescale Semiconductor
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += lowlevel.o
+obj-y += soc.o
+obj-$(CONFIG_MP) += mp.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_SPL) += spl.o
+
+ifneq ($(CONFIG_FSL_LSCH3),)
+obj-y += fsl_lsch3_speed.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o
+else
+ifneq ($(CONFIG_FSL_LSCH2),)
+obj-y += fsl_lsch2_speed.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o
+endif
+endif
+
+ifneq ($(CONFIG_LS2085A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o
+else
+ifneq ($(CONFIG_LS1043A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
+endif
+endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
new file mode 100644
index 0000000000..a6ef830069
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
@@ -0,0 +1,10 @@
+#
+# Copyright 2015 Freescale Semiconductor
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+Freescale LayerScape with Chassis Generation 2
+
+This architecture supports Freescale ARMv8 SoCs with Chassis generation 2,
+for example LS1043A.
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
index 08da7e4d1d..03e18f6573 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/README
+++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
@@ -1,5 +1,5 @@
 #
-# Copyright 2014 Freescale Semiconductor
+# Copyright 2014-2015 Freescale Semiconductor
 #
 # SPDX-License-Identifier:      GPL-2.0+
 #
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index eb1213e9f0..0cb0afa0b3 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -10,34 +10,28 @@
 #include <asm/system.h>
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
-#include <asm/arch-fsl-lsch3/soc.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/speed.h>
+#ifdef CONFIG_MP
+#include <asm/arch/mp.h>
+#endif
+#include <fm_eth.h>
 #include <fsl_debug_server.h>
 #include <fsl-mc/fsl_mc.h>
-#include <asm/arch/fsl_serdes.h>
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
-#include "cpu.h"
-#include "mp.h"
-#include "speed.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct cpu_type cpu_type_list[] = {
-#ifdef CONFIG_LS2085A
-	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
-	CPU_TYPE_ENTRY(LS2080, LS2080, 8),
-	CPU_TYPE_ENTRY(LS2045, LS2045, 4),
-#endif
-};
-
 void cpu_name(char *name)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	unsigned int i, svr, ver;
 
-	svr = in_le32(&gur->svr);
+	svr = gur_in32(&gur->svr);
 	ver = SVR_SOC_VER(svr);
 
 	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
@@ -54,146 +48,6 @@ void cpu_name(char *name)
 }
 
 #ifndef CONFIG_SYS_DCACHE_OFF
-
-#define SECTION_SHIFT_L0		39UL
-#define SECTION_SHIFT_L1		30UL
-#define SECTION_SHIFT_L2		21UL
-#define BLOCK_SIZE_L0			0x8000000000
-#define BLOCK_SIZE_L1			0x40000000
-#define BLOCK_SIZE_L2			0x200000
-
-#define NUM_OF_ENTRY		512
-
-#define TCR_EL2_PS_40BIT	(2 << 16)
-#define LSCH3_VA_BITS		(40)
-#define LSCH3_TCR	(TCR_TG0_4K		| \
-			TCR_EL2_PS_40BIT	| \
-			TCR_SHARED_NON		| \
-			TCR_ORGN_NC		| \
-			TCR_IRGN_NC		| \
-			TCR_T0SZ(LSCH3_VA_BITS))
-#define LSCH3_TCR_FINAL	(TCR_TG0_4K		| \
-			TCR_EL2_PS_40BIT	| \
-			TCR_SHARED_OUTER	| \
-			TCR_ORGN_WBWA		| \
-			TCR_IRGN_WBWA		| \
-			TCR_T0SZ(LSCH3_VA_BITS))
-
-#define CONFIG_SYS_FSL_CCSR_BASE	0x00000000
-#define CONFIG_SYS_FSL_CCSR_SIZE	0x10000000
-#define CONFIG_SYS_FSL_QSPI_BASE1	0x20000000
-#define CONFIG_SYS_FSL_QSPI_SIZE1	0x10000000
-#define CONFIG_SYS_FSL_IFC_BASE1	0x30000000
-#define CONFIG_SYS_FSL_IFC_SIZE1	0x10000000
-#define CONFIG_SYS_FSL_IFC_SIZE1_1	0x400000
-#define CONFIG_SYS_FSL_DRAM_BASE1	0x80000000
-#define CONFIG_SYS_FSL_DRAM_SIZE1	0x80000000
-#define CONFIG_SYS_FSL_QSPI_BASE2	0x400000000
-#define CONFIG_SYS_FSL_QSPI_SIZE2	0x100000000
-#define CONFIG_SYS_FSL_IFC_BASE2	0x500000000
-#define CONFIG_SYS_FSL_IFC_SIZE2	0x100000000
-#define CONFIG_SYS_FSL_DCSR_BASE	0x700000000
-#define CONFIG_SYS_FSL_DCSR_SIZE	0x40000000
-#define CONFIG_SYS_FSL_MC_BASE		0x80c000000
-#define CONFIG_SYS_FSL_MC_SIZE		0x4000000
-#define CONFIG_SYS_FSL_NI_BASE		0x810000000
-#define CONFIG_SYS_FSL_NI_SIZE		0x8000000
-#define CONFIG_SYS_FSL_QBMAN_BASE	0x818000000
-#define CONFIG_SYS_FSL_QBMAN_SIZE	0x8000000
-#define CONFIG_SYS_FSL_QBMAN_SIZE_1	0x4000000
-#define CONFIG_SYS_PCIE1_PHYS_SIZE	0x200000000
-#define CONFIG_SYS_PCIE2_PHYS_SIZE	0x200000000
-#define CONFIG_SYS_PCIE3_PHYS_SIZE	0x200000000
-#define CONFIG_SYS_PCIE4_PHYS_SIZE	0x200000000
-#define CONFIG_SYS_FSL_WRIOP1_BASE	0x4300000000
-#define CONFIG_SYS_FSL_WRIOP1_SIZE	0x100000000
-#define CONFIG_SYS_FSL_AIOP1_BASE	0x4b00000000
-#define CONFIG_SYS_FSL_AIOP1_SIZE	0x100000000
-#define CONFIG_SYS_FSL_PEBUF_BASE	0x4c00000000
-#define CONFIG_SYS_FSL_PEBUF_SIZE	0x400000000
-#define CONFIG_SYS_FSL_DRAM_BASE2	0x8080000000
-#define CONFIG_SYS_FSL_DRAM_SIZE2	0x7F80000000
-
-struct sys_mmu_table {
-	u64 virt_addr;
-	u64 phys_addr;
-	u64 size;
-	u64 memory_type;
-	u64 share;
-};
-
-static const struct sys_mmu_table lsch3_early_mmu_table[] = {
-	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
-	/* For IFC Region #1, only the first 4MB is cache-enabled */
-	{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
-	  CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
-	{ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
-	  CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
-	  CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
-	  MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
-	  CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
-	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
-};
-
-static const struct sys_mmu_table lsch3_final_mmu_table[] = {
-	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
-	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
-	{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
-	  CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
-	  CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-	{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
-	  CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-	{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
-	  CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-	/* For QBMAN portal, only the first 64MB is cache-enabled */
-	{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
-	  CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
-	{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
-	  CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
-	  CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
-	  MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-	  CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-	  CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-	  CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-#ifdef CONFIG_LS2085A
-	{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
-	  CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-#endif
-	{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
-	  CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-	{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
-	  CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-	{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
-	  CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
-};
-
-struct table_info {
-	u64 *ptr;
-	u64 table_base;
-	u64 entry_size;
-};
-
 /*
  * Set the block entries according to the information of the table.
  */
@@ -311,6 +165,7 @@ static inline void early_mmu_setup(void)
 	u64 *level1_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
 	u64 *level2_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
 	u64 *level2_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000);
+
 	struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
 
 	/* Invalidate all table entries */
@@ -320,19 +175,23 @@ static inline void early_mmu_setup(void)
 	set_pgtable_table(level0_table, 0, level1_table0);
 	set_pgtable_table(level0_table, 1, level1_table1);
 	set_pgtable_table(level1_table0, 0, level2_table0);
+
+#ifdef CONFIG_FSL_LSCH3
 	set_pgtable_table(level1_table0,
 			  CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1,
 			  level2_table1);
-
+#elif defined(CONFIG_FSL_LSCH2)
+	set_pgtable_table(level1_table0, 1, level2_table1);
+#endif
 	/* Find the table and fill in the block entries */
-	for (i = 0; i < ARRAY_SIZE(lsch3_early_mmu_table); i++) {
-		if (find_table(&lsch3_early_mmu_table[i],
+	for (i = 0; i < ARRAY_SIZE(early_mmu_table); i++) {
+		if (find_table(&early_mmu_table[i],
 			       &table, level0_table) == 0) {
 			/*
 			 * If find_table() returns error, it cannot be dealt
 			 * with here. Breakpoint can be added for debugging.
 			 */
-			set_block_entry(&lsch3_early_mmu_table[i], &table);
+			set_block_entry(&early_mmu_table[i], &table);
 			/*
 			 * If set_block_entry() returns error, it cannot be
 			 * dealt with here too.
@@ -341,7 +200,9 @@ static inline void early_mmu_setup(void)
 	}
 
 	el = current_el();
-	set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR, MEMORY_ATTRIBUTES);
+
+	set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR,
+			  MEMORY_ATTRIBUTES);
 	set_sctlr(get_sctlr() | CR_M);
 }
 
@@ -353,7 +214,12 @@ static inline void early_mmu_setup(void)
  * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB.
  * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB.
  * Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB.
+ *
+ * For LSCH3:
  * Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB.
+ * For LSCH2:
+ * Level 2 table 1 contains 512 entries for each 2MB from 1GB to 2GB.
+ * Level 2 table 2 contains 512 entries for each 2MB from 20GB to 21GB.
  */
 static inline void final_mmu_setup(void)
 {
@@ -362,7 +228,12 @@ static inline void final_mmu_setup(void)
 	u64 *level1_table0 = (u64 *)(gd->arch.tlb_addr + 0x1000);
 	u64 *level1_table1 = (u64 *)(gd->arch.tlb_addr + 0x2000);
 	u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000);
+#ifdef CONFIG_FSL_LSCH3
+	u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
+#elif defined(CONFIG_FSL_LSCH2)
 	u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
+	u64 *level2_table2 = (u64 *)(gd->arch.tlb_addr + 0x5000);
+#endif
 	struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
 
 	/* Invalidate all table entries */
@@ -372,23 +243,30 @@ static inline void final_mmu_setup(void)
 	set_pgtable_table(level0_table, 0, level1_table0);
 	set_pgtable_table(level0_table, 1, level1_table1);
 	set_pgtable_table(level1_table0, 0, level2_table0);
+#ifdef CONFIG_FSL_LSCH3
 	set_pgtable_table(level1_table0,
 			  CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
 			  level2_table1);
+#elif defined(CONFIG_FSL_LSCH2)
+	set_pgtable_table(level1_table0, 1, level2_table1);
+	set_pgtable_table(level1_table0,
+			  CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
+			  level2_table2);
+#endif
 
 	/* Find the table and fill in the block entries */
-	for (i = 0; i < ARRAY_SIZE(lsch3_final_mmu_table); i++) {
-		if (find_table(&lsch3_final_mmu_table[i],
+	for (i = 0; i < ARRAY_SIZE(final_mmu_table); i++) {
+		if (find_table(&final_mmu_table[i],
 			       &table, level0_table) == 0) {
-			if (set_block_entry(&lsch3_final_mmu_table[i],
+			if (set_block_entry(&final_mmu_table[i],
 					    &table) != 0) {
 				printf("MMU error: could not set block entry for %p\n",
-				       &lsch3_final_mmu_table[i]);
+				       &final_mmu_table[i]);
 			}
 
 		} else {
 			printf("MMU error: could not find the table for %p\n",
-			       &lsch3_final_mmu_table[i]);
+			       &final_mmu_table[i]);
 		}
 	}
 
@@ -396,9 +274,13 @@ static inline void final_mmu_setup(void)
 	flush_dcache_range(gd->arch.tlb_addr,
 			   gd->arch.tlb_addr + gd->arch.tlb_size);
 
+#ifdef CONFIG_SYS_DPAA_FMAN
+	flush_dcache_all();
+#endif
 	/* point TTBR to the new table */
 	el = current_el();
-	set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR_FINAL,
+
+	set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL,
 			  MEMORY_ATTRIBUTES);
 	/*
 	 * MMU is already enabled, just need to invalidate TLB to load the
@@ -434,8 +316,9 @@ static inline u32 initiator_type(u32 cluster, int init_id)
 {
 	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
-	u32 type = in_le32(&gur->tp_ityp[idx]);
+	u32 type = 0;
 
+	type = gur_in32(&gur->tp_ityp[idx]);
 	if (type & TP_ITYP_AV)
 		return type;
 
@@ -450,7 +333,8 @@ u32 cpu_mask(void)
 
 	do {
 		int j;
-		cluster = in_le32(&gur->tp_cluster[i].lower);
+
+		cluster = gur_in32(&gur->tp_cluster[i].lower);
 		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 			type = initiator_type(cluster, j);
 			if (type) {
@@ -460,7 +344,7 @@ u32 cpu_mask(void)
 			}
 		}
 		i++;
-	} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+	} while ((cluster & TP_CLUSTER_EOC) == 0x0);
 
 	return mask;
 }
@@ -482,7 +366,8 @@ int fsl_qoriq_core_to_cluster(unsigned int core)
 
 	do {
 		int j;
-		cluster = in_le32(&gur->tp_cluster[i].lower);
+
+		cluster = gur_in32(&gur->tp_cluster[i].lower);
 		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 			if (initiator_type(cluster, j)) {
 				if (count == core)
@@ -491,7 +376,7 @@ int fsl_qoriq_core_to_cluster(unsigned int core)
 			}
 		}
 		i++;
-	} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+	} while ((cluster & TP_CLUSTER_EOC) == 0x0);
 
 	return -1;      /* cannot identify the cluster */
 }
@@ -505,7 +390,8 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
 
 	do {
 		int j;
-		cluster = in_le32(&gur->tp_cluster[i].lower);
+
+		cluster = gur_in32(&gur->tp_cluster[i].lower);
 		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 			type = initiator_type(cluster, j);
 			if (type) {
@@ -515,7 +401,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
 			}
 		}
 		i++;
-	} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+	} while ((cluster & TP_CLUSTER_EOC) == 0x0);
 
 	return -1;      /* cannot identify the cluster */
 }
@@ -527,15 +413,13 @@ int print_cpuinfo(void)
 	struct sys_info sysinfo;
 	char buf[32];
 	unsigned int i, core;
-	u32 type;
+	u32 type, rcw;
 
 	puts("SoC: ");
 
 	cpu_name(buf);
-	printf(" %s (0x%x)\n", buf, in_le32(&gur->svr));
-
+	printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr));
 	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
-
 	get_sys_info(&sysinfo);
 	puts("Clock Configuration:");
 	for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
@@ -551,18 +435,23 @@ int print_cpuinfo(void)
 	printf("\n       Bus:      %-4s MHz  ",
 	       strmhz(buf, sysinfo.freq_systembus));
 	printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
+#ifdef CONFIG_SYS_DPAA_FMAN
+	printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
+#endif
+#ifdef CONFIG_FSL_LSCH3
 	printf("     DP-DDR:   %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
+#endif
 	puts("\n");
 
-	/* Display the RCW, so that no one gets confused as to what RCW
+	/*
+	 * Display the RCW, so that no one gets confused as to what RCW
 	 * we're actually using for this boot.
 	 */
 	puts("Reset Configuration Word (RCW):");
 	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
-		u32 rcw = in_le32(&gur->rcwsr[i]);
-
+		rcw = gur_in32(&gur->rcwsr[i]);
 		if ((i % 4) == 0)
-			printf("\n       %02x:", i * 4);
+			printf("\n       %08x:", i * 4);
 		printf(" %08x", rcw);
 	}
 	puts("\n");
@@ -585,27 +474,37 @@ int cpu_eth_init(bd_t *bis)
 #ifdef CONFIG_FSL_MC_ENET
 	error = fsl_mc_ldpaa_init(bis);
 #endif
+#ifdef CONFIG_FMAN_ENET
+	fm_standard_init(bis);
+#endif
 	return error;
 }
 
 int arch_early_init_r(void)
 {
-	int rv;
-	rv = fsl_lsch3_wake_seconday_cores();
+#ifdef CONFIG_MP
+	int rv = 1;
 
+	rv = fsl_layerscape_wake_seconday_cores();
 	if (rv)
 		printf("Did not wake secondary cores\n");
+#endif
 
 #ifdef CONFIG_SYS_HAS_SERDES
 	fsl_serdes_init();
 #endif
+#ifdef CONFIG_FMAN_ENET
+	fman_enet_init();
+#endif
 	return 0;
 }
 
 int timer_init(void)
 {
 	u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+#ifdef CONFIG_FSL_LSCH3
 	u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+#endif
 #ifdef COUNTER_FREQUENCY_REAL
 	unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
 
@@ -613,10 +512,12 @@ int timer_init(void)
 	asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
 #endif
 
+#ifdef CONFIG_FSL_LSCH3
 	/* Enable timebase for all clusters.
 	 * It is safe to do so even some clusters are not enabled.
 	 */
 	out_le32(cltbenr, 0xf);
+#endif
 
 	/* Enable clock for timer
 	 * This is a global setting.
@@ -632,7 +533,7 @@ void reset_cpu(ulong addr)
 	u32 val;
 
 	/* Raise RESET_REQ_B */
-	val = in_le32(rstcr);
+	val = scfg_in32(rstcr);
 	val |= 0x02;
-	out_le32(rstcr, val);
+	scfg_out32(rstcr, val);
 }
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
index 2e3312b99b..8072f3ca6a 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014, Freescale Semiconductor
+ * Copyright 2014-2015, Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 567c41927a..47599c1217 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -7,11 +7,22 @@
 #include <common.h>
 #include <libfdt.h>
 #include <fdt_support.h>
-#include <asm/arch-fsl-lsch3/fdt.h>
+#include <phy.h>
+#ifdef CONFIG_FSL_LSCH3
+#include <asm/arch/fdt.h>
+#endif
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
-#include "mp.h"
+#ifdef CONFIG_MP
+#include <asm/arch/mp.h>
+#endif
+
+int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
+{
+	return fdt_setprop_string(blob, offset, "phy-connection-type",
+					 phy_string_for_interface(phyc));
+}
 
 #ifdef CONFIG_MP
 void ft_fixup_cpu(void *blob)
@@ -33,8 +44,8 @@ void ft_fixup_cpu(void *blob)
 	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 	while (off != -FDT_ERR_NOTFOUND) {
 		reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
-		core_id = of_read_number(reg, addr_cells);
 		if (reg) {
+			core_id = of_read_number(reg, addr_cells);
 			if (core_id  == 0 || (is_core_online(core_id))) {
 				val = spin_tbl_addr;
 				val += id_to_core(core_id) *
@@ -150,6 +161,7 @@ void append_mmu_masters(void *blob, const char *smmu_path,
  *      for all DPAA2 devices.
  *
  */
+#ifdef CONFIG_FSL_LSCH3
 static void fdt_fixup_smmu(void *blob)
 {
 	int nodeoffset;
@@ -165,6 +177,7 @@ static void fdt_fixup_smmu(void *blob)
 	fdt_fixup_smmu_pcie(blob);
 #endif
 }
+#endif
 
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
@@ -181,9 +194,11 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	ft_pci_setup(blob, bd);
 #endif
 
-#if defined(CONFIG_FSL_ESDHC)
+#ifdef CONFIG_FSL_ESDHC
 	fdt_fixup_esdhc(blob, bd);
 #endif
 
+#ifdef CONFIG_FSL_LSCH3
 	fdt_fixup_smmu(blob);
+#endif
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
new file mode 100644
index 0000000000..f7178d1470
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
+#endif
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+	int ret = 0;
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	ret |= serdes1_prtcl_map[device];
+#endif
+
+	return !!ret;
+}
+
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 cfg = gur_in32(&gur->rcwsr[4]);
+	int i;
+
+	switch (sd) {
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	case FSL_SRDS_1:
+		cfg &= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+		cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+		break;
+#endif
+	default:
+		printf("invalid SerDes%d\n", sd);
+		break;
+	}
+
+	/* Is serdes enabled at all? */
+	if (unlikely(cfg == 0))
+		return -ENODEV;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (serdes_get_prtcl(sd, cfg, i) == device)
+			return i;
+	}
+
+	return -ENODEV;
+}
+
+int get_serdes_protocol(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 cfg = gur_in32(&gur->rcwsr[4]) &
+			  FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	return cfg;
+}
+
+const char *serdes_clock_to_string(u32 clock)
+{
+	switch (clock) {
+	case SRDS_PLLCR0_RFCK_SEL_100:
+		return "100";
+	case SRDS_PLLCR0_RFCK_SEL_125:
+		return "125";
+	case SRDS_PLLCR0_RFCK_SEL_156_25:
+		return "156.25";
+	default:
+		return "100";
+	}
+}
+
+void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
+		 u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 cfg;
+	int lane;
+
+	memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
+
+	cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask;
+	cfg >>= sd_prctl_shift;
+	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
+
+	if (!is_serdes_prtcl_valid(sd, cfg))
+		printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
+
+	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+		enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
+
+		if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
+			debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
+		else
+			serdes_prtcl_map[lane_prtcl] = 1;
+	}
+}
+
+void fsl_serdes_init(void)
+{
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	serdes_init(FSL_SRDS_1,
+		    CONFIG_SYS_FSL_SERDES_ADDR,
+		    FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
+		    FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
+		    serdes1_prtcl_map);
+#endif
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
new file mode 100644
index 0000000000..6f6a588292
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/compiler.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/soc.h>
+#include <fsl_ifc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
+#define CONFIG_SYS_FSL_NUM_CC_PLLS      2
+#endif
+
+void get_sys_info(struct sys_info *sys_info)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+	u32 ccr;
+#endif
+#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
+	u32 rcw_tmp;
+#endif
+	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
+	unsigned int cpu;
+	const u8 core_cplx_pll[8] = {
+		[0] = 0,	/* CC1 PPL / 1 */
+		[1] = 0,	/* CC1 PPL / 2 */
+		[4] = 1,	/* CC2 PPL / 1 */
+		[5] = 1,	/* CC2 PPL / 2 */
+	};
+
+	const u8 core_cplx_pll_div[8] = {
+		[0] = 1,	/* CC1 PPL / 1 */
+		[1] = 2,	/* CC1 PPL / 2 */
+		[4] = 1,	/* CC2 PPL / 1 */
+		[5] = 2,	/* CC2 PPL / 2 */
+	};
+
+	uint i;
+	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
+	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
+	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+
+	sys_info->freq_systembus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#else
+	sys_info->freq_ddrbus = sysclk;
+#endif
+
+	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
+			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
+			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
+			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
+
+	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
+		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
+		if (ratio[i] > 4)
+			freq_c_pll[i] = sysclk * ratio[i];
+		else
+			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
+	}
+
+	for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) {
+		u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
+				& 0xf;
+		u32 cplx_pll = core_cplx_pll[c_pll_sel];
+
+		sys_info->freq_processor[cpu] =
+			freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+	}
+
+#define HWA_CGA_M1_CLK_SEL	0xe0000000
+#define HWA_CGA_M1_CLK_SHIFT	29
+#ifdef CONFIG_SYS_DPAA_FMAN
+	rcw_tmp = in_be32(&gur->rcwsr[7]);
+	switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
+	case 2:
+		sys_info->freq_fman[0] = freq_c_pll[0] / 2;
+		break;
+	case 3:
+		sys_info->freq_fman[0] = freq_c_pll[0] / 3;
+		break;
+	case 6:
+		sys_info->freq_fman[0] = freq_c_pll[1] / 2;
+		break;
+	case 7:
+		sys_info->freq_fman[0] = freq_c_pll[1] / 3;
+		break;
+	default:
+		printf("Error: Unknown FMan1 clock select!\n");
+		break;
+	}
+#endif
+
+#define HWA_CGA_M2_CLK_SEL	0x00000007
+#define HWA_CGA_M2_CLK_SHIFT	0
+#ifdef CONFIG_FSL_ESDHC
+	rcw_tmp = in_be32(&gur->rcwsr[15]);
+	rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
+	sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
+#endif
+
+#if defined(CONFIG_FSL_IFC)
+	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
+	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
+
+	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+#endif
+}
+
+int get_clocks(void)
+{
+	struct sys_info sys_info;
+
+	get_sys_info(&sys_info);
+	gd->cpu_clk = sys_info.freq_processor[0];
+	gd->bus_clk = sys_info.freq_systembus;
+	gd->mem_clk = sys_info.freq_ddrbus;
+
+#ifdef CONFIG_FSL_ESDHC
+	gd->arch.sdhc_clk = sys_info.freq_sdhc;
+#endif
+
+	if (gd->cpu_clk != 0)
+		return 0;
+	else
+		return 1;
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+	return gd->bus_clk;
+}
+
+ulong get_ddr_freq(ulong dummy)
+{
+	return gd->mem_clk;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int get_sdhc_freq(ulong dummy)
+{
+	return gd->arch.sdhc_clk;
+}
+#endif
+
+int get_serial_clock(void)
+{
+	return gd->bus_clk;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_I2C_CLK:
+		return get_bus_freq(0);
+#if defined(CONFIG_FSL_ESDHC)
+	case MXC_ESDHC_CLK:
+		return get_sdhc_freq(0);
+#endif
+	case MXC_DSPI_CLK:
+		return get_bus_freq(0);
+	case MXC_UART_CLK:
+		return get_bus_freq(0);
+	default:
+		printf("Unsupported clock\n");
+	}
+	return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index ae0834365e..2ab8da6403 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -8,7 +8,7 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <asm/arch/fsl_serdes.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <asm/arch/soc.h>
 #include <fsl-mc/ldpaa_wriop.h>
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
@@ -35,7 +35,7 @@ int is_serdes_configured(enum srds_prtcl device)
 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-	u32 cfg = in_le32(&gur->rcwsr[28]);
+	u32 cfg = gur_in32(&gur->rcwsr[28]);
 	int i;
 
 	switch (sd) {
@@ -76,7 +76,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 
 	memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
 
-	cfg = in_le32(&gur->rcwsr[28]) & sd_prctl_mask;
+	cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask;
 	cfg >>= sd_prctl_shift;
 	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index d9f137cc2d..4054c3c7d2 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014, Freescale Semiconductor, Inc.
+ * Copyright 2014-2015, Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
@@ -11,8 +11,8 @@
 #include <fsl_ifc.h>
 #include <asm/processor.h>
 #include <asm/io.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/soc.h>
 #include "cpu.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -83,15 +83,15 @@ void get_sys_info(struct sys_info *sys_info)
 	sys_info->freq_ddrbus2 = sysclk;
 #endif
 
-	sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
+	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
 			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
 	/* Platform clock is half of platform PLL */
 	sys_info->freq_systembus /= 2;
-	sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
+	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
 			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
-	sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >>
+	sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
 			FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
 
@@ -118,7 +118,7 @@ void get_sys_info(struct sys_info *sys_info)
 	}
 
 #if defined(CONFIG_FSL_IFC)
-	ccr = in_le32(&ifc_regs.gregs->ifc_ccr);
+	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
 	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
 
 	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 6b19d36f11..41e1704986 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2014 Freescale Semiconductor
+ * (C) Copyright 2014-2015 Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
@@ -10,11 +10,14 @@
 #include <linux/linkage.h>
 #include <asm/gic.h>
 #include <asm/macro.h>
-#include "mp.h"
+#ifdef CONFIG_MP
+#include <asm/arch/mp.h>
+#endif
 
 ENTRY(lowlevel_init)
 	mov	x29, lr			/* Save LR */
 
+#ifdef CONFIG_FSL_LSCH3
 	/* Add fully-coherent masters to DVM domain */
 	ldr	x0, =CCI_MN_BASE
 	ldr	x1, =CCI_MN_RNF_NODEID_LIST
@@ -81,6 +84,7 @@ ENTRY(lowlevel_init)
 	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(20)
 	ldr	x1, =0x00FF000C
 	bl	ccn504_set_qos
+#endif
 
 	/* Set the SMMU page size in the sACR register */
 	ldr	x1, =SMMU_BASE
@@ -106,10 +110,12 @@ ENTRY(lowlevel_init)
 
 	branch_if_master x0, x1, 2f
 
+#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
 	ldr	x0, =secondary_boot_func
 	blr	x0
-2:
+#endif
 
+2:
 #ifdef CONFIG_FSL_TZPC_BP147
 	/* Set Non Secure access for all devices protected via TZPC */
 	ldr	x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
@@ -245,6 +251,7 @@ ENTRY(__asm_flush_l3_cache)
 	ret
 ENDPROC(__asm_flush_l3_cache)
 
+#ifdef CONFIG_MP
 	/* Keep literals not used by the secondary boot code outside it */
 	.ltorg
 
@@ -353,3 +360,4 @@ __real_cntfrq:
 	/* Secondary Boot Code ends here */
 __secondary_boot_code_size:
 	.quad .-secondary_boot_code
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c
new file mode 100644
index 0000000000..e54d3899bb
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/immap_lsch2.h>
+
+struct serdes_config {
+	u32 protocol;
+	u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+	/* SerDes 1 */
+	{0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3} },
+	{0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
+	{0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3} },
+	{0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA1} },
+	{0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
+	{0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
+	{0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
+		  PCIE3} },
+	{0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
+	{0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA1} },
+	{0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
+	{0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA1} },
+	{0x7000, {PCIE1, PCIE1, PCIE1, PCIE1} },
+	{0x9998, {PCIE1, PCIE2, PCIE3, SATA1} },
+	{0x6058, {PCIE1, PCIE1, PCIE2, SATA1} },
+	{0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3} },
+	{0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3} },
+	{0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3} },
+	{0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
+		  SGMII_FM1_DTSEC6} },
+	{}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+	serdes1_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == cfg)
+			return ptr->lanes[lane];
+		ptr++;
+	}
+
+	return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+	int i;
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == prtcl)
+			break;
+		ptr++;
+	}
+
+	if (!ptr->protocol)
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (ptr->lanes[i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c
index 0b79a501d9..ea3114cca4 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c
@@ -1,12 +1,11 @@
 /*
- * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/arch/fsl_serdes.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
 
 struct serdes_config {
 	u8 protocol;
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index da7853a5af..0d600db090 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -7,9 +7,8 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/system.h>
-#include <asm/io.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
-#include "mp.h"
+#include <asm/arch/mp.h>
+#include <asm/arch/soc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -23,10 +22,14 @@ phys_addr_t determine_mp_bootpg(void)
 	return (phys_addr_t)&secondary_boot_code;
 }
 
-int fsl_lsch3_wake_seconday_cores(void)
+int fsl_layerscape_wake_seconday_cores(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_LSCH3
 	struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+#elif defined(CONFIG_FSL_LSCH2)
+	struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
+#endif
 	u32 cores, cpu_up_mask = 1;
 	int i, timeout = 10;
 	u64 *table = get_spin_tbl_addr();
@@ -48,13 +51,24 @@ int fsl_lsch3_wake_seconday_cores(void)
 			   (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
 
 	printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
-	out_le32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
-	out_le32(&gur->bootlocptrl, (u32)gd->relocaddr);
-	out_le32(&gur->scratchrw[6], 1);
+
+#ifdef CONFIG_FSL_LSCH3
+	gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
+	gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
+	gur_out32(&gur->scratchrw[6], 1);
 	asm volatile("dsb st" : : : "memory");
 	rst->brrl = cores;
 	asm volatile("dsb st" : : : "memory");
+#elif defined(CONFIG_FSL_LSCH2)
+	scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
+	scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
+	asm volatile("dsb st" : : : "memory");
+	gur_out32(&gur->brrl, cores);
+	asm volatile("dsb st" : : : "memory");
 
+	/* Bootup online cores */
+	scfg_out32(&scfg->corebcr, cores);
+#endif
 	/* This is needed as a precautionary measure.
 	 * If some code before this has accidentally  released the secondary
 	 * cores then the pre-bootloader code will trap them in a "wfe" unless
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 2538001bca..637853d51f 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -1,19 +1,18 @@
 /*
- * Copyright 2015 Freescale Semiconductor
+ * Copyright 2014-2015 Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
 #include <fsl_ifc.h>
-#include <nand.h>
-#include <spl.h>
-#include <asm/arch-fsl-lsch3/soc.h>
+#include <asm/arch/soc.h>
 #include <asm/io.h>
 #include <asm/global_data.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_LS2085A
 static void erratum_a008751(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008751
@@ -78,30 +77,27 @@ void fsl_lsch3_early_init_f(void)
 	erratum_a009203();
 }
 
-#ifdef CONFIG_SPL_BUILD
-void board_init_f(ulong dummy)
+#elif defined(CONFIG_LS1043A)
+void fsl_lsch2_early_init_f(void)
 {
-	/* Clear global data */
-	memset((void *)gd, 0, sizeof(gd_t));
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 
-	arch_cpu_init();
-	board_early_init_f();
-	timer_init();
-	env_init();
-	gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
-
-	serial_init();
-	console_init_f();
-	dram_init();
-
-	/* Clear the BSS. */
-	memset(__bss_start, 0, __bss_end - __bss_start);
+#ifdef CONFIG_FSL_IFC
+	init_early_memctl_regs();	/* tighten IFC timing */
+#endif
 
-	board_init_r(NULL, 0);
+	/*
+	 * Enable snoop requests and DVM message requests for
+	 * Slave insterface S4 (A53 core cluster)
+	 */
+	out_le32(&cci->slave[4].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 }
+#endif
 
-u32 spl_boot_device(void)
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
 {
-	return BOOT_DEVICE_NAND;
+	return 0;
 }
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
new file mode 100644
index 0000000000..ba551aaa6e
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <fsl_ifc.h>
+#include <fsl_csu.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SPL_MMC_SUPPORT
+	return BOOT_DEVICE_MMC1;
+#endif
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	return BOOT_DEVICE_NAND;
+#endif
+	return 0;
+}
+
+u32 spl_boot_mode(void)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+		return MMCSD_MODE_FAT;
+#else
+		return MMCSD_MODE_RAW;
+#endif
+	case BOOT_DEVICE_NAND:
+		return 0;
+	default:
+		puts("spl: error: unsupported device\n");
+		hang();
+	}
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+	/* Set global data pointer */
+	gd = &gdata;
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+#ifdef CONFIG_LS2085A
+	arch_cpu_init();
+#endif
+#ifdef CONFIG_FSL_IFC
+	init_early_memctl_regs();
+#endif
+	board_early_init_f();
+	timer_init();
+#ifdef CONFIG_LS2085A
+	env_init();
+#endif
+	get_clocks();
+
+	preloader_console_init();
+
+#ifdef CONFIG_SPL_I2C_SUPPORT
+	i2c_init_all();
+#endif
+	dram_init();
+
+	/* Clear the BSS */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+	board_init_r(NULL, 0);
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
deleted file mode 100644
index 9f7815bd52..0000000000
--- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright 2014, Freescale Semiconductor
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += cpu.o
-obj-y += lowlevel.o
-obj-y += soc.o
-obj-y += speed.o
-obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o ls2085a_serdes.o
-obj-$(CONFIG_MP) += mp.o
-obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.h b/arch/arm/cpu/armv8/fsl-lsch3/speed.h
deleted file mode 100644
index 15af5b9f91..0000000000
--- a/arch/arm/cpu/armv8/fsl-lsch3/speed.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Copyright 2014, Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-void get_sys_info(struct sys_info *sys_info);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ddc6a057d5..9542fff47d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
@@ -65,6 +69,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
 	zynq-zc770-xm011.dtb \
 	zynq-zc770-xm012.dtb \
 	zynq-zc770-xm013.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += \
+	zynqmp-ep108.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb
 
diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts
index d0a8621fda..690c747289 100644
--- a/arch/arm/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/dts/exynos5422-odroidxu3.dts
@@ -31,6 +31,18 @@
 			0xb0000000 0xea00000>;
 	};
 
+	adc@12D10000 {
+		u-boot,dm-pre-reloc;
+		status = "okay";
+	};
+
+	i2c@12CA0000 {
+		s2mps11_pmic@66 {
+			compatible = "samsung,s2mps11-pmic";
+			reg = <0x66>;
+		};
+	};
+
 	ehci@12110000 {
 		samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
 	};
diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
index bd3619d751..daa6a33c5b 100644
--- a/arch/arm/dts/exynos54xx.dtsi
+++ b/arch/arm/dts/exynos54xx.dtsi
@@ -42,6 +42,13 @@
 		xhci1 = "/xhci@12400000";
 	};
 
+	adc@12D10000 {
+		compatible = "samsung,exynos-adc-v2";
+		reg = <0x12D10000 0x100>;
+		interrupts = <0 106 0>;
+		status = "disabled";
+	};
+
 	i2c@12CA0000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts
index 1d7ff23c93..76826dc23b 100644
--- a/arch/arm/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/dts/exynos5800-peach-pi.dts
@@ -12,6 +12,7 @@
 
 / {
 	model = "Samsung/Google Peach Pi board based on Exynos5800";
+	cpu-model = "Exynos5800";
 
 	compatible = "google,pit-rev#", "google,pit",
 		"google,peach", "samsung,exynos5800", "samsung,exynos5";
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 546560979b..9eb5a2209c 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -89,7 +89,7 @@
 		#size-cells = <1>;
 		compatible = "n25q00";
 		reg = <0>;      /* chip select */
-		spi-max-frequency = <50000000>;
+		spi-max-frequency = <100000000>;
 		m25p,fast-read;
 		page-size = <256>;
 		block-size = <16>; /* 2^16, 64KB */
diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
index bd86f09326..ccadd817c0 100644
--- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
@@ -54,6 +54,14 @@
 	status = "okay";
 };
 
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
+
 /* for U-boot only */
 / {
 	soc {
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index a57f8ae335..a11b628f19 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -221,7 +221,7 @@
 			reg = <0x65c00000 0x100>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_usb1>;
-			interrupts = <0 135 4>;
+			interrupts = <0 137 4>;
 		};
 
 		pinctrl: pinctrl@5f801000 {
diff --git a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
index 912bc27bea..52dd1f96b0 100644
--- a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
+++ b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
@@ -44,6 +44,10 @@
 	status = "okay";
 };
 
+&usb1 {
+	status = "okay";
+};
+
 /* for U-boot only */
 / {
 	soc {
diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi
index a15c7b2161..6f19bf81dc 100644
--- a/arch/arm/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi
@@ -210,6 +210,24 @@
 			reg = <0x60001000 0x1000>,
 			      <0x60000100 0x100>;
 		};
+
+		usb0: usb@65a00000 {
+			compatible = "socionext,uniphier-xhci", "generic-xhci";
+			status = "disabled";
+			reg = <0x65a00000 0x100>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>;
+			interrupts = <0 134 4>;
+		};
+
+		usb1: usb@65c00000 {
+			compatible = "socionext,uniphier-xhci", "generic-xhci";
+			status = "disabled";
+			reg = <0x65c00000 0x100>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
+			interrupts = <0 137 4>;
+		};
 	};
 };
 
diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts
index 81d2385bf9..d0af8acd37 100644
--- a/arch/arm/dts/uniphier-proxstream2-gentil.dts
+++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts
@@ -42,6 +42,14 @@
 	status = "okay";
 };
 
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
+
 /* for U-boot only */
 / {
 	soc {
diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts
index fba7b742ca..92d74044c1 100644
--- a/arch/arm/dts/uniphier-proxstream2-vodka.dts
+++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts
@@ -42,6 +42,10 @@
 	status = "okay";
 };
 
+&usb0 {
+	status = "okay";
+};
+
 /* for U-boot only */
 / {
 	soc {
diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi
index 8b496a7210..cd0cf4e74b 100644
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/dts/uniphier-proxstream2.dtsi
@@ -235,6 +235,24 @@
 			reg = <0x60001000 0x1000>,
 			      <0x60000100 0x100>;
 		};
+
+		usb0: usb@65a00000 {
+			compatible = "socionext,uniphier-xhci", "generic-xhci";
+			status = "disabled";
+			reg = <0x65a00000 0x100>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
+			interrupts = <0 134 4>;
+		};
+
+		usb1: usb@65c00000 {
+			compatible = "socionext,uniphier-xhci", "generic-xhci";
+			status = "disabled";
+			reg = <0x65c00000 0x100>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
+			interrupts = <0 137 4>;
+		};
 	};
 };
 
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 84c15b5c79..83be51ae9d 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -54,6 +54,7 @@
 	};
 
 	amba: amba {
+		u-boot,dm-pre-reloc;
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts
index d5e0050893..e841a1d616 100644
--- a/arch/arm/dts/zynq-microzed.dts
+++ b/arch/arm/dts/zynq-microzed.dts
@@ -26,3 +26,8 @@
 &qspi {
 	status = "okay";
 };
+
+&uart1 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
diff --git a/arch/arm/dts/zynq-picozed.dts b/arch/arm/dts/zynq-picozed.dts
index 686b98fe7e..3408df8b8b 100644
--- a/arch/arm/dts/zynq-picozed.dts
+++ b/arch/arm/dts/zynq-picozed.dts
@@ -21,3 +21,8 @@
 		reg = <0 0x40000000>;
 	};
 };
+
+&uart1 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 4d8696021b..c41723641e 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -376,6 +376,7 @@
 };
 
 &uart1 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1_default>;
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index fc336ea5c9..5088cfee3e 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -297,6 +297,7 @@
 };
 
 &uart1 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1_default>;
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts
index cf56ac8d82..07e2b7a738 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -88,6 +88,7 @@
 };
 
 &uart1 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts
index f73c0ddcb8..77e3bb0e63 100644
--- a/arch/arm/dts/zynq-zc770-xm011.dts
+++ b/arch/arm/dts/zynq-zc770-xm011.dts
@@ -55,6 +55,7 @@
 };
 
 &uart1 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts
index 4289e31f46..3e1769acb5 100644
--- a/arch/arm/dts/zynq-zc770-xm012.dts
+++ b/arch/arm/dts/zynq-zc770-xm012.dts
@@ -62,5 +62,6 @@
 };
 
 &uart1 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 };
diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts
index 5124cdc5cd..288e248374 100644
--- a/arch/arm/dts/zynq-zc770-xm013.dts
+++ b/arch/arm/dts/zynq-zc770-xm013.dts
@@ -75,5 +75,6 @@
 };
 
 &uart0 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 };
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index 363049085f..51d67d93f2 100644
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -54,6 +54,7 @@
 };
 
 &uart1 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts
index 10f7815524..dcfc00e096 100644
--- a/arch/arm/dts/zynq-zybo.dts
+++ b/arch/arm/dts/zynq-zybo.dts
@@ -49,5 +49,6 @@
 };
 
 &uart1 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 };
diff --git a/arch/arm/dts/zynqmp-ep108-clk.dtsi b/arch/arm/dts/zynqmp-ep108-clk.dtsi
new file mode 100644
index 0000000000..f864526553
--- /dev/null
+++ b/arch/arm/dts/zynqmp-ep108-clk.dtsi
@@ -0,0 +1,119 @@
+/*
+ * clock specification for Xilinx ZynqMP ep108 development board
+ *
+ * (C) Copyright 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+&amba {
+	misc_clk: misc_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
+
+	i2c_clk: i2c_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0x0>;
+		clock-frequency = <111111111>;
+	};
+
+	sata_clk: sata_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <75000000>;
+	};
+
+	dp_aclk: clock0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <50000000>;
+		clock-accuracy = <100>;
+	};
+
+	dp_aud_clk: clock1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <22579200>;
+		clock-accuracy = <100>;
+	};
+};
+
+&can0 {
+	clocks = <&misc_clk &misc_clk>;
+};
+
+&gem0 {
+	clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
+};
+
+&gpio {
+	clocks = <&misc_clk>;
+};
+
+&i2c0 {
+	clocks = <&i2c_clk>;
+};
+
+&i2c1 {
+	clocks = <&i2c_clk>;
+};
+
+&qspi {
+	clocks = <&misc_clk &misc_clk>;
+};
+
+&sata {
+	clocks = <&sata_clk>;
+};
+
+&sdhci0 {
+	clocks = <&misc_clk>, <&misc_clk>;
+};
+
+&sdhci1 {
+	clocks = <&misc_clk>, <&misc_clk>;
+};
+
+&spi0 {
+	clocks = <&misc_clk &misc_clk>;
+};
+
+&spi1 {
+	clocks = <&misc_clk &misc_clk>;
+};
+
+&uart0 {
+	clocks = <&misc_clk &misc_clk>;
+};
+
+&usb0 {
+	clocks = <&misc_clk>, <&misc_clk>;
+};
+
+&usb1 {
+	clocks = <&misc_clk>, <&misc_clk>;
+};
+
+&watchdog0 {
+	clocks= <&misc_clk>;
+};
+
+&xilinx_drm {
+	clocks = <&misc_clk>;
+};
+
+&xlnx_dp {
+	clocks = <&dp_aclk>, <&dp_aud_clk>;
+};
+
+&xlnx_dp_snd_codec0 {
+	clocks = <&dp_aud_clk>;
+};
+
+&xlnx_dpdma {
+	clocks = <&misc_clk>;
+};
diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts
new file mode 100644
index 0000000000..4481bd07c9
--- /dev/null
+++ b/arch/arm/dts/zynqmp-ep108.dts
@@ -0,0 +1,174 @@
+/*
+ * dts file for Xilinx ZynqMP ep108 development board
+ *
+ * (C) Copyright 2014 - 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+/include/ "zynqmp.dtsi"
+/include/ "zynqmp-ep108-clk.dtsi"
+
+/ {
+	model = "ZynqMP EP108";
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &qspi;
+		spi1 = &spi0;
+		spi2 = &spi1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x40000000>;
+	};
+};
+
+&can0 {
+	status = "okay";
+};
+
+&gem0 {
+	status = "okay";
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	phy0: phy@0{
+		reg = <0>;
+		max-speed = <100>;
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+	eeprom@54 {
+		compatible = "at,24c64";
+		reg = <0x54>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <400000>;
+	eeprom@55 {
+		compatible = "at,24c64";
+		reg = <0x55>;
+	};
+};
+
+&qspi {
+	status = "okay";
+	flash@0 {
+		compatible = "n25q512a11";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <10000000>;
+		partition@qspi-fsbl-uboot { /* for testing purpose */
+			label = "qspi-fsbl-uboot";
+			reg = <0x0 0x100000>;
+		};
+		partition@qspi-linux { /* for testing purpose */
+			label = "qspi-linux";
+			reg = <0x100000 0x500000>;
+		};
+		partition@qspi-device-tree { /* for testing purpose */
+			label = "qspi-device-tree";
+			reg = <0x600000 0x20000>;
+		};
+		partition@qspi-rootfs { /* for testing purpose */
+			label = "qspi-rootfs";
+			reg = <0x620000 0x5E0000>;
+		};
+	};
+};
+
+&sata {
+	status = "okay";
+	ceva,broken-gen2;
+};
+
+&sdhci0 {
+	status = "okay";
+};
+
+&sdhci1 {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+	num-cs = <1>;
+	spi0_flash0: spi0_flash0@0 {
+		compatible = "m25p80";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <50000000>;
+		reg = <0>;
+
+		spi0_flash0@00000000 {
+			label = "spi0_flash0";
+			reg = <0x0 0x100000>;
+		};
+	};
+};
+
+&spi1 {
+	status = "okay";
+	num-cs = <1>;
+	spi1_flash0: spi1_flash0@0 {
+		compatible = "m25p80";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <50000000>;
+		reg = <0>;
+
+		spi1_flash0@00000000 {
+			label = "spi1_flash0";
+			reg = <0x0 0x100000>;
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "peripheral";
+	maximum-speed = "high-speed";
+};
+
+&usb1 {
+	status = "okay";
+	dr_mode = "host";
+	maximum-speed = "high-speed";
+};
+
+&watchdog0 {
+	status = "okay";
+};
+
+&xlnx_dp {
+	xlnx,max-pclock-frequency = <200000>;
+};
+
+&xlnx_dpdma {
+	xlnx,axi-clock-freq = <200000000>;
+};
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
new file mode 100644
index 0000000000..24a34e6d85
--- /dev/null
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -0,0 +1,668 @@
+/*
+ * dts file for Xilinx ZynqMP
+ *
+ * (C) Copyright 2014 - 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/ {
+	compatible = "xlnx,zynqmp";
+	#address-cells = <2>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x0>;
+		};
+
+		cpu@1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x1>;
+		};
+
+		cpu@2 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x2>;
+		};
+
+		cpu@3 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x3>;
+		};
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <0 143 4>,
+			     <0 144 4>,
+			     <0 145 4>,
+			     <0 146 4>;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	firmware {
+		compatible = "xlnx,zynqmp-pm";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <1 13 0xf01>,
+			     <1 14 0xf01>,
+			     <1 11 0xf01>,
+			     <1 10 0xf01>;
+	};
+
+	amba_apu: amba_apu {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		gic: interrupt-controller@f9010000 {
+			compatible = "arm,gic-400", "arm,cortex-a15-gic";
+			#interrupt-cells = <3>;
+			reg = <0x0 0xf9010000 0x10000>,
+			      <0x0 0xf902f000 0x2000>,
+			      <0x0 0xf9040000 0x20000>,
+			      <0x0 0xf906f000 0x2000>;
+			interrupt-controller;
+			interrupt-parent = <&gic>;
+			interrupts = <1 9 0xf04>;
+		};
+	};
+
+	amba: amba {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		can0: can@ff060000 {
+			compatible = "xlnx,zynq-can-1.0";
+			status = "disabled";
+			clock-names = "can_clk", "pclk";
+			reg = <0x0 0xff060000 0x1000>;
+			interrupts = <0 23 4>;
+			interrupt-parent = <&gic>;
+			tx-fifo-depth = <0x40>;
+			rx-fifo-depth = <0x40>;
+		};
+
+		can1: can@ff070000 {
+			compatible = "xlnx,zynq-can-1.0";
+			status = "disabled";
+			clock-names = "can_clk", "pclk";
+			reg = <0x0 0xff070000 0x1000>;
+			interrupts = <0 24 4>;
+			interrupt-parent = <&gic>;
+			tx-fifo-depth = <0x40>;
+			rx-fifo-depth = <0x40>;
+		};
+
+		/* GDMA */
+		fpd_dma_chan1: dma@fd500000 {
+			status = "disabled";
+			compatible = "xlnx,zynqmp-dma-1.0";
+			reg = <0x0 0xfd500000 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 124 4>;
+			xlnx,id = <0>;
+			xlnx,bus-width = <128>;
+		};
+
+		fpd_dma_chan2: dma@fd510000 {
+			status = "disabled";
+			compatible = "xlnx,zynqmp-dma-1.0";
+			reg = <0x0 0xfd510000 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 125 4>;
+			xlnx,id = <1>;
+			xlnx,bus-width = <128>;
+		};
+
+		fpd_dma_chan3: dma@fd520000 {
+			status = "disabled";
+			compatible = "xlnx,zynqmp-dma-1.0";
+			reg = <0x0 0xfd520000 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 126 4>;
+			xlnx,id = <2>;
+			xlnx,bus-width = <128>;
+		};
+
+		fpd_dma_chan4: dma@fd530000 {
+			status = "disabled";
+			compatible = "xlnx,zynqmp-dma-1.0";
+			reg = <0x0 0xfd530000 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 127 4>;
+			xlnx,id = <3>;
+			xlnx,bus-width = <128>;
+		};
+
+		fpd_dma_chan5: dma@fd540000 {
+			status = "disabled";
+			compatible = "xlnx,zynqmp-dma-1.0";
+			reg = <0x0 0xfd540000 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 128 4>;
+			xlnx,id = <4>;
+			xlnx,bus-width = <128>;
+		};
+
+		fpd_dma_chan6: dma@fd550000 {
+			status = "disabled";
+			compatible = "xlnx,zynqmp-dma-1.0";
+			reg = <0x0 0xfd550000 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 129 4>;
+			xlnx,id = <5>;
+			xlnx,bus-width = <128>;
+		};
+
+		fpd_dma_chan7: dma@fd560000 {
+			status = "disabled";
+			compatible = "xlnx,zynqmp-dma-1.0";
+			reg = <0x0 0xfd560000 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 130 4>;
+			xlnx,id = <6>;
+			xlnx,bus-width = <128>;
+		};
+
+		fpd_dma_chan8: dma@fd570000 {
+			status = "disabled";
+			compatible = "xlnx,zynqmp-dma-1.0";
+			reg = <0x0 0xfd570000 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 131 4>;
+			xlnx,id = <7>;
+			xlnx,bus-width = <128>;
+		};
+
+		gpu: gpu@fd4b0000 {
+			status = "disabled";
+			compatible = "arm,mali-400", "arm,mali-utgard";
+			reg = <0x0 0xfd4b0000 0x30000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
+			interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
+		};
+
+		/* ADMA */
+		lpd_dma_chan1: dma@ffa80000 {
+			status = "disabled";
+			compatible = "xlnx,zynqmp-dma-1.0";
+			reg = <0x0 0xffa80000 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 77 4>;
+			xlnx,id = <0>;
+			xlnx,bus-width = <64>;
+		};
+
+		lpd_dma_chan2: dma@ffa90000 {
+			status = "disabled";
+			compatible = "xlnx,zynqmp-dma-1.0";
+			reg = <0x0 0xffa90000 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 78 4>;
+			xlnx,id = <1>;
+			xlnx,bus-width = <64>;
+		};
+
+		lpd_dma_chan3: dma@ffaa0000 {
+			status = "disabled";
+			compatible = "xlnx,zynqmp-dma-1.0";
+			reg = <0x0 0xffaa0000 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 79 4>;
+			xlnx,id = <2>;
+			xlnx,bus-width = <64>;
+		};
+
+		lpd_dma_chan4: dma@ffab0000 {
+			status = "disabled";
+			compatible = "xlnx,zynqmp-dma-1.0";
+			reg = <0x0 0xffab0000 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 80 4>;
+			xlnx,id = <3>;
+			xlnx,bus-width = <64>;
+		};
+
+		lpd_dma_chan5: dma@ffac0000 {
+			status = "disabled";
+			compatible = "xlnx,zynqmp-dma-1.0";
+			reg = <0x0 0xffac0000 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 81 4>;
+			xlnx,id = <4>;
+			xlnx,bus-width = <64>;
+		};
+
+		lpd_dma_chan6: dma@ffad0000 {
+			status = "disabled";
+			compatible = "xlnx,zynqmp-dma-1.0";
+			reg = <0x0 0xffad0000 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 82 4>;
+			xlnx,id = <5>;
+			xlnx,bus-width = <64>;
+		};
+
+		lpd_dma_chan7: dma@ffae0000 {
+			status = "disabled";
+			compatible = "xlnx,zynqmp-dma-1.0";
+			reg = <0x0 0xffae0000 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 83 4>;
+			xlnx,id = <6>;
+			xlnx,bus-width = <64>;
+		};
+
+		lpd_dma_chan8: dma@ffaf0000 {
+			status = "disabled";
+			compatible = "xlnx,zynqmp-dma-1.0";
+			reg = <0x0 0xffaf0000 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 84 4>;
+			xlnx,id = <7>;
+			xlnx,bus-width = <64>;
+		};
+
+		nand0: nand@ff100000 {
+			compatible = "arasan,nfc-v3p10";
+			status = "disabled";
+			reg = <0x0 0xff100000 0x1000>;
+			clock-names = "clk_sys", "clk_flash";
+			interrupt-parent = <&gic>;
+			interrupts = <0 14 4>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+		};
+
+		gem0: ethernet@ff0b0000 {
+			compatible = "cdns,gem";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 57 4>, <0 57 4>;
+			reg = <0x0 0xff0b0000 0x1000>;
+			clock-names = "pclk", "hclk", "tx_clk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			jumbo-max-len = <10240>;
+			jumbo-supported;
+		};
+
+		gem1: ethernet@ff0c0000 {
+			compatible = "cdns,gem";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 59 4>, <0 59 4>;
+			reg = <0x0 0xff0c0000 0x1000>;
+			clock-names = "pclk", "hclk", "tx_clk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			jumbo-max-len = <10240>;
+			jumbo-supported;
+		};
+
+		gem2: ethernet@ff0d0000 {
+			compatible = "cdns,gem";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 61 4>, <0 61 4>;
+			reg = <0x0 0xff0d0000 0x1000>;
+			clock-names = "pclk", "hclk", "tx_clk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			jumbo-max-len = <10240>;
+			jumbo-supported;
+		};
+
+		gem3: ethernet@ff0e0000 {
+			compatible = "cdns,gem";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 63 4>, <0 63 4>;
+			reg = <0x0 0xff0e0000 0x1000>;
+			clock-names = "pclk", "hclk", "tx_clk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			jumbo-max-len = <10240>;
+			jumbo-supported;
+		};
+
+		gpio: gpio@ff0a0000 {
+			compatible = "xlnx,zynqmp-gpio-1.0";
+			status = "disabled";
+			#gpio-cells = <0x2>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 16 4>;
+			reg = <0x0 0xff0a0000 0x1000>;
+		};
+
+		i2c0: i2c@ff020000 {
+			compatible = "cdns,i2c-r1p10";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 17 4>;
+			reg = <0x0 0xff020000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@ff030000 {
+			compatible = "cdns,i2c-r1p10";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 18 4>;
+			reg = <0x0 0xff030000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		pcie: pcie@fd0e0000 {
+			compatible = "xlnx,nwl-pcie-2.11";
+			status = "disabled";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			device_type = "pci";
+			interrupt-parent = <&gic>;
+			interrupts = < 0 118 4>,
+				     < 0 116 4>,
+				     < 0 115 4>,	/* MSI_1 [63...32] */
+				     < 0 114 4 >;	/* MSI_0 [31...0] */
+			interrupt-names = "misc", "intx", "msi_1", "msi_0";
+			reg = <0x0 0xfd0e0000 0x1000>,
+			      <0x0 0xfd480000 0x1000>,
+			      <0x0 0xe0000000 0x1000000>;
+			reg-names = "breg", "pcireg", "cfg";
+			ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
+		};
+
+		qspi: spi@ff0f0000 {
+			compatible = "xlnx,zynqmp-qspi-1.0";
+			status = "disabled";
+			clock-names = "ref_clk", "pclk";
+			interrupts = <0 15 4>;
+			interrupt-parent = <&gic>;
+			num-cs = <1>;
+			reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		rtc: rtc@ffa60000 {
+			compatible = "xlnx,zynqmp-rtc";
+			status = "disabled";
+			reg = <0x0 0xffa60000 0x100>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 26 4>, <0 27 4>;
+			interrupt-names = "alarm", "sec";
+		};
+
+		sata: ahci@fd0c0000 {
+			compatible = "ceva,ahci-1v84";
+			status = "disabled";
+			reg = <0x0 0xfd0c0000 0x2000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 133 4>;
+		};
+
+		sdhci0: sdhci@ff160000 {
+			compatible = "arasan,sdhci-8.9a";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 48 4>;
+			reg = <0x0 0xff160000 0x1000>;
+			clock-names = "clk_xin", "clk_ahb";
+		};
+
+		sdhci1: sdhci@ff170000 {
+			compatible = "arasan,sdhci-8.9a";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 49 4>;
+			reg = <0x0 0xff170000 0x1000>;
+			clock-names = "clk_xin", "clk_ahb";
+		};
+
+		smmu: smmu@fd800000 {
+			compatible = "arm,mmu-500";
+			reg = <0x0 0xfd800000 0x20000>;
+			#global-interrupts = <1>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 157 4>,
+				<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
+				<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
+				<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
+				<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>;
+		};
+
+		spi0: spi@ff040000 {
+			compatible = "cdns,spi-r1p6";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 19 4>;
+			reg = <0x0 0xff040000 0x1000>;
+			clock-names = "ref_clk", "pclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi@ff050000 {
+			compatible = "cdns,spi-r1p6";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 20 4>;
+			reg = <0x0 0xff050000 0x1000>;
+			clock-names = "ref_clk", "pclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		ttc0: timer@ff110000 {
+			compatible = "cdns,ttc";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
+			reg = <0x0 0xff110000 0x1000>;
+			timer-width = <32>;
+		};
+
+		ttc1: timer@ff120000 {
+			compatible = "cdns,ttc";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
+			reg = <0x0 0xff120000 0x1000>;
+			timer-width = <32>;
+		};
+
+		ttc2: timer@ff130000 {
+			compatible = "cdns,ttc";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
+			reg = <0x0 0xff130000 0x1000>;
+			timer-width = <32>;
+		};
+
+		ttc3: timer@ff140000 {
+			compatible = "cdns,ttc";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
+			reg = <0x0 0xff140000 0x1000>;
+			timer-width = <32>;
+		};
+
+		uart0: serial@ff000000 {
+			compatible = "cdns,uart-r1p8";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 21 4>;
+			reg = <0x0 0xff000000 0x1000>;
+			clock-names = "uart_clk", "pclk";
+		};
+
+		uart1: serial@ff010000 {
+			compatible = "cdns,uart-r1p8";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 22 4>;
+			reg = <0x0 0xff010000 0x1000>;
+			clock-names = "uart_clk", "pclk";
+		};
+
+		usb0: usb@fe200000 {
+			compatible = "snps,dwc3";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 65 4>;
+			reg = <0x0 0xfe200000 0x40000>;
+			clock-names = "clk_xin", "clk_ahb";
+		};
+
+		usb1: usb@fe300000 {
+			compatible = "snps,dwc3";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 70 4>;
+			reg = <0x0 0xfe300000 0x40000>;
+			clock-names = "clk_xin", "clk_ahb";
+		};
+
+		watchdog0: watchdog@fd4d0000 {
+			compatible = "cdns,wdt-r1p2";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 52 1>;
+			reg = <0x0 0xfd4d0000 0x1000>;
+			timeout-sec = <10>;
+		};
+
+		xilinx_drm: xilinx_drm {
+			compatible = "xlnx,drm";
+			status = "disabled";
+			xlnx,encoder-slave = <&xlnx_dp>;
+			xlnx,connector-type = "DisplayPort";
+			xlnx,dp-sub = <&xlnx_dp_sub>;
+			planes {
+				xlnx,pixel-format = "rgb565";
+				plane0 {
+					dmas = <&xlnx_dpdma 3>;
+					dma-names = "dma";
+				};
+				plane1 {
+					dmas = <&xlnx_dpdma 0>;
+					dma-names = "dma";
+				};
+			};
+		};
+
+		xlnx_dp: dp@43c00000 {
+			compatible = "xlnx,v-dp";
+			status = "disabled";
+			reg = <0x0 0xfd4a0000 0x1000>;
+			interrupts = <0 119 4>;
+			interrupt-parent = <&gic>;
+			clock-names = "aclk", "aud_clk";
+			xlnx,dp-version = "v1.2";
+			xlnx,max-lanes = <2>;
+			xlnx,max-link-rate = <540000>;
+			xlnx,max-bpc = <16>;
+			xlnx,enable-ycrcb;
+			xlnx,colormetry = "rgb";
+			xlnx,bpc = <8>;
+			xlnx,audio-chan = <2>;
+			xlnx,dp-sub = <&xlnx_dp_sub>;
+		};
+
+		xlnx_dp_snd_card: dp_snd_card {
+			compatible = "xlnx,dp-snd-card";
+			status = "disabled";
+			xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
+			xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
+		};
+
+		xlnx_dp_snd_codec0: dp_snd_codec0 {
+			compatible = "xlnx,dp-snd-codec";
+			status = "disabled";
+			clock-names = "aud_clk";
+		};
+
+		xlnx_dp_snd_pcm0: dp_snd_pcm0 {
+			compatible = "xlnx,dp-snd-pcm";
+			status = "disabled";
+			dmas = <&xlnx_dpdma 4>;
+			dma-names = "tx";
+		};
+
+		xlnx_dp_snd_pcm1: dp_snd_pcm1 {
+			compatible = "xlnx,dp-snd-pcm";
+			status = "disabled";
+			dmas = <&xlnx_dpdma 5>;
+			dma-names = "tx";
+		};
+
+		xlnx_dp_sub: dp_sub@43c0a000 {
+			compatible = "xlnx,dp-sub";
+			status = "disabled";
+			reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>;
+			reg-names = "blend", "av_buf", "aud";
+			xlnx,output-fmt = "rgb";
+		};
+
+		xlnx_dpdma: dma@fd4c0000 {
+			compatible = "xlnx,dpdma";
+			status = "disabled";
+			reg = <0x0 0xfd4c0000 0x1000>;
+			interrupts = <0 122 4>;
+			interrupt-parent = <&gic>;
+			clock-names = "axi_clk";
+			dma-channels = <6>;
+			#dma-cells = <1>;
+			dma-video0channel@43c10000 {
+				compatible = "xlnx,video0";
+			};
+			dma-video1channel@43c10000 {
+				compatible = "xlnx,video1";
+			};
+			dma-video2channel@43c10000 {
+				compatible = "xlnx,video2";
+			};
+			dma-graphicschannel@43c10000 {
+				compatible = "xlnx,graphics";
+			};
+			dma-audio0channel@43c10000 {
+				compatible = "xlnx,audio0";
+			};
+			dma-audio1channel@43c10000 {
+				compatible = "xlnx,audio1";
+			};
+		};
+	};
+};
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
index 62bc53c2fe..69359135d5 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/clock.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
@@ -1,12 +1,12 @@
 /*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
  */
 
-#ifndef __ASM_ARCH_FSL_LSCH3_CLOCK_H_
-#define __ASM_ARCH_FSL_LSCH3_CLOCK_H_
+#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
+#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
 
 #include <common.h>
 
@@ -21,4 +21,4 @@ enum mxc_clock {
 
 unsigned int mxc_get_clock(enum mxc_clock clk);
 
-#endif /* __ASM_ARCH_FSL_LSCH3_CLOCK_H_ */
+#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
new file mode 100644
index 0000000000..87bb937582
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
+
+#include <fsl_ddrc_version.h>
+
+#ifdef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDRC_GEN4
+#else
+#define CONFIG_SYS_FSL_DDRC_ARM_GEN3	/* Enable Freescale ARM DDR3 driver */
+#endif
+#define CONFIG_SYS_FSL_DDR		/* Freescale DDR driver */
+#define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
+
+#if defined(CONFIG_LS2085A)
+#define CONFIG_MAX_CPUS				16
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
+#define CONFIG_NUM_DDR_CONTROLLERS		3
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
+#define	SRDS_MAX_LANES	8
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
+#define CONFIG_SYS_PAGE_SIZE		0x10000
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#ifndef L1_CACHE_BYTES
+#define L1_CACHE_SHIFT		6
+#define L1_CACHE_BYTES		BIT(L1_CACHE_SHIFT)
+#endif
+
+#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000	/* initial RAM */
+#define CONFIG_SYS_FSL_OCRAM_SIZE	0x00200000	/* 2M */
+
+/* DDR */
+#define CONFIG_SYS_FSL_DDR_LE
+#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define CONFIG_SYS_FSL_ESDHC_LE
+#define CONFIG_SYS_FSL_IFC_LE
+
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE			0x06000000
+#define GICR_BASE			0x06100000
+
+/* SMMU Defintions */
+#define SMMU_BASE			0x05000000 /* GR0 Base */
+
+/* Cache Coherent Interconnect */
+#define CCI_MN_BASE			0x04000000
+#define CCI_MN_RNF_NODEID_LIST		0x180
+#define CCI_MN_DVM_DOMAIN_CTL		0x200
+#define CCI_MN_DVM_DOMAIN_CTL_SET	0x210
+
+#define CCI_RN_I_0_BASE			(CCI_MN_BASE + 0x800000)
+#define CCI_RN_I_2_BASE			(CCI_MN_BASE + 0x820000)
+#define CCI_RN_I_6_BASE			(CCI_MN_BASE + 0x860000)
+#define CCI_RN_I_12_BASE		(CCI_MN_BASE + 0x8C0000)
+#define CCI_RN_I_16_BASE		(CCI_MN_BASE + 0x900000)
+#define CCI_RN_I_20_BASE		(CCI_MN_BASE + 0x940000)
+
+#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
+#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
+#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
+
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE				0x02200000
+#define TZPCR0SIZE_BASE				(TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE			(TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE			(TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE			(TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE			(TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE			(TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE			(TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE			(TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE			(TZPC_BASE + 0x820)
+
+#define CONFIG_SYS_FSL_ERRATUM_A008336
+#define CONFIG_SYS_FSL_ERRATUM_A008511
+#define CONFIG_SYS_FSL_ERRATUM_A008514
+#define CONFIG_SYS_FSL_ERRATUM_A008585
+#define CONFIG_SYS_FSL_ERRATUM_A008751
+#elif defined(CONFIG_LS1043A)
+#define CONFIG_MAX_CPUS				4
+#define CONFIG_SYS_CACHELINE_SIZE		64
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_NUM_FMAN			1
+#define CONFIG_SYS_NUM_FM1_DTSEC		7
+#define CONFIG_SYS_NUM_FM1_10GEC		1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT		4
+#define CONFIG_NUM_DDR_CONTROLLERS		1
+#define CONFIG_SYS_CCSRBAR_DEFAULT		0x01000000
+#define CONFIG_SYS_FSL_SEC_COMPAT		5
+#define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
+#define CONFIG_SYS_FSL_OCRAM_SIZE		0x200000 /* 2 MiB */
+#define CONFIG_SYS_FSL_DDR_BE
+#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_BE
+#define CONFIG_SYS_FSL_CCSR_SCFG_BE
+#define CONFIG_SYS_FSL_IFC_BE
+#define CONFIG_SYS_FSL_ESDHC_BE
+#define CONFIG_SYS_FSL_WDOG_BE
+#define CONFIG_SYS_FSL_DSPI_BE
+#define CONFIG_SYS_FSL_QSPI_BE
+
+#define QE_MURAM_SIZE		0x6000UL
+#define MAX_QE_RISC		1
+#define QE_NUM_OF_SNUM		28
+
+#define SRDS_MAX_LANES		4
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_PCIE_COMPAT		"fsl,qoriq-pcie-v2.4"
+
+#define CONFIG_SYS_FSL_SFP_VER_3_2
+#define CONFIG_SYS_FSL_SNVS_LE
+#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SRK_LE
+#define CONFIG_KEY_REVOCATION
+
+/* SMMU Defintions */
+#define SMMU_BASE		0x09000000
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE		0x01401000
+#define GICC_BASE		0x01402000
+
+#else
+#error SoC not defined
+#endif
+
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
new file mode 100644
index 0000000000..29039963f1
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -0,0 +1,229 @@
+/*
+ * Copyright 2014-2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _FSL_LAYERSCAPE_CPU_H
+#define _FSL_LAYERSCAPE_CPU_H
+
+static struct cpu_type cpu_type_list[] = {
+	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
+	CPU_TYPE_ENTRY(LS2080, LS2080, 8),
+	CPU_TYPE_ENTRY(LS2045, LS2045, 4),
+	CPU_TYPE_ENTRY(LS1043, LS1043, 4),
+};
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#define SECTION_SHIFT_L0		39UL
+#define SECTION_SHIFT_L1		30UL
+#define SECTION_SHIFT_L2		21UL
+#define BLOCK_SIZE_L0			0x8000000000
+#define BLOCK_SIZE_L1			0x40000000
+#define BLOCK_SIZE_L2			0x200000
+#define NUM_OF_ENTRY			512
+#define TCR_EL2_PS_40BIT		(2 << 16)
+
+#define LAYERSCAPE_VA_BITS		(40)
+#define LAYERSCAPE_TCR		(TCR_TG0_4K		| \
+				TCR_EL2_PS_40BIT	| \
+				TCR_SHARED_NON		| \
+				TCR_ORGN_NC		| \
+				TCR_IRGN_NC		| \
+				TCR_T0SZ(LAYERSCAPE_VA_BITS))
+#define LAYERSCAPE_TCR_FINAL	(TCR_TG0_4K		| \
+				TCR_EL2_PS_40BIT	| \
+				TCR_SHARED_OUTER	| \
+				TCR_ORGN_WBWA		| \
+				TCR_IRGN_WBWA		| \
+				TCR_T0SZ(LAYERSCAPE_VA_BITS))
+
+#ifdef CONFIG_FSL_LSCH3
+#define CONFIG_SYS_FSL_CCSR_BASE	0x00000000
+#define CONFIG_SYS_FSL_CCSR_SIZE	0x10000000
+#define CONFIG_SYS_FSL_QSPI_BASE1	0x20000000
+#define CONFIG_SYS_FSL_QSPI_SIZE1	0x10000000
+#define CONFIG_SYS_FSL_IFC_BASE1	0x30000000
+#define CONFIG_SYS_FSL_IFC_SIZE1	0x10000000
+#define CONFIG_SYS_FSL_IFC_SIZE1_1	0x400000
+#define CONFIG_SYS_FSL_DRAM_BASE1	0x80000000
+#define CONFIG_SYS_FSL_DRAM_SIZE1	0x80000000
+#define CONFIG_SYS_FSL_QSPI_BASE2	0x400000000
+#define CONFIG_SYS_FSL_QSPI_SIZE2	0x100000000
+#define CONFIG_SYS_FSL_IFC_BASE2	0x500000000
+#define CONFIG_SYS_FSL_IFC_SIZE2	0x100000000
+#define CONFIG_SYS_FSL_DCSR_BASE	0x700000000
+#define CONFIG_SYS_FSL_DCSR_SIZE	0x40000000
+#define CONFIG_SYS_FSL_MC_BASE		0x80c000000
+#define CONFIG_SYS_FSL_MC_SIZE		0x4000000
+#define CONFIG_SYS_FSL_NI_BASE		0x810000000
+#define CONFIG_SYS_FSL_NI_SIZE		0x8000000
+#define CONFIG_SYS_FSL_QBMAN_BASE	0x818000000
+#define CONFIG_SYS_FSL_QBMAN_SIZE	0x8000000
+#define CONFIG_SYS_FSL_QBMAN_SIZE_1	0x4000000
+#define CONFIG_SYS_PCIE1_PHYS_SIZE	0x200000000
+#define CONFIG_SYS_PCIE2_PHYS_SIZE	0x200000000
+#define CONFIG_SYS_PCIE3_PHYS_SIZE	0x200000000
+#define CONFIG_SYS_PCIE4_PHYS_SIZE	0x200000000
+#define CONFIG_SYS_FSL_WRIOP1_BASE	0x4300000000
+#define CONFIG_SYS_FSL_WRIOP1_SIZE	0x100000000
+#define CONFIG_SYS_FSL_AIOP1_BASE	0x4b00000000
+#define CONFIG_SYS_FSL_AIOP1_SIZE	0x100000000
+#define CONFIG_SYS_FSL_PEBUF_BASE	0x4c00000000
+#define CONFIG_SYS_FSL_PEBUF_SIZE	0x400000000
+#define CONFIG_SYS_FSL_DRAM_BASE2	0x8080000000
+#define CONFIG_SYS_FSL_DRAM_SIZE2	0x7F80000000
+#elif defined(CONFIG_FSL_LSCH2)
+#define CONFIG_SYS_FSL_BOOTROM_BASE	0x0
+#define CONFIG_SYS_FSL_BOOTROM_SIZE	0x1000000
+#define CONFIG_SYS_FSL_CCSR_BASE	0x1000000
+#define CONFIG_SYS_FSL_CCSR_SIZE	0xf000000
+#define CONFIG_SYS_FSL_DCSR_BASE	0x20000000
+#define CONFIG_SYS_FSL_DCSR_SIZE	0x4000000
+#define CONFIG_SYS_FSL_QSPI_BASE	0x40000000
+#define CONFIG_SYS_FSL_QSPI_SIZE	0x20000000
+#define CONFIG_SYS_FSL_IFC_BASE		0x60000000
+#define CONFIG_SYS_FSL_IFC_SIZE		0x20000000
+#define CONFIG_SYS_FSL_DRAM_BASE1	0x80000000
+#define CONFIG_SYS_FSL_DRAM_SIZE1	0x80000000
+#define CONFIG_SYS_FSL_QBMAN_BASE	0x500000000
+#define CONFIG_SYS_FSL_QBMAN_SIZE	0x10000000
+#define CONFIG_SYS_FSL_DRAM_BASE2	0x880000000
+#define CONFIG_SYS_FSL_DRAM_SIZE2	0x780000000	/* 30GB */
+#define CONFIG_SYS_PCIE1_PHYS_SIZE	0x800000000
+#define CONFIG_SYS_PCIE2_PHYS_SIZE	0x800000000
+#define CONFIG_SYS_PCIE3_PHYS_SIZE	0x800000000
+#define CONFIG_SYS_FSL_DRAM_BASE3	0x8800000000
+#define CONFIG_SYS_FSL_DRAM_SIZE3	0x7800000000	/* 480GB */
+#endif
+
+struct sys_mmu_table {
+	u64 virt_addr;
+	u64 phys_addr;
+	u64 size;
+	u64 memory_type;
+	u64 share;
+};
+
+struct table_info {
+	u64 *ptr;
+	u64 table_base;
+	u64 entry_size;
+};
+
+static const struct sys_mmu_table early_mmu_table[] = {
+#ifdef CONFIG_FSL_LSCH3
+	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+	/* For IFC Region #1, only the first 4MB is cache-enabled */
+	{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
+	  CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+	  CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+	  CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
+	  MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
+	  CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+#elif defined(CONFIG_FSL_LSCH2)
+	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
+	  CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+#endif
+};
+
+static const struct sys_mmu_table final_mmu_table[] = {
+#ifdef CONFIG_FSL_LSCH3
+	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+	{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
+	  CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+	  CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
+	  CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
+	  CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	/* For QBMAN portal, only the first 64MB is cache-enabled */
+	{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
+	  CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
+	  CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
+	  CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
+	  MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
+	  CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
+	  CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
+	  CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+#ifdef CONFIG_LS2085A
+	{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
+	  CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+#endif
+	{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
+	  CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
+	  CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
+	  CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+#elif defined(CONFIG_FSL_LSCH2)
+	{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
+	  CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+	  CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
+	  CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
+	  PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
+	{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
+	  CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
+	  CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
+	  CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
+	  CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
+	  CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+#endif
+};
+#endif
+
+int fsl_qoriq_core_to_cluster(unsigned int core);
+u32 cpu_mask(void);
+#endif /* _FSL_LAYERSCAPE_CPU_H */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/fdt.h b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
index 21d20fba21..4da73ab142 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/fdt.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
@@ -4,7 +4,11 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
+
 void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt);
 void append_mmu_masters(void *blob, const char *smmu_path,
 			const char *master_name, u32 *stream_ids, int count);
 void fdt_fixup_smmu_pcie(void *blob);
+#endif	/* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
new file mode 100644
index 0000000000..e1043b5a5f
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_SERDES_H__
+#define __FSL_SERDES_H__
+
+#include <config.h>
+
+#if defined(CONFIG_LS2085A)
+enum srds_prtcl {
+	NONE = 0,
+	PCIE1,
+	PCIE2,
+	PCIE3,
+	PCIE4,
+	SATA1,
+	SATA2,
+	XAUI1,
+	XAUI2,
+	XFI1,
+	XFI2,
+	XFI3,
+	XFI4,
+	XFI5,
+	XFI6,
+	XFI7,
+	XFI8,
+	SGMII1,
+	SGMII2,
+	SGMII3,
+	SGMII4,
+	SGMII5,
+	SGMII6,
+	SGMII7,
+	SGMII8,
+	SGMII9,
+	SGMII10,
+	SGMII11,
+	SGMII12,
+	SGMII13,
+	SGMII14,
+	SGMII15,
+	SGMII16,
+	QSGMII_A, /* A indicates MACs 1-4 */
+	QSGMII_B, /* B indicates MACs 5-8 */
+	QSGMII_C, /* C indicates MACs 9-12 */
+	QSGMII_D, /* D indicates MACs 12-16 */
+	SERDES_PRCTL_COUNT
+};
+
+enum srds {
+	FSL_SRDS_1  = 0,
+	FSL_SRDS_2  = 1,
+};
+#elif defined(CONFIG_LS1043A)
+enum srds_prtcl {
+	NONE = 0,
+	PCIE1,
+	PCIE2,
+	PCIE3,
+	PCIE4,
+	SATA1,
+	SATA2,
+	SRIO1,
+	SRIO2,
+	SGMII_FM1_DTSEC1,
+	SGMII_FM1_DTSEC2,
+	SGMII_FM1_DTSEC3,
+	SGMII_FM1_DTSEC4,
+	SGMII_FM1_DTSEC5,
+	SGMII_FM1_DTSEC6,
+	SGMII_FM1_DTSEC9,
+	SGMII_FM1_DTSEC10,
+	SGMII_FM2_DTSEC1,
+	SGMII_FM2_DTSEC2,
+	SGMII_FM2_DTSEC3,
+	SGMII_FM2_DTSEC4,
+	SGMII_FM2_DTSEC5,
+	SGMII_FM2_DTSEC6,
+	SGMII_FM2_DTSEC9,
+	SGMII_FM2_DTSEC10,
+	SGMII_TSEC1,
+	SGMII_TSEC2,
+	SGMII_TSEC3,
+	SGMII_TSEC4,
+	XAUI_FM1,
+	XAUI_FM2,
+	AURORA,
+	CPRI1,
+	CPRI2,
+	CPRI3,
+	CPRI4,
+	CPRI5,
+	CPRI6,
+	CPRI7,
+	CPRI8,
+	XAUI_FM1_MAC9,
+	XAUI_FM1_MAC10,
+	XAUI_FM2_MAC9,
+	XAUI_FM2_MAC10,
+	HIGIG_FM1_MAC9,
+	HIGIG_FM1_MAC10,
+	HIGIG_FM2_MAC9,
+	HIGIG_FM2_MAC10,
+	QSGMII_FM1_A,		/* A indicates MACs 1,2,5,6 */
+	QSGMII_FM1_B,		/* B indicates MACs 5,6,9,10 */
+	QSGMII_FM2_A,
+	QSGMII_FM2_B,
+	XFI_FM1_MAC1,
+	XFI_FM1_MAC2,
+	XFI_FM1_MAC9,
+	XFI_FM1_MAC10,
+	XFI_FM2_MAC9,
+	XFI_FM2_MAC10,
+	INTERLAKEN,
+	QSGMII_SW1_A,		/* Indicates ports on L2 Switch */
+	QSGMII_SW1_B,
+	SGMII_2500_FM1_DTSEC1,
+	SGMII_2500_FM1_DTSEC2,
+	SGMII_2500_FM1_DTSEC3,
+	SGMII_2500_FM1_DTSEC4,
+	SGMII_2500_FM1_DTSEC5,
+	SGMII_2500_FM1_DTSEC6,
+	SGMII_2500_FM1_DTSEC9,
+	SGMII_2500_FM1_DTSEC10,
+	SGMII_2500_FM2_DTSEC1,
+	SGMII_2500_FM2_DTSEC2,
+	SGMII_2500_FM2_DTSEC3,
+	SGMII_2500_FM2_DTSEC4,
+	SGMII_2500_FM2_DTSEC5,
+	SGMII_2500_FM2_DTSEC6,
+	SGMII_2500_FM2_DTSEC9,
+	SGMII_2500_FM2_DTSEC10,
+	SERDES_PRCTL_COUNT
+};
+
+enum srds {
+	FSL_SRDS_1  = 0,
+};
+
+#endif
+
+int is_serdes_configured(enum srds_prtcl device);
+void fsl_serdes_init(void);
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+
+#ifdef	CONFIG_LS1043A
+const char *serdes_clock_to_string(u32 clock);
+int get_serdes_protocol(void);
+#endif
+
+#endif /* __FSL_SERDES_H__ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
new file mode 100644
index 0000000000..d941437d63
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -0,0 +1,555 @@
+/*
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_FSL_LSCH2_IMMAP_H__
+#define __ARCH_FSL_LSCH2_IMMAP_H__
+
+#include <fsl_immap.h>
+
+#define CONFIG_SYS_IMMR				0x01000000
+#define CONFIG_SYS_DCSRBAR			0x20000000
+#define CONFIG_SYS_DCSR_DCFG_ADDR	(CONFIG_SYS_DCSRBAR + 0x00220000)
+
+#define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
+#define CONFIG_SYS_CCI400_ADDR			(CONFIG_SYS_IMMR + 0x00180000)
+#define CONFIG_SYS_GIC400_ADDR			(CONFIG_SYS_IMMR + 0x00400000)
+#define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
+#define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
+#define CONFIG_SYS_FSL_CSU_ADDR			(CONFIG_SYS_IMMR + 0x00510000)
+#define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
+#define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00ee00b0)
+#define CONFIG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
+#define CONFIG_SYS_FSL_FMAN_ADDR		(CONFIG_SYS_IMMR + 0x00a00000)
+#define CONFIG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
+#define CONFIG_SYS_FSL_DCFG_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
+#define CONFIG_SYS_FSL_CLK_ADDR			(CONFIG_SYS_IMMR + 0x00ee1000)
+#define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
+#define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011c0600)
+#define CONFIG_SYS_NS16550_COM3			(CONFIG_SYS_IMMR + 0x011d0500)
+#define CONFIG_SYS_NS16550_COM4			(CONFIG_SYS_IMMR + 0x011d0600)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x01f00000)
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02000000)
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
+#define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
+#define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
+#define CONFIG_SYS_FSL_SEC_ADDR			(CONFIG_SYS_IMMR + 0x700000)
+#define CONFIG_SYS_FSL_JR0_ADDR			(CONFIG_SYS_IMMR + 0x710000)
+#define CONFIG_SYS_SNVS_ADDR			(CONFIG_SYS_IMMR + 0xe90000)
+#define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0xe80200)
+
+#define CONFIG_SYS_FSL_TIMER_ADDR		0x02b00000
+
+#define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01180000)
+#define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01190000)
+#define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x011a0000)
+#define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x011b0000)
+
+#define WDOG1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01ad0000)
+
+#define QSPI0_BASE_ADDR				(CONFIG_SYS_IMMR + 0x00550000)
+#define DSPI1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01100000)
+
+#define LPUART_BASE				(CONFIG_SYS_IMMR + 0x01950000)
+
+#define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
+
+#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x4000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x4800000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x5000000000ULL
+
+/* TZ Address Space Controller Definitions */
+#define TZASC1_BASE			0x01100000	/* as per CCSR map. */
+#define TZASC2_BASE			0x01110000	/* as per CCSR map. */
+#define TZASC3_BASE			0x01120000	/* as per CCSR map. */
+#define TZASC4_BASE			0x01130000	/* as per CCSR map. */
+#define TZASC_BUILD_CONFIG_REG(x)	((TZASC1_BASE + (x * 0x10000)))
+#define TZASC_ACTION_REG(x)		((TZASC1_BASE + (x * 0x10000)) + 0x004)
+#define TZASC_GATE_KEEPER(x)		((TZASC1_BASE + (x * 0x10000)) + 0x008)
+#define TZASC_REGION_BASE_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x100)
+#define TZASC_REGION_BASE_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x104)
+#define TZASC_REGION_TOP_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x108)
+#define TZASC_REGION_TOP_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x10C)
+#define TZASC_REGION_ATTRIBUTES_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x110)
+#define TZASC_REGION_ID_ACCESS_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x114)
+
+#define TP_ITYP_AV              0x00000001      /* Initiator available */
+#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1)      /* Initiator Type */
+#define TP_ITYP_TYPE_ARM        0x0
+#define TP_ITYP_TYPE_PPC        0x1             /* PowerPC */
+#define TP_ITYP_TYPE_OTHER      0x2             /* StarCore DSP */
+#define TP_ITYP_TYPE_HA         0x3             /* HW Accelerator */
+#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3)     /* # threads */
+#define TP_ITYP_VER(x)  (((x) & 0xe0) >> 5)     /* Initiator Version */
+#define TY_ITYP_VER_A7          0x1
+#define TY_ITYP_VER_A53         0x2
+#define TY_ITYP_VER_A57         0x3
+
+#define TP_CLUSTER_EOC		0xc0000000      /* end of clusters */
+#define TP_CLUSTER_INIT_MASK    0x0000003f      /* initiator mask */
+#define TP_INIT_PER_CLUSTER     4
+
+/*
+ * Define default values for some CCSR macros to make header files cleaner*
+ *
+ * To completely disable CCSR relocation in a board header file, define
+ * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
+ * to a value that is the same as CONFIG_SYS_CCSRBAR.
+ */
+
+#ifdef CONFIG_SYS_CCSRBAR_PHYS
+#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly.  Use \
+CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
+#endif
+
+#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR		CONFIG_SYS_CCSRBAR_DEFAULT
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR_DEFAULT
+#endif
+
+#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
+
+struct sys_info {
+	unsigned long freq_processor[CONFIG_MAX_CPUS];
+	unsigned long freq_systembus;
+	unsigned long freq_ddrbus;
+	unsigned long freq_localbus;
+	unsigned long freq_sdhc;
+#ifdef CONFIG_SYS_DPAA_FMAN
+	unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
+#endif
+	unsigned long freq_qman;
+};
+
+#define CONFIG_SYS_FSL_FM1_OFFSET		0xa00000
+#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0xa88000
+#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0xa89000
+#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET	0xa8a000
+#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET	0xa8b000
+#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET	0xa8c000
+#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET	0xa8d000
+
+#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0xae0000
+#define CONFIG_SYS_FSL_FM1_ADDR			\
+		(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
+#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR		\
+		(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
+
+/* Device Configuration and Pin Control */
+struct ccsr_gur {
+	u32     porsr1;         /* POR status 1 */
+#define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK	0xFF800000
+	u32     porsr2;         /* POR status 2 */
+	u8      res_008[0x20-0x8];
+	u32     gpporcr1;       /* General-purpose POR configuration */
+	u32	gpporcr2;
+#define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT	25
+#define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK	0x1F
+#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT	20
+#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK	0x1F
+	u32     dcfg_fusesr;    /* Fuse status register */
+	u8      res_02c[0x70-0x2c];
+	u32     devdisr;        /* Device disable control */
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_1	0x80000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_2	0x40000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_3	0x20000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_4	0x10000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_5	0x08000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_6	0x04000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_9	0x00800000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_10	0x00400000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_1	0x00800000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_2	0x00400000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_3	0x80000000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_4	0x40000000
+	u32     devdisr2;       /* Device disable control 2 */
+	u32     devdisr3;       /* Device disable control 3 */
+	u32     devdisr4;       /* Device disable control 4 */
+	u32     devdisr5;       /* Device disable control 5 */
+	u32     devdisr6;       /* Device disable control 6 */
+	u32     devdisr7;       /* Device disable control 7 */
+	u8      res_08c[0x94-0x8c];
+	u32     coredisru;      /* uppper portion for support of 64 cores */
+	u32     coredisrl;      /* lower portion for support of 64 cores */
+	u8      res_09c[0xa0-0x9c];
+	u32     pvr;            /* Processor version */
+	u32     svr;            /* System version */
+	u32     mvr;            /* Manufacturing version */
+	u8	res_0ac[0xb0-0xac];
+	u32	rstcr;		/* Reset control */
+	u32	rstrqpblsr;	/* Reset request preboot loader status */
+	u8	res_0b8[0xc0-0xb8];
+	u32	rstrqmr1;	/* Reset request mask */
+	u8	res_0c4[0xc8-0xc4];
+	u32	rstrqsr1;	/* Reset request status */
+	u8	res_0cc[0xd4-0xcc];
+	u32	rstrqwdtmrl;	/* Reset request WDT mask */
+	u8	res_0d8[0xdc-0xd8];
+	u32	rstrqwdtsrl;	/* Reset request WDT status */
+	u8	res_0e0[0xe4-0xe0];
+	u32	brrl;		/* Boot release */
+	u8      res_0e8[0x100-0xe8];
+	u32     rcwsr[16];      /* Reset control word status */
+#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT	25
+#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK	0x1f
+#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT	16
+#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK	0x3f
+#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK	0xffff0000
+#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT	16
+	u8      res_140[0x200-0x140];
+	u32     scratchrw[4];  /* Scratch Read/Write */
+	u8      res_210[0x300-0x210];
+	u32     scratchw1r[4];  /* Scratch Read (Write once) */
+	u8      res_310[0x400-0x310];
+	u32	crstsr[12];
+	u8	res_430[0x500-0x430];
+
+	/* PCI Express n Logical I/O Device Number register */
+	u32 dcfg_ccsr_pex1liodnr;
+	u32 dcfg_ccsr_pex2liodnr;
+	u32 dcfg_ccsr_pex3liodnr;
+	u32 dcfg_ccsr_pex4liodnr;
+	/* RIO n Logical I/O Device Number register */
+	u32 dcfg_ccsr_rio1liodnr;
+	u32 dcfg_ccsr_rio2liodnr;
+	u32 dcfg_ccsr_rio3liodnr;
+	u32 dcfg_ccsr_rio4liodnr;
+	/* USB Logical I/O Device Number register */
+	u32 dcfg_ccsr_usb1liodnr;
+	u32 dcfg_ccsr_usb2liodnr;
+	u32 dcfg_ccsr_usb3liodnr;
+	u32 dcfg_ccsr_usb4liodnr;
+	/* SD/MMC Logical I/O Device Number register */
+	u32 dcfg_ccsr_sdmmc1liodnr;
+	u32 dcfg_ccsr_sdmmc2liodnr;
+	u32 dcfg_ccsr_sdmmc3liodnr;
+	u32 dcfg_ccsr_sdmmc4liodnr;
+	/* RIO Message Unit Logical I/O Device Number register */
+	u32 dcfg_ccsr_riomaintliodnr;
+
+	u8      res_544[0x550-0x544];
+	u32	sataliodnr[4];
+	u8	res_560[0x570-0x560];
+
+	u32 dcfg_ccsr_misc1liodnr;
+	u32 dcfg_ccsr_misc2liodnr;
+	u32 dcfg_ccsr_misc3liodnr;
+	u32 dcfg_ccsr_misc4liodnr;
+	u32 dcfg_ccsr_dma1liodnr;
+	u32 dcfg_ccsr_dma2liodnr;
+	u32 dcfg_ccsr_dma3liodnr;
+	u32 dcfg_ccsr_dma4liodnr;
+	u32 dcfg_ccsr_spare1liodnr;
+	u32 dcfg_ccsr_spare2liodnr;
+	u32 dcfg_ccsr_spare3liodnr;
+	u32 dcfg_ccsr_spare4liodnr;
+	u8	res_5a0[0x600-0x5a0];
+	u32 dcfg_ccsr_pblsr;
+
+	u32	pamubypenr;
+	u32	dmacr1;
+
+	u8	res_60c[0x610-0x60c];
+	u32 dcfg_ccsr_gensr1;
+	u32 dcfg_ccsr_gensr2;
+	u32 dcfg_ccsr_gensr3;
+	u32 dcfg_ccsr_gensr4;
+	u32 dcfg_ccsr_gencr1;
+	u32 dcfg_ccsr_gencr2;
+	u32 dcfg_ccsr_gencr3;
+	u32 dcfg_ccsr_gencr4;
+	u32 dcfg_ccsr_gencr5;
+	u32 dcfg_ccsr_gencr6;
+	u32 dcfg_ccsr_gencr7;
+	u8	res_63c[0x658-0x63c];
+	u32 dcfg_ccsr_cgensr1;
+	u32 dcfg_ccsr_cgensr0;
+	u8	res_660[0x678-0x660];
+	u32 dcfg_ccsr_cgencr1;
+
+	u32 dcfg_ccsr_cgencr0;
+	u8	res_680[0x700-0x680];
+	u32 dcfg_ccsr_sriopstecr;
+	u32 dcfg_ccsr_dcsrcr;
+
+	u8      res_708[0x740-0x708];   /* add more registers when needed */
+	u32     tp_ityp[64];    /* Topology Initiator Type Register */
+	struct {
+		u32     upper;
+		u32     lower;
+	} tp_cluster[16];
+	u8      res_8c0[0xa00-0x8c0];   /* add more registers when needed */
+	u32 dcfg_ccsr_qmbm_warmrst;
+	u8      res_a04[0xa20-0xa04];   /* add more registers when needed */
+	u32 dcfg_ccsr_reserved0;
+	u32 dcfg_ccsr_reserved1;
+};
+
+#define SCFG_QSPI_CLKSEL		0x40100000
+#define SCFG_USBDRVVBUS_SELCR_USB1	0x00000000
+#define SCFG_USBDRVVBUS_SELCR_USB2	0x00000001
+#define SCFG_USBDRVVBUS_SELCR_USB3	0x00000002
+#define SCFG_USBPWRFAULT_INACTIVE	0x00000000
+#define SCFG_USBPWRFAULT_SHARED		0x00000001
+#define SCFG_USBPWRFAULT_DEDICATED	0x00000002
+#define SCFG_USBPWRFAULT_USB3_SHIFT	4
+#define SCFG_USBPWRFAULT_USB2_SHIFT	2
+#define SCFG_USBPWRFAULT_USB1_SHIFT	0
+
+#define SCFG_SNPCNFGCR_SECRDSNP		0x80000000
+#define SCFG_SNPCNFGCR_SECWRSNP		0x40000000
+
+/* Supplemental Configuration Unit */
+struct ccsr_scfg {
+	u8 res_000[0x100-0x000];
+	u32 usb2_icid;
+	u32 usb3_icid;
+	u8 res_108[0x114-0x108];
+	u32 dma_icid;
+	u32 sata_icid;
+	u32 usb1_icid;
+	u32 qe_icid;
+	u32 sdhc_icid;
+	u32 edma_icid;
+	u32 etr_icid;
+	u32 core_sft_rst[4];
+	u8 res_140[0x158-0x140];
+	u32 altcbar;
+	u32 qspi_cfg;
+	u8 res_160[0x180-0x160];
+	u32 dmamcr;
+	u8 res_184[0x18c-0x184];
+	u32 debug_icid;
+	u8 res_190[0x1a4-0x190];
+	u32 snpcnfgcr;
+	u8 res_1a8[0x1ac-0x1a8];
+	u32 intpcr;
+	u8 res_1b0[0x204-0x1b0];
+	u32 coresrencr;
+	u8 res_208[0x220-0x208];
+	u32 rvbar0_0;
+	u32 rvbar0_1;
+	u32 rvbar1_0;
+	u32 rvbar1_1;
+	u32 rvbar2_0;
+	u32 rvbar2_1;
+	u32 rvbar3_0;
+	u32 rvbar3_1;
+	u32 lpmcsr;
+	u8 res_244[0x400-0x244];
+	u32 qspidqscr;
+	u32 ecgtxcmcr;
+	u32 sdhciovselcr;
+	u32 rcwpmuxcr0;
+	u32 usbdrvvbus_selcr;
+	u32 usbpwrfault_selcr;
+	u32 usb_refclk_selcr1;
+	u32 usb_refclk_selcr2;
+	u32 usb_refclk_selcr3;
+	u8 res_424[0x600-0x424];
+	u32 scratchrw[4];
+	u8 res_610[0x680-0x610];
+	u32 corebcr;
+	u8 res_684[0x1000-0x684];
+	u32 pex1msiir;
+	u32 pex1msir;
+	u8 res_1008[0x2000-0x1008];
+	u32 pex2;
+	u32 pex2msir;
+	u8 res_2008[0x3000-0x2008];
+	u32 pex3msiir;
+	u32 pex3msir;
+};
+
+/* Clocking */
+struct ccsr_clk {
+	struct {
+		u32 clkcncsr;	/* core cluster n clock control status */
+		u8  res_004[0x0c];
+		u32 clkcghwacsr; /* Clock generator n hardware accelerator */
+		u8  res_014[0x0c];
+	} clkcsr[4];
+	u8	res_040[0x780]; /* 0x100 */
+	struct {
+		u32 pllcngsr;
+		u8 res_804[0x1c];
+	} pllcgsr[2];
+	u8	res_840[0x1c0];
+	u32	clkpcsr;	/* 0xa00 Platform clock domain control/status */
+	u8	res_a04[0x1fc];
+	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
+	u8	res_c04[0x1c];
+	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
+	u8	res_c24[0x3dc];
+};
+
+/* System Counter */
+struct sctr_regs {
+	u32 cntcr;
+	u32 cntsr;
+	u32 cntcv1;
+	u32 cntcv2;
+	u32 resv1[4];
+	u32 cntfid0;
+	u32 cntfid1;
+	u32 resv2[1002];
+	u32 counterid[12];
+};
+
+#define SRDS_MAX_LANES		4
+struct ccsr_serdes {
+	struct {
+		u32	rstctl;	/* Reset Control Register */
+#define SRDS_RSTCTL_RST		0x80000000
+#define SRDS_RSTCTL_RSTDONE	0x40000000
+#define SRDS_RSTCTL_RSTERR	0x20000000
+#define SRDS_RSTCTL_SWRST	0x10000000
+#define SRDS_RSTCTL_SDEN	0x00000020
+#define SRDS_RSTCTL_SDRST_B	0x00000040
+#define SRDS_RSTCTL_PLLRST_B	0x00000080
+		u32	pllcr0; /* PLL Control Register 0 */
+#define SRDS_PLLCR0_POFF		0x80000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
+#define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
+#define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
+#define SRDS_PLLCR0_PLL_LCK		0x00800000
+#define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
+#define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
+#define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
+#define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
+#define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
+		u32	pllcr1; /* PLL Control Register 1 */
+#define SRDS_PLLCR1_PLL_BWSEL	0x08000000
+		u32	res_0c;	/* 0x00c */
+		u32	pllcr3;
+		u32	pllcr4;
+		u8	res_18[0x20-0x18];
+	} bank[2];
+	u8	res_40[0x90-0x40];
+	u32	srdstcalcr;	/* 0x90 TX Calibration Control */
+	u8	res_94[0xa0-0x94];
+	u32	srdsrcalcr;	/* 0xa0 RX Calibration Control */
+	u8	res_a4[0xb0-0xa4];
+	u32	srdsgr0;	/* 0xb0 General Register 0 */
+	u8	res_b4[0xe0-0xb4];
+	u32	srdspccr0;	/* 0xe0 Protocol Converter Config 0 */
+	u32	srdspccr1;	/* 0xe4 Protocol Converter Config 1 */
+	u32	srdspccr2;	/* 0xe8 Protocol Converter Config 2 */
+	u32	srdspccr3;	/* 0xec Protocol Converter Config 3 */
+	u32	srdspccr4;	/* 0xf0 Protocol Converter Config 4 */
+	u8	res_f4[0x100-0xf4];
+	struct {
+		u32	lnpssr;	/* 0x100, 0x120, ..., 0x1e0 */
+		u8	res_104[0x120-0x104];
+	} srdslnpssr[4];
+	u8	res_180[0x300-0x180];
+	u32	srdspexeqcr;
+	u32	srdspexeqpcr[11];
+	u8	res_330[0x400-0x330];
+	u32	srdspexapcr;
+	u8	res_404[0x440-0x404];
+	u32	srdspexbpcr;
+	u8	res_444[0x800-0x444];
+	struct {
+		u32	gcr0;	/* 0x800 General Control Register 0 */
+		u32	gcr1;	/* 0x804 General Control Register 1 */
+		u32	gcr2;	/* 0x808 General Control Register 2 */
+		u32	sscr0;
+		u32	recr0;	/* 0x810 Receive Equalization Control */
+		u32	recr1;
+		u32	tecr0;	/* 0x818 Transmit Equalization Control */
+		u32	sscr1;
+		u32	ttlcr0;	/* 0x820 Transition Tracking Loop Ctrl 0 */
+		u8	res_824[0x83c-0x824];
+		u32	tcsr3;
+	} lane[4];	/* Lane A, B, C, D, E, F, G, H */
+	u8	res_a00[0x1000-0xa00];	/* from 0xa00 to 0xfff */
+};
+
+#define CCI400_CTRLORD_TERM_BARRIER	0x00000008
+#define CCI400_CTRLORD_EN_BARRIER	0
+#define CCI400_SHAORD_NON_SHAREABLE	0x00000002
+#define CCI400_DVM_MESSAGE_REQ_EN	0x00000002
+#define CCI400_SNOOP_REQ_EN		0x00000001
+
+/* CCI-400 registers */
+struct ccsr_cci400 {
+	u32 ctrl_ord;			/* Control Override */
+	u32 spec_ctrl;			/* Speculation Control */
+	u32 secure_access;		/* Secure Access */
+	u32 status;			/* Status */
+	u32 impr_err;			/* Imprecise Error */
+	u8 res_14[0x100 - 0x14];
+	u32 pmcr;			/* Performance Monitor Control */
+	u8 res_104[0xfd0 - 0x104];
+	u32 pid[8];			/* Peripheral ID */
+	u32 cid[4];			/* Component ID */
+	struct {
+		u32 snoop_ctrl;		/* Snoop Control */
+		u32 sha_ord;		/* Shareable Override */
+		u8 res_1008[0x1100 - 0x1008];
+		u32 rc_qos_ord;		/* read channel QoS Value Override */
+		u32 wc_qos_ord;		/* read channel QoS Value Override */
+		u8 res_1108[0x110c - 0x1108];
+		u32 qos_ctrl;		/* QoS Control */
+		u32 max_ot;		/* Max OT */
+		u8 res_1114[0x1130 - 0x1114];
+		u32 target_lat;		/* Target Latency */
+		u32 latency_regu;	/* Latency Regulation */
+		u32 qos_range;		/* QoS Range */
+		u8 res_113c[0x2000 - 0x113c];
+	} slave[5];			/* Slave Interface */
+	u8 res_6000[0x9004 - 0x6000];
+	u32 cycle_counter;		/* Cycle counter */
+	u32 count_ctrl;			/* Count Control */
+	u32 overflow_status;		/* Overflow Flag Status */
+	u8 res_9010[0xa000 - 0x9010];
+	struct {
+		u32 event_select;	/* Event Select */
+		u32 event_count;	/* Event Count */
+		u32 counter_ctrl;	/* Counter Control */
+		u32 overflow_status;	/* Overflow Flag Status */
+		u8 res_a010[0xb000 - 0xa010];
+	} pcounter[4];			/* Performance Counter */
+	u8 res_e004[0x10000 - 0xe004];
+};
+
+/* MMU 500 */
+#define SMMU_SCR0			(SMMU_BASE + 0x0)
+#define SMMU_SCR1			(SMMU_BASE + 0x4)
+#define SMMU_SCR2			(SMMU_BASE + 0x8)
+#define SMMU_SACR			(SMMU_BASE + 0x10)
+#define SMMU_IDR0			(SMMU_BASE + 0x20)
+#define SMMU_IDR1			(SMMU_BASE + 0x24)
+
+#define SMMU_NSCR0			(SMMU_BASE + 0x400)
+#define SMMU_NSCR2			(SMMU_BASE + 0x408)
+#define SMMU_NSACR			(SMMU_BASE + 0x410)
+
+#define SCR0_CLIENTPD_MASK		0x00000001
+#define SCR0_USFCFG_MASK		0x00000400
+
+#endif	/* __ARCH_FSL_LSCH2_IMMAP_H__*/
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index d6bee60385..6a70d44305 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -6,9 +6,109 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __ARCH_FSL_LSCH3_IMMAP_H
+#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
 #define __ARCH_FSL_LSCH3_IMMAP_H_
 
+#define CONFIG_SYS_IMMR				0x01000000
+#define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
+#define CONFIG_SYS_FSL_DDR2_ADDR		(CONFIG_SYS_IMMR + 0x00090000)
+#define CONFIG_SYS_FSL_DDR3_ADDR		0x08210000
+#define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00E00000)
+#define CONFIG_SYS_FSL_PMU_ADDR			(CONFIG_SYS_IMMR + 0x00E30000)
+#define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00E60000)
+#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR	(CONFIG_SYS_IMMR + 0x00300000)
+#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR	(CONFIG_SYS_IMMR + 0x00310000)
+#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR + 0x00370000)
+#define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x01140000)
+#define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
+#define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011C0500)
+#define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011C0600)
+#define CONFIG_SYS_FSL_TIMER_ADDR		0x023d0000
+#define CONFIG_SYS_FSL_PMU_CLTBENR		(CONFIG_SYS_FSL_PMU_ADDR + \
+						 0x18A0)
+
+#define CONFIG_SYS_FSL_WRIOP1_ADDR		(CONFIG_SYS_IMMR + 0x7B80000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO1	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO2	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
+#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR	(CONFIG_SYS_IMMR + 0xEA0000)
+
+/* SP (Cortex-A5) related */
+#define CONFIG_SYS_FSL_SP_ADDR			(CONFIG_SYS_IMMR + 0x00F00000)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR		(CONFIG_SYS_FSL_SP_ADDR)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1		(CONFIG_SYS_FSL_SP_ADDR)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2		\
+					(CONFIG_SYS_FSL_SP_ADDR + 0x0008)
+#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART	\
+					(CONFIG_SYS_FSL_SP_ADDR + 0x1000)
+
+#define CONFIG_SYS_FSL_DCSR_DDR_ADDR		0x70012c000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR		0x70012d000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR		0x700132000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR		0x700133000ULL
+
+#define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01000000)
+#define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01010000)
+#define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01020000)
+#define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01030000)
+
+#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR	(CONFIG_SYS_IMMR + 0x02110000)
+
+/* TZ Address Space Controller Definitions */
+#define TZASC1_BASE			0x01100000	/* as per CCSR map. */
+#define TZASC2_BASE			0x01110000	/* as per CCSR map. */
+#define TZASC3_BASE			0x01120000	/* as per CCSR map. */
+#define TZASC4_BASE			0x01130000	/* as per CCSR map. */
+#define TZASC_BUILD_CONFIG_REG(x)	((TZASC1_BASE + (x * 0x10000)))
+#define TZASC_ACTION_REG(x)		((TZASC1_BASE + (x * 0x10000)) + 0x004)
+#define TZASC_GATE_KEEPER(x)		((TZASC1_BASE + (x * 0x10000)) + 0x008)
+#define TZASC_REGION_BASE_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x100)
+#define TZASC_REGION_BASE_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x104)
+#define TZASC_REGION_TOP_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x108)
+#define TZASC_REGION_TOP_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x10C)
+#define TZASC_REGION_ATTRIBUTES_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x110)
+#define TZASC_REGION_ID_ACCESS_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x114)
+
+/* PCIe */
+#define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
+#define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
+#define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
+#define CONFIG_SYS_PCIE4_ADDR			(CONFIG_SYS_IMMR + 0x2700000)
+#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x1000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x1200000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x1400000000ULL
+#define CONFIG_SYS_PCIE4_PHYS_ADDR		0x1600000000ULL
+
+/* Device Configuration */
+#define DCFG_BASE		0x01e00000
+#define DCFG_PORSR1			0x000
+#define DCFG_PORSR1_RCW_SRC		0xff800000
+#define DCFG_PORSR1_RCW_SRC_NOR		0x12f00000
+#define DCFG_RCWSR13			0x130
+#define DCFG_RCWSR13_DSPI		(0 << 8)
+
+#define DCFG_DCSR_BASE		0X700100000ULL
+#define DCFG_DCSR_PORCR1		0x000
+
+/* Supplemental Configuration */
+#define SCFG_BASE		0x01fc0000
+#define SCFG_USB3PRM1CR			0x000
+
+#define TP_ITYP_AV		0x00000001	/* Initiator available */
+#define TP_ITYP_TYPE(x)	(((x) & 0x6) >> 1)	/* Initiator Type */
+#define TP_ITYP_TYPE_ARM	0x0
+#define TP_ITYP_TYPE_PPC	0x1		/* PowerPC */
+#define TP_ITYP_TYPE_OTHER	0x2		/* StarCore DSP */
+#define TP_ITYP_TYPE_HA		0x3		/* HW Accelerator */
+#define TP_ITYP_THDS(x)	(((x) & 0x18) >> 3)	/* # threads */
+#define TP_ITYP_VER(x)	(((x) & 0xe0) >> 5)	/* Initiator Version */
+#define TY_ITYP_VER_A7		0x1
+#define TY_ITYP_VER_A53		0x2
+#define TY_ITYP_VER_A57		0x3
+
+#define TP_CLUSTER_EOC		0x80000000	/* end of clusters */
+#define TP_CLUSTER_INIT_MASK	0x0000003f	/* initiator mask */
+#define TP_INIT_PER_CLUSTER     4
 /* This is chassis generation 3 */
 
 struct sys_info {
@@ -109,21 +209,6 @@ struct ccsr_gur {
 	u8	res_858[0x1000-0x858];
 };
 
-#define TP_ITYP_AV		0x00000001	/* Initiator available */
-#define TP_ITYP_TYPE(x)	(((x) & 0x6) >> 1)	/* Initiator Type */
-#define TP_ITYP_TYPE_ARM	0x0
-#define TP_ITYP_TYPE_PPC	0x1		/* PowerPC */
-#define TP_ITYP_TYPE_OTHER	0x2		/* StarCore DSP */
-#define TP_ITYP_TYPE_HA		0x3		/* HW Accelerator */
-#define TP_ITYP_THDS(x)	(((x) & 0x18) >> 3)	/* # threads */
-#define TP_ITYP_VER(x)	(((x) & 0xe0) >> 5)	/* Initiator Version */
-#define TY_ITYP_VER_A7		0x1
-#define TY_ITYP_VER_A53		0x2
-#define TY_ITYP_VER_A57		0x3
-
-#define TP_CLUSTER_EOC		0x80000000	/* end of clusters */
-#define TP_CLUSTER_INIT_MASK	0x0000003f	/* initiator mask */
-#define TP_INIT_PER_CLUSTER     4
 
 struct ccsr_clk_cluster_group {
 	struct {
@@ -180,4 +265,4 @@ struct ccsr_reset {
 	u32 ip_rev1;			/* 0xbf8 */
 	u32 ip_rev2;			/* 0xbfc */
 };
-#endif /* __ARCH_FSL_LSCH3_IMMAP_H */
+#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
new file mode 100644
index 0000000000..57e417b9e0
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#ifndef __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
+#define __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
+
+#define I2C_QUIRK_REG	/* enable 8-bit driver */
+
+#ifdef CONFIG_FSL_LPUART
+#ifdef CONFIG_LPUART_32B_REG
+struct lpuart_fsl {
+	u32 baud;
+	u32 stat;
+	u32 ctrl;
+	u32 data;
+	u32 match;
+	u32 modir;
+	u32 fifo;
+	u32 water;
+};
+#else
+struct lpuart_fsl {
+	u8 ubdh;
+	u8 ubdl;
+	u8 uc1;
+	u8 uc2;
+	u8 us1;
+	u8 us2;
+	u8 uc3;
+	u8 ud;
+	u8 uma1;
+	u8 uma2;
+	u8 uc4;
+	u8 uc5;
+	u8 ued;
+	u8 umodem;
+	u8 uir;
+	u8 reserved;
+	u8 upfifo;
+	u8 ucfifo;
+	u8 usfifo;
+	u8 utwfifo;
+	u8 utcfifo;
+	u8 urwfifo;
+	u8 urcfifo;
+	u8 rsvd[28];
+};
+#endif
+#endif	/* CONFIG_FSL_LPUART */
+
+#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h b/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h
index 5c945309a9..5c945309a9 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mmu.h b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h
new file mode 100644
index 0000000000..d54eacd4a0
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
+#include <asm/arch-armv8/mmu.h>
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
index c985d6a6ba..e46e076f16 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
@@ -1,11 +1,11 @@
 /*
- * Copyright 2014, Freescale Semiconductor
+ * Copyright 2014-2015, Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef _FSL_CH3_MP_H
-#define _FSL_CH3_MP_H
+#ifndef _FSL_LAYERSCAPE_MP_H
+#define _FSL_LAYERSCAPE_MP_H
 
 /*
 * Each spin table element is defined as
@@ -29,10 +29,10 @@ extern u64 __spin_table[];
 extern u64 __real_cntfrq;
 extern u64 *secondary_boot_code;
 extern size_t __secondary_boot_code_size;
-int fsl_lsch3_wake_seconday_cores(void);
+int fsl_layerscape_wake_seconday_cores(void);
 void *get_spin_tbl_addr(void);
 phys_addr_t determine_mp_bootpg(void);
 void secondary_boot_func(void);
 int is_core_online(u64 cpu_id);
 #endif
-#endif /* _FSL_CH3_MP_H */
+#endif /* _FSL_LAYERSCAPE_MP_H */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
new file mode 100644
index 0000000000..a3ccdb03c7
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_NS_ACCESS_H_
+#define __FSL_NS_ACCESS_H_
+
+enum csu_cslx_ind {
+	CSU_CSLX_PCIE2_IO = 0,
+	CSU_CSLX_PCIE1_IO,
+	CSU_CSLX_MG2TPR_IP,
+	CSU_CSLX_IFC_MEM,
+	CSU_CSLX_OCRAM,
+	CSU_CSLX_GIC,
+	CSU_CSLX_PCIE1,
+	CSU_CSLX_OCRAM2,
+	CSU_CSLX_QSPI_MEM,
+	CSU_CSLX_PCIE2,
+	CSU_CSLX_SATA,
+	CSU_CSLX_USB1,
+	CSU_CSLX_QM_BM_SWPORTAL,
+	CSU_CSLX_PCIE3 = 16,
+	CSU_CSLX_PCIE3_IO,
+	CSU_CSLX_USB3 = 20,
+	CSU_CSLX_USB2,
+	CSU_CSLX_SERDES = 32,
+	CSU_CSLX_QDMA,
+	CSU_CSLX_LPUART2,
+	CSU_CSLX_LPUART1,
+	CSU_CSLX_LPUART4,
+	CSU_CSLX_LPUART3,
+	CSU_CSLX_LPUART6,
+	CSU_CSLX_LPUART5,
+	CSU_CSLX_DSPI1 = 41,
+	CSU_CSLX_QSPI,
+	CSU_CSLX_ESDHC,
+	CSU_CSLX_IFC = 45,
+	CSU_CSLX_I2C1,
+	CSU_CSLX_I2C3 = 48,
+	CSU_CSLX_I2C2,
+	CSU_CSLX_DUART2 = 50,
+	CSU_CSLX_DUART1,
+	CSU_CSLX_WDT2,
+	CSU_CSLX_WDT1,
+	CSU_CSLX_EDMA,
+	CSU_CSLX_SYS_CNT,
+	CSU_CSLX_DMA_MUX2,
+	CSU_CSLX_DMA_MUX1,
+	CSU_CSLX_DDR,
+	CSU_CSLX_QUICC,
+	CSU_CSLX_DCFG_CCU_RCPM = 60,
+	CSU_CSLX_SECURE_BOOTROM,
+	CSU_CSLX_SFP,
+	CSU_CSLX_TMU,
+	CSU_CSLX_SECURE_MONITOR,
+	CSU_CSLX_SCFG,
+	CSU_CSLX_FM = 66,
+	CSU_CSLX_SEC5_5,
+	CSU_CSLX_BM,
+	CSU_CSLX_QM,
+	CSU_CSLX_GPIO2 = 70,
+	CSU_CSLX_GPIO1,
+	CSU_CSLX_GPIO4,
+	CSU_CSLX_GPIO3,
+	CSU_CSLX_PLATFORM_CONT,
+	CSU_CSLX_CSU,
+	CSU_CSLX_IIC4 = 77,
+	CSU_CSLX_WDT4,
+	CSU_CSLX_WDT3,
+	CSU_CSLX_WDT5 = 81,
+	CSU_CSLX_FTM2 = 86,
+	CSU_CSLX_FTM1,
+	CSU_CSLX_FTM4,
+	CSU_CSLX_FTM3,
+	CSU_CSLX_FTM6 = 90,
+	CSU_CSLX_FTM5,
+	CSU_CSLX_FTM8,
+	CSU_CSLX_FTM7,
+	CSU_CSLX_DSCR = 121,
+};
+
+static struct csu_ns_dev ns_dev[] = {
+	 {CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
+	 {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
+	 {CSU_CSLX_IFC_MEM, CSU_ALL_RW},
+	 {CSU_CSLX_OCRAM, CSU_ALL_RW},
+	 {CSU_CSLX_GIC, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE1, CSU_ALL_RW},
+	 {CSU_CSLX_OCRAM2, CSU_ALL_RW},
+	 {CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE2, CSU_ALL_RW},
+	 {CSU_CSLX_SATA, CSU_ALL_RW},
+	 {CSU_CSLX_USB1, CSU_ALL_RW},
+	 {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE3, CSU_ALL_RW},
+	 {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
+	 {CSU_CSLX_USB3, CSU_ALL_RW},
+	 {CSU_CSLX_USB2, CSU_ALL_RW},
+	 {CSU_CSLX_SERDES, CSU_ALL_RW},
+	 {CSU_CSLX_QDMA, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART2, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART1, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART4, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART3, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART6, CSU_ALL_RW},
+	 {CSU_CSLX_LPUART5, CSU_ALL_RW},
+	 {CSU_CSLX_DSPI1, CSU_ALL_RW},
+	 {CSU_CSLX_QSPI, CSU_ALL_RW},
+	 {CSU_CSLX_ESDHC, CSU_ALL_RW},
+	 {CSU_CSLX_IFC, CSU_ALL_RW},
+	 {CSU_CSLX_I2C1, CSU_ALL_RW},
+	 {CSU_CSLX_I2C3, CSU_ALL_RW},
+	 {CSU_CSLX_I2C2, CSU_ALL_RW},
+	 {CSU_CSLX_DUART2, CSU_ALL_RW},
+	 {CSU_CSLX_DUART1, CSU_ALL_RW},
+	 {CSU_CSLX_WDT2, CSU_ALL_RW},
+	 {CSU_CSLX_WDT1, CSU_ALL_RW},
+	 {CSU_CSLX_EDMA, CSU_ALL_RW},
+	 {CSU_CSLX_SYS_CNT, CSU_ALL_RW},
+	 {CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
+	 {CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
+	 {CSU_CSLX_DDR, CSU_ALL_RW},
+	 {CSU_CSLX_QUICC, CSU_ALL_RW},
+	 {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
+	 {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
+	 {CSU_CSLX_SFP, CSU_ALL_RW},
+	 {CSU_CSLX_TMU, CSU_ALL_RW},
+	 {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
+	 {CSU_CSLX_SCFG, CSU_ALL_RW},
+	 {CSU_CSLX_FM, CSU_ALL_RW},
+	 {CSU_CSLX_SEC5_5, CSU_ALL_RW},
+	 {CSU_CSLX_BM, CSU_ALL_RW},
+	 {CSU_CSLX_QM, CSU_ALL_RW},
+	 {CSU_CSLX_GPIO2, CSU_ALL_RW},
+	 {CSU_CSLX_GPIO1, CSU_ALL_RW},
+	 {CSU_CSLX_GPIO4, CSU_ALL_RW},
+	 {CSU_CSLX_GPIO3, CSU_ALL_RW},
+	 {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
+	 {CSU_CSLX_CSU, CSU_ALL_RW},
+	 {CSU_CSLX_IIC4, CSU_ALL_RW},
+	 {CSU_CSLX_WDT4, CSU_ALL_RW},
+	 {CSU_CSLX_WDT3, CSU_ALL_RW},
+	 {CSU_CSLX_WDT5, CSU_ALL_RW},
+	 {CSU_CSLX_FTM2, CSU_ALL_RW},
+	 {CSU_CSLX_FTM1, CSU_ALL_RW},
+	 {CSU_CSLX_FTM4, CSU_ALL_RW},
+	 {CSU_CSLX_FTM3, CSU_ALL_RW},
+	 {CSU_CSLX_FTM6, CSU_ALL_RW},
+	 {CSU_CSLX_FTM5, CSU_ALL_RW},
+	 {CSU_CSLX_FTM8, CSU_ALL_RW},
+	 {CSU_CSLX_FTM7, CSU_ALL_RW},
+	 {CSU_CSLX_DSCR, CSU_ALL_RW},
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
new file mode 100644
index 0000000000..5ed456e4e2
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
+
+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
+#define gur_in32(a)       in_le32(a)
+#define gur_out32(a, v)   out_le32(a, v)
+#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
+#define gur_in32(a)       in_be32(a)
+#define gur_out32(a, v)   out_be32(a, v)
+#endif
+
+#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define scfg_in32(a)       in_le32(a)
+#define scfg_out32(a, v)   out_le32(a, v)
+#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
+#define scfg_in32(a)       in_be32(a)
+#define scfg_out32(a, v)   out_be32(a, v)
+#endif
+
+struct cpu_type {
+	char name[15];
+	u32 soc_ver;
+	u32 num_cores;
+};
+
+#define CPU_TYPE_ENTRY(n, v, nc) \
+	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
+
+#define SVR_WO_E		0xFFFFFE
+#define SVR_LS1043		0x879204
+#define SVR_LS2045		0x870120
+#define SVR_LS2080		0x870110
+#define SVR_LS2085		0x870100
+
+#define SVR_MAJ(svr)		(((svr) >> 4) & 0xf)
+#define SVR_MIN(svr)		(((svr) >> 0) & 0xf)
+#define SVR_SOC_VER(svr)	(((svr) >> 8) & SVR_WO_E)
+#define IS_E_PROCESSOR(svr)	(!((svr >> 8) & 0x1))
+
+#ifdef CONFIG_FSL_LSCH3
+void fsl_lsch3_early_init_f(void);
+#elif defined(CONFIG_FSL_LSCH2)
+void fsl_lsch2_early_init_f(void);
+#endif
+
+void cpu_name(char *name);
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/speed.h b/arch/arm/include/asm/arch-fsl-layerscape/speed.h
new file mode 100644
index 0000000000..de795f6056
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/speed.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2014-2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _FSL_LAYERSCAPE_SPEED_H
+#define _FSL_LAYERSCAPE_SPEED_H
+void get_sys_info(struct sys_info *sys_info);
+#endif /* _FSL_LAYERSCAPE_SPEED_H */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
deleted file mode 100644
index 96d6c98cb8..0000000000
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Copyright 2014, Freescale Semiconductor
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_
-#define _ASM_ARMV8_FSL_LSCH3_CONFIG_
-
-#include <fsl_ddrc_version.h>
-
-#define CONFIG_SYS_PAGE_SIZE		0x10000
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
-#ifndef L1_CACHE_BYTES
-#define L1_CACHE_SHIFT		6
-#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
-#endif
-
-#define CONFIG_MP
-#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000	/* initial RAM */
-#define CONFIG_SYS_FSL_OCRAM_SIZE	0x00200000	/* 2M */
-/* Link Definitions */
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
-
-#define CONFIG_SYS_IMMR				0x01000000
-#define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_FSL_DDR2_ADDR		(CONFIG_SYS_IMMR + 0x00090000)
-#define CONFIG_SYS_FSL_DDR3_ADDR		0x08210000
-#define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00E00000)
-#define CONFIG_SYS_FSL_PMU_ADDR			(CONFIG_SYS_IMMR + 0x00E30000)
-#define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00E60000)
-#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR	(CONFIG_SYS_IMMR + 0x00300000)
-#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR	(CONFIG_SYS_IMMR + 0x00310000)
-#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR + 0x00370000)
-#define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x01140000)
-#define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
-#define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011C0500)
-#define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011C0600)
-#define CONFIG_SYS_FSL_TIMER_ADDR		0x023d0000
-#define CONFIG_SYS_FSL_PMU_CLTBENR		(CONFIG_SYS_FSL_PMU_ADDR + \
-						 0x18A0)
-
-#define CONFIG_SYS_FSL_WRIOP1_ADDR		(CONFIG_SYS_IMMR + 0x7B80000)
-#define CONFIG_SYS_FSL_WRIOP1_MDIO1	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
-#define CONFIG_SYS_FSL_WRIOP1_MDIO2	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
-#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR	(CONFIG_SYS_IMMR + 0xEA0000)
-
-/* SP (Cortex-A5) related */
-#define CONFIG_SYS_FSL_SP_ADDR			(CONFIG_SYS_IMMR + 0x00F00000)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR		(CONFIG_SYS_FSL_SP_ADDR)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1		(CONFIG_SYS_FSL_SP_ADDR)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2		\
-					(CONFIG_SYS_FSL_SP_ADDR + 0x0008)
-#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART	\
-					(CONFIG_SYS_FSL_SP_ADDR + 0x1000)
-
-#define CONFIG_SYS_FSL_DCSR_DDR_ADDR		0x70012c000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR		0x70012d000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR		0x700132000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR		0x700133000ULL
-
-#define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01000000)
-#define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01010000)
-#define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01020000)
-#define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01030000)
-
-#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR	(CONFIG_SYS_IMMR + 0x02110000)
-
-/* TZ Protection Controller Definitions */
-#define TZPC_BASE				0x02200000
-#define TZPCR0SIZE_BASE				(TZPC_BASE)
-#define TZPCDECPROT_0_STAT_BASE			(TZPC_BASE + 0x800)
-#define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
-#define TZPCDECPROT_0_CLR_BASE			(TZPC_BASE + 0x808)
-#define TZPCDECPROT_1_STAT_BASE			(TZPC_BASE + 0x80C)
-#define TZPCDECPROT_1_SET_BASE			(TZPC_BASE + 0x810)
-#define TZPCDECPROT_1_CLR_BASE			(TZPC_BASE + 0x814)
-#define TZPCDECPROT_2_STAT_BASE			(TZPC_BASE + 0x818)
-#define TZPCDECPROT_2_SET_BASE			(TZPC_BASE + 0x81C)
-#define TZPCDECPROT_2_CLR_BASE			(TZPC_BASE + 0x820)
-
-/* TZ Address Space Controller Definitions */
-#define TZASC1_BASE			0x01100000	/* as per CCSR map. */
-#define TZASC2_BASE			0x01110000	/* as per CCSR map. */
-#define TZASC3_BASE			0x01120000	/* as per CCSR map. */
-#define TZASC4_BASE			0x01130000	/* as per CCSR map. */
-#define TZASC_BUILD_CONFIG_REG(x)	((TZASC1_BASE + (x * 0x10000)))
-#define TZASC_ACTION_REG(x)		((TZASC1_BASE + (x * 0x10000)) + 0x004)
-#define TZASC_GATE_KEEPER(x)		((TZASC1_BASE + (x * 0x10000)) + 0x008)
-#define TZASC_REGION_BASE_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x100)
-#define TZASC_REGION_BASE_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x104)
-#define TZASC_REGION_TOP_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x108)
-#define TZASC_REGION_TOP_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x10C)
-#define TZASC_REGION_ATTRIBUTES_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x110)
-#define TZASC_REGION_ID_ACCESS_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x114)
-
-/* Generic Interrupt Controller Definitions */
-#define GICD_BASE		0x06000000
-#define GICR_BASE		0x06100000
-
-/* SMMU Defintions */
-#define SMMU_BASE		0x05000000 /* GR0 Base */
-
-/* DDR */
-#define CONFIG_SYS_FSL_DDR_LE
-#define CONFIG_VERY_BIG_RAM
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#else
-#define CONFIG_SYS_FSL_DDRC_ARM_GEN3	/* Enable Freescale ARM DDR3 driver */
-#endif
-#define CONFIG_SYS_FSL_DDR		/* Freescale DDR driver */
-#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
-#define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
-
-#define CONFIG_SYS_FSL_ESDHC_LE
-/* IFC */
-#define CONFIG_SYS_FSL_IFC_LE
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
-/* PCIe */
-#define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
-#define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
-#define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
-#define CONFIG_SYS_PCIE4_ADDR			(CONFIG_SYS_IMMR + 0x2700000)
-#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x1000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x1200000000ULL
-#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x1400000000ULL
-#define CONFIG_SYS_PCIE4_PHYS_ADDR		0x1600000000ULL
-
-/* Cache Coherent Interconnect */
-#define CCI_MN_BASE		0x04000000
-#define CCI_MN_RNF_NODEID_LIST		0x180
-#define CCI_MN_DVM_DOMAIN_CTL		0x200
-#define CCI_MN_DVM_DOMAIN_CTL_SET	0x210
-
-#define CCI_RN_I_0_BASE			(CCI_MN_BASE + 0x800000)
-#define CCI_RN_I_2_BASE			(CCI_MN_BASE + 0x820000)
-#define CCI_RN_I_6_BASE			(CCI_MN_BASE + 0x860000)
-#define CCI_RN_I_12_BASE		(CCI_MN_BASE + 0x8C0000)
-#define CCI_RN_I_16_BASE		(CCI_MN_BASE + 0x900000)
-#define CCI_RN_I_20_BASE		(CCI_MN_BASE + 0x940000)
-
-#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
-#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
-#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
-
-/* Device Configuration */
-#define DCFG_BASE		0x01e00000
-#define DCFG_PORSR1			0x000
-#define DCFG_PORSR1_RCW_SRC		0xff800000
-#define DCFG_PORSR1_RCW_SRC_NOR		0x12f00000
-#define DCFG_RCWSR13			0x130
-#define DCFG_RCWSR13_DSPI		(0 << 8)
-
-#define DCFG_DCSR_BASE		0X700100000ULL
-#define DCFG_DCSR_PORCR1		0x000
-
-/* Supplemental Configuration */
-#define SCFG_BASE		0x01fc0000
-#define SCFG_USB3PRM1CR			0x000
-
-#ifdef CONFIG_LS2085A
-#define CONFIG_MAX_CPUS				16
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
-#define CONFIG_NUM_DDR_CONTROLLERS		3
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SRDS_2
-#else
-#error SoC not defined
-#endif
-
-#ifdef CONFIG_LS2085A
-#define CONFIG_SYS_FSL_ERRATUM_A008336
-#define CONFIG_SYS_FSL_ERRATUM_A008511
-#define CONFIG_SYS_FSL_ERRATUM_A008514
-#define CONFIG_SYS_FSL_ERRATUM_A008585
-#define CONFIG_SYS_FSL_ERRATUM_A008751
-#endif
-
-#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h
deleted file mode 100644
index 2810f3f6d9..0000000000
--- a/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __FSL_SERDES_H
-#define __FSL_SERDES_H
-
-#include <config.h>
-
-#define	SRDS_MAX_LANES	8
-
-enum srds_prtcl {
-	NONE = 0,
-	PCIE1,
-	PCIE2,
-	PCIE3,
-	PCIE4,
-	SATA1,
-	SATA2,
-	XAUI1,
-	XAUI2,
-	XFI1,
-	XFI2,
-	XFI3,
-	XFI4,
-	XFI5,
-	XFI6,
-	XFI7,
-	XFI8,
-	SGMII1,
-	SGMII2,
-	SGMII3,
-	SGMII4,
-	SGMII5,
-	SGMII6,
-	SGMII7,
-	SGMII8,
-	SGMII9,
-	SGMII10,
-	SGMII11,
-	SGMII12,
-	SGMII13,
-	SGMII14,
-	SGMII15,
-	SGMII16,
-	QSGMII_A, /* A indicates MACs 1-4 */
-	QSGMII_B, /* B indicates MACs 5-8 */
-	QSGMII_C, /* C indicates MACs 9-12 */
-	QSGMII_D, /* D indicates MACs 12-16 */
-	SERDES_PRCTL_COUNT
-};
-
-enum srds {
-	FSL_SRDS_1  = 0,
-	FSL_SRDS_2  = 1,
-};
-
-int is_serdes_configured(enum srds_prtcl device);
-void fsl_serdes_init(void);
-
-int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
-enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
-int is_serdes_prtcl_valid(int serdes, u32 prtcl);
-
-#endif /* __FSL_SERDES_H */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/gpio.h b/arch/arm/include/asm/arch-fsl-lsch3/gpio.h
deleted file mode 100644
index f23a78c62d..0000000000
--- a/arch/arm/include/asm/arch-fsl-lsch3/gpio.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright 2014, Freescale Semiconductor
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_ARMV8_FSL_LSCH3_GPIO_H_
-#define _ASM_ARMV8_FSL_LSCH3_GPIO_H_
-#endif	/* _ASM_ARMV8_FSL_LSCH3_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h b/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h
deleted file mode 100644
index 8f005353b4..0000000000
--- a/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- */
-
-#ifndef __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_
-#define __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_
-
-#define I2C_QUIRK_REG	/* enable 8-bit driver */
-
-#endif /* __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/soc.h b/arch/arm/include/asm/arch-fsl-lsch3/soc.h
deleted file mode 100644
index 9a29272072..0000000000
--- a/arch/arm/include/asm/arch-fsl-lsch3/soc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright 2015 Freescale Semiconductor
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-struct cpu_type {
-	char name[15];
-	u32 soc_ver;
-	u32 num_cores;
-};
-
-#define CPU_TYPE_ENTRY(n, v, nc) \
-	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
-
-#define SVR_WO_E		0xFFFFFE
-#define SVR_LS2045		0x870120
-#define SVR_LS2080		0x870110
-#define SVR_LS2085		0x870100
-
-#define SVR_MAJ(svr)		(((svr) >> 4) & 0xf)
-#define SVR_MIN(svr)		(((svr) >> 0) & 0xf)
-#define SVR_SOC_VER(svr)	(((svr) >> 8) & SVR_WO_E)
-#define IS_E_PROCESSOR(svr)	(!((svr >> 8) & 0x1))
-
-void fsl_lsch3_early_init_f(void);
-void cpu_name(char *name);
-
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index bcaf7bf2e4..f066480c0c 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -79,6 +79,21 @@
 #define CONFIG_SYS_PCIE2_PHYS_ADDR		(CONFIG_SYS_PCIE2_PHYS_BASE + \
 						 CONFIG_SYS_PCIE2_VIRT_ADDR)
 
+/* SATA */
+#define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_FSL_ERRATUM_A008407
+
 #ifdef CONFIG_DDR_SPD
 #define CONFIG_SYS_FSL_DDR_BE
 #define CONFIG_VERY_BIG_RAM
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 60aa0d3b6f..09ed9809f1 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -144,6 +144,7 @@ struct ccsr_gur {
 };
 
 #define SCFG_ETSECDMAMCR_LE_BD_FR	0x00000c00
+#define SCFG_SNPCNFGCR_SEC_RD_WR	0xc0000000
 #define SCFG_ETSECCMCR_GE2_CLK125	0x04000000
 #define SCFG_ETSECCMCR_GE0_CLK125	0x00000000
 #define SCFG_ETSECCMCR_GE1_CLK125	0x08000000
@@ -397,4 +398,28 @@ struct ccsr_cci400 {
 	u8 res_e004[0x10000 - 0xe004];
 };
 
+/* AHCI (sata) register map */
+struct ccsr_ahci {
+	u32 res1[0xa4/4];	/* 0x0 - 0xa4 */
+	u32 pcfg;	/* port config */
+	u32 ppcfg;	/* port phy1 config */
+	u32 pp2c;	/* port phy2 config */
+	u32 pp3c;	/* port phy3 config */
+	u32 pp4c;	/* port phy4 config */
+	u32 pp5c;	/* port phy5 config */
+	u32 paxic;	/* port AXI config */
+	u32 axicc;	/* AXI cache control */
+	u32 axipc;	/* AXI PROT control */
+	u32 ptc;	/* port Trans Config */
+	u32 pts;	/* port Trans Status */
+	u32 plc;	/* port link config */
+	u32 plc1;	/* port link config1 */
+	u32 plc2;	/* port link config2 */
+	u32 pls;	/* port link status */
+	u32 pls1;	/* port link status1 */
+	u32 pcmdc;	/* port CMD config */
+	u32 ppcs;	/* port phy control status */
+	u32 pberr;	/* port 0/1 BIST error */
+	u32 cmds;	/* port 0/1 CMD status error */
+};
 #endif	/* __ASM_ARCH_LS102XA_IMMAP_H_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
new file mode 100644
index 0000000000..d097a6a14c
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_SATA_H_
+#define __FSL_SATA_H_
+
+int ls1021a_sata_init(void);
+#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h
index b53f69951a..a921fb6d14 100644
--- a/arch/arm/include/asm/arch-ls102xa/ns_access.h
+++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h
@@ -7,22 +7,6 @@
 #ifndef __FSL_NS_ACCESS_H_
 #define __FSL_NS_ACCESS_H_
 
-enum csu_cslx_access {
-	CSU_NS_SUP_R = 0x08,
-	CSU_NS_SUP_W = 0x80,
-	CSU_NS_SUP_RW = 0x88,
-	CSU_NS_USER_R = 0x04,
-	CSU_NS_USER_W = 0x40,
-	CSU_NS_USER_RW = 0x44,
-	CSU_S_SUP_R = 0x02,
-	CSU_S_SUP_W = 0x20,
-	CSU_S_SUP_RW = 0x22,
-	CSU_S_USER_R = 0x01,
-	CSU_S_USER_W = 0x10,
-	CSU_S_USER_RW = 0x11,
-	CSU_ALL_RW = 0xff,
-};
-
 enum csu_cslx_ind {
 	CSU_CSLX_PCIE2_IO = 0,
 	CSU_CSLX_PCIE1_IO,
@@ -108,11 +92,88 @@ enum csu_cslx_ind {
 	CSU_CSLX_MAX,
 };
 
-struct csu_ns_dev {
-	unsigned long ind;
-	uint32_t val;
+static struct csu_ns_dev ns_dev[] = {
+	{ CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+	{ CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+	{ CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+	{ CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+	{ CSU_CSLX_OCRAM, CSU_ALL_RW },
+	{ CSU_CSLX_GIC, CSU_ALL_RW },
+	{ CSU_CSLX_PCIE1, CSU_ALL_RW },
+	{ CSU_CSLX_OCRAM2, CSU_ALL_RW },
+	{ CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+	{ CSU_CSLX_PCIE2, CSU_ALL_RW },
+	{ CSU_CSLX_SATA, CSU_ALL_RW },
+	{ CSU_CSLX_USB3, CSU_ALL_RW },
+	{ CSU_CSLX_SERDES, CSU_ALL_RW },
+	{ CSU_CSLX_QDMA, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART2, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART1, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART4, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART3, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART6, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART5, CSU_ALL_RW },
+	{ CSU_CSLX_DSPI2, CSU_ALL_RW },
+	{ CSU_CSLX_DSPI1, CSU_ALL_RW },
+	{ CSU_CSLX_QSPI, CSU_ALL_RW },
+	{ CSU_CSLX_ESDHC, CSU_ALL_RW },
+	{ CSU_CSLX_2D_ACE, CSU_ALL_RW },
+	{ CSU_CSLX_IFC, CSU_ALL_RW },
+	{ CSU_CSLX_I2C1, CSU_ALL_RW },
+	{ CSU_CSLX_USB2, CSU_ALL_RW },
+	{ CSU_CSLX_I2C3, CSU_ALL_RW },
+	{ CSU_CSLX_I2C2, CSU_ALL_RW },
+	{ CSU_CSLX_DUART2, CSU_ALL_RW },
+	{ CSU_CSLX_DUART1, CSU_ALL_RW },
+	{ CSU_CSLX_WDT2, CSU_ALL_RW },
+	{ CSU_CSLX_WDT1, CSU_ALL_RW },
+	{ CSU_CSLX_EDMA, CSU_ALL_RW },
+	{ CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+	{ CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+	{ CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+	{ CSU_CSLX_DDR, CSU_ALL_RW },
+	{ CSU_CSLX_QUICC, CSU_ALL_RW },
+	{ CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+	{ CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+	{ CSU_CSLX_SFP, CSU_ALL_RW },
+	{ CSU_CSLX_TMU, CSU_ALL_RW },
+	{ CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+	{ CSU_CSLX_RESERVED0, CSU_ALL_RW },
+	{ CSU_CSLX_ETSEC1, CSU_ALL_RW },
+	{ CSU_CSLX_SEC5_5, CSU_ALL_RW },
+	{ CSU_CSLX_ETSEC3, CSU_ALL_RW },
+	{ CSU_CSLX_ETSEC2, CSU_ALL_RW },
+	{ CSU_CSLX_GPIO2, CSU_ALL_RW },
+	{ CSU_CSLX_GPIO1, CSU_ALL_RW },
+	{ CSU_CSLX_GPIO4, CSU_ALL_RW },
+	{ CSU_CSLX_GPIO3, CSU_ALL_RW },
+	{ CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+	{ CSU_CSLX_CSU, CSU_ALL_RW },
+	{ CSU_CSLX_ASRC, CSU_ALL_RW },
+	{ CSU_CSLX_SPDIF, CSU_ALL_RW },
+	{ CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+	{ CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+	{ CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+	{ CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+	{ CSU_CSLX_SAI2, CSU_ALL_RW },
+	{ CSU_CSLX_SAI1, CSU_ALL_RW },
+	{ CSU_CSLX_SAI4, CSU_ALL_RW },
+	{ CSU_CSLX_SAI3, CSU_ALL_RW },
+	{ CSU_CSLX_FTM2, CSU_ALL_RW },
+	{ CSU_CSLX_FTM1, CSU_ALL_RW },
+	{ CSU_CSLX_FTM4, CSU_ALL_RW },
+	{ CSU_CSLX_FTM3, CSU_ALL_RW },
+	{ CSU_CSLX_FTM6, CSU_ALL_RW },
+	{ CSU_CSLX_FTM5, CSU_ALL_RW },
+	{ CSU_CSLX_FTM8, CSU_ALL_RW },
+	{ CSU_CSLX_FTM7, CSU_ALL_RW },
+	{ CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+	{ CSU_CSLX_EPU, CSU_ALL_RW },
+	{ CSU_CSLX_GDI, CSU_ALL_RW },
+	{ CSU_CSLX_DDI, CSU_ALL_RW },
+	{ CSU_CSLX_RESERVED1, CSU_ALL_RW },
+	{ CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+	{ CSU_CSLX_RESERVED2, CSU_ALL_RW },
 };
 
-void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num);
-
 #endif
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h
index 3ed3801dfe..7ca6dc3de8 100644
--- a/arch/arm/include/asm/arch-stm32f4/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -104,6 +104,7 @@ struct stm32_flash_regs {
 #define STM32_FLASH_CR_STRT		(1 << 16)
 #define STM32_FLASH_CR_LOCK		(1 << 31)
 #define STM32_FLASH_CR_SNB_OFFSET	3
+#define STM32_FLASH_CR_SNB_MASK		(15 << STM32_FLASH_CR_SNB_OFFSET)
 
 enum clock {
 	CLOCK_CORE,
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index f5c90d11dc..f1e95a2a28 100644
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -13,7 +13,7 @@ static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
 {
 }
 
-int zynq_sdhci_init(unsigned long regbase);
+int zynq_sdhci_init(phys_addr_t regbase);
 int zynq_slcr_get_mio_pin_status(const char *periph);
 
 unsigned int zynqmp_get_silicon_version(void);
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 587ee39909..d8d9af45db 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -65,6 +65,7 @@
 /*
  * Section
  */
+#define PMD_SECT_NS		(1 << 5)
 #define PMD_SECT_NON_SHARE	(0 << 8)
 #define PMD_SECT_OUTER_SHARE	(2 << 8)
 #define PMD_SECT_INNER_SHARE	(3 << 8)
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index 9b78043db7..d479a38291 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -190,4 +190,9 @@ found_middle:
 
 #endif /* __KERNEL__ */
 
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/__ffs.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/fls64.h>
+
 #endif /* _ARM_BITOPS_H */
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index a836e9f2ab..1f63127bdc 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -16,6 +16,9 @@
 /*
  * Invalidate L2 Cache using co-proc instruction
  */
+#ifdef CONFIG_SYS_THUMB_BUILD
+void invalidate_l2_cache(void);
+#else
 static inline void invalidate_l2_cache(void)
 {
 	unsigned int val=0;
@@ -24,6 +27,7 @@ static inline void invalidate_l2_cache(void)
 		: : "r" (val) : "cc");
 	isb();
 }
+#endif
 
 void l2_cache_enable(void);
 void l2_cache_disable(void);
diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
index 22fff02778..435fc4521c 100644
--- a/arch/arm/include/asm/config.h
+++ b/arch/arm/include/asm/config.h
@@ -15,14 +15,11 @@
 #define CONFIG_STATIC_RELA
 #endif
 
-#ifdef CONFIG_FSL_LSCH3
-#include <asm/arch-fsl-lsch3/config.h>
-#endif
-
 #if defined(CONFIG_LS102XA) || \
 	defined(CONFIG_CPU_PXA27X) || \
 	defined(CONFIG_CPU_MONAHANS) || \
-	defined(CONFIG_CPU_PXA25X)
+	defined(CONFIG_CPU_PXA25X) || \
+	defined(CONFIG_FSL_LAYERSCAPE)
 #include <asm/arch/config.h>
 #endif
 
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index bfbe0a0988..75773bdbe0 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -46,7 +46,7 @@ static inline void sync(void)
 static inline void *
 map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
 {
-	return (void *)paddr;
+	return (void *)((unsigned long)paddr);
 }
 
 /*
@@ -59,7 +59,7 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
 
 static inline phys_addr_t virt_to_phys(void * vaddr)
 {
-	return (phys_addr_t)(vaddr);
+	return (phys_addr_t)((unsigned long)vaddr);
 }
 
 /*
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index cfc7834ed9..71b31085b4 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -17,6 +17,7 @@
 #define PGTABLE_SIZE	(0x10000)
 /* 2MB granularity */
 #define MMU_SECTION_SHIFT	21
+#define MMU_SECTION_SIZE	(1 << MMU_SECTION_SHIFT)
 
 #ifndef __ASSEMBLY__
 
@@ -278,11 +279,6 @@ enum {
  */
 void mmu_page_table_flush(unsigned long start, unsigned long stop);
 
-#ifdef CONFIG_SYS_NONCACHED_MEMORY
-void noncached_init(void);
-phys_addr_t noncached_alloc(size_t size, size_t align);
-#endif /* CONFIG_SYS_NONCACHED_MEMORY */
-
 #endif /* __ASSEMBLY__ */
 
 #define arch_align_stack(x) (x)
@@ -302,6 +298,11 @@ phys_addr_t noncached_alloc(size_t size, size_t align);
 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 				     enum dcache_option option);
 
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+void noncached_init(void);
+phys_addr_t noncached_alloc(size_t size, size_t align);
+#endif /* CONFIG_SYS_NONCACHED_MEMORY */
+
 #endif /* __ASSEMBLY__ */
 
 #endif
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
index ee77c4179f..388058e04c 100644
--- a/arch/arm/include/asm/types.h
+++ b/arch/arm/include/asm/types.h
@@ -45,12 +45,16 @@ typedef unsigned long long u64;
 #define BITS_PER_LONG 32
 #endif	/* CONFIG_ARM64 */
 
-/* Dma addresses are 32-bits wide.  */
-
+#ifdef CONFIG_PHYS_64BIT
+typedef unsigned long long dma_addr_t;
+typedef unsigned long long phys_addr_t;
+typedef unsigned long long phys_size_t;
+#else
+/* DMA addresses are 32-bits wide */
 typedef u32 dma_addr_t;
-
 typedef unsigned long phys_addr_t;
 typedef unsigned long phys_size_t;
+#endif
 
 #endif /* __KERNEL__ */
 
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 2bdfaba5b7..f3db7b58cb 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -60,3 +60,27 @@ obj-$(CONFIG_DEBUG_LL)	+= debug.o
 ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
 extra-y	+= eabi_compat.o
 endif
+
+# some files can only build in ARM or THUMB2, not THUMB1
+
+ifdef CONFIG_SYS_THUMB_BUILD
+ifndef CONFIG_HAS_THUMB2
+
+# for C files, just apend -marm, which will override previous -mthumb*
+
+CFLAGS_cache.o := -marm
+CFLAGS_cache-cp15.o := -marm
+
+# For .S, drop -mthumb* and other thumb-related options.
+# CFLAGS_REMOVE_* would not have an effet, so AFLAGS_REMOVE_*
+# was implemented and is used here.
+# Also, define ${target}_NO_THUMB_BUILD for these two targets
+# so that the code knows it should not use Thumb.
+
+AFLAGS_REMOVE_memset.o := -mthumb -mthumb-interwork
+AFLAGS_REMOVE_memcpy.o := -mthumb -mthumb-interwork
+AFLAGS_memset.o := -DMEMSET_NO_THUMB_BUILD
+AFLAGS_memcpy.o := -DMEMCPY_NO_THUMB_BUILD
+
+endif
+endif
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index cd13db3440..3bd87105c5 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -88,3 +88,14 @@ phys_addr_t noncached_alloc(size_t size, size_t align)
 	return next;
 }
 #endif /* CONFIG_SYS_NONCACHED_MEMORY */
+
+#if defined(CONFIG_SYS_THUMB_BUILD)
+void invalidate_l2_cache(void)
+{
+	unsigned int val = 0;
+
+	asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
+		: : "r" (val) : "cc");
+	isb();
+}
+#endif
diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index eeaf003529..7d9fc0f9be 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -13,7 +13,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-#ifdef CONFIG_SYS_THUMB_BUILD
+#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD)
 #define W(instr)	instr.w
 #else
 #define W(instr)	instr
@@ -62,7 +62,7 @@
 
 /* Prototype: void *memcpy(void *dest, const void *src, size_t n); */
 	.syntax unified
-#ifdef CONFIG_SYS_THUMB_BUILD
+#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD)
 	.thumb
 	.thumb_func
 #endif
diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S
index 7208f20dda..df053a31d5 100644
--- a/arch/arm/lib/memset.S
+++ b/arch/arm/lib/memset.S
@@ -16,7 +16,7 @@
 	.align	5
 
 	.syntax unified
-#ifdef CONFIG_SYS_THUMB_BUILD
+#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMSET_NO_THUMB_BUILD)
 	.thumb
 	.thumb_func
 #endif
diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c
index c3e964eabc..e32ad90945 100644
--- a/arch/arm/lib/semihosting.c
+++ b/arch/arm/lib/semihosting.c
@@ -31,6 +31,8 @@ static noinline long smh_trap(unsigned int sysnum, void *addr)
 	register long result asm("r0");
 #if defined(CONFIG_ARM64)
 	asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr));
+#elif defined(CONFIG_CPU_V7M)
+	asm volatile ("bkpt #0xAB" : "=r" (result) : "0"(sysnum), "r"(addr));
 #else
 	/* Note - untested placeholder */
 	asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr));
@@ -90,7 +92,7 @@ static long smh_read(long fd, void *memp, size_t len)
 		size_t len;
 	} read;
 
-	debug("%s: fd %ld, memp %p, len %lu\n", __func__, fd, memp, len);
+	debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len);
 
 	read.fd = fd;
 	read.memp = memp;
@@ -104,7 +106,7 @@ static long smh_read(long fd, void *memp, size_t len)
 		 * hard to maintain partial read loops and such, just fail
 		 * with an error message.
 		 */
-		printf("%s: ERROR ret %ld, fd %ld, len %lu memp %p\n",
+		printf("%s: ERROR ret %ld, fd %ld, len %zu memp %p\n",
 		       __func__, ret, fd, len, memp);
 		return -1;
 	}
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 313eb47894..30f2b49b69 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
 ifneq ($(CONFIG_SPL_BUILD),)
 obj-$(CONFIG_AT91SAM9260) += sdram.o spl_at91.o
diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c
index 0bf453eff5..41dbf16afd 100644
--- a/arch/arm/mach-at91/armv7/clock.c
+++ b/arch/arm/mach-at91/armv7/clock.c
@@ -5,11 +5,13 @@
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
+ * Copyright (C) 2015 Wenyou Yang <wenyou.yang@atmel.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_pmc.h>
@@ -173,3 +175,96 @@ void at91_periph_clk_disable(int id)
 
 	writel(regval, &pmc->pcr);
 }
+
+int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	u32 regval, status;
+	u32 timeout = 1000;
+
+	if (id > AT91_PMC_PCR_PID_MASK)
+		return -EINVAL;
+
+	if (div > 0xff)
+		return -EINVAL;
+
+	writel(id, &pmc->pcr);
+	regval = readl(&pmc->pcr);
+	regval &= ~AT91_PMC_PCR_GCKCSS;
+	regval &= ~AT91_PMC_PCR_GCKDIV;
+
+	switch (clk_source) {
+	case GCK_CSS_SLOW_CLK:
+		regval |= AT91_PMC_PCR_GCKCSS_SLOW_CLK;
+		break;
+	case GCK_CSS_MAIN_CLK:
+		regval |= AT91_PMC_PCR_GCKCSS_MAIN_CLK;
+		break;
+	case GCK_CSS_PLLA_CLK:
+		regval |= AT91_PMC_PCR_GCKCSS_PLLA_CLK;
+		break;
+	case GCK_CSS_UPLL_CLK:
+		regval |= AT91_PMC_PCR_GCKCSS_UPLL_CLK;
+		break;
+	case GCK_CSS_MCK_CLK:
+		regval |= AT91_PMC_PCR_GCKCSS_MCK_CLK;
+		break;
+	case GCK_CSS_AUDIO_CLK:
+		regval |= AT91_PMC_PCR_GCKCSS_AUDIO_CLK;
+		break;
+	default:
+		printf("Error GCK clock source selection!\n");
+		return -EINVAL;
+	}
+
+	regval |= AT91_PMC_PCR_CMD_WRITE |
+		  AT91_PMC_PCR_GCKDIV_(div) |
+		  AT91_PMC_PCR_GCKEN;
+
+	writel(regval, &pmc->pcr);
+
+	do {
+		udelay(1);
+		status = readl(&pmc->sr);
+	} while ((!!(--timeout)) && (!(status & AT91_PMC_GCKRDY)));
+
+	if (!timeout)
+		printf("Timeout waiting for GCK ready!\n");
+
+	return 0;
+}
+
+u32 at91_get_periph_generated_clk(u32 id)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	u32 regval, clk_source, div;
+	u32 freq;
+
+	if (id > AT91_PMC_PCR_PID_MASK)
+		return 0;
+
+	writel(id, &pmc->pcr);
+	regval = readl(&pmc->pcr);
+
+	clk_source = regval & AT91_PMC_PCR_GCKCSS;
+	switch (clk_source) {
+	case AT91_PMC_PCR_GCKCSS_SLOW_CLK:
+		freq = CONFIG_SYS_AT91_SLOW_CLOCK;
+		break;
+	case AT91_PMC_PCR_GCKCSS_MAIN_CLK:
+		freq = gd->arch.main_clk_rate_hz;
+		break;
+	case AT91_PMC_PCR_GCKCSS_PLLA_CLK:
+		freq = gd->arch.plla_rate_hz;
+		break;
+	default:
+		printf("Improper GCK clock source selection!\n");
+		freq = 0;
+		break;
+	}
+
+	div = ((regval & AT91_PMC_PCR_GCKDIV) >> AT91_PMC_PCR_GCKDIV_OFFSET);
+	div += 1;
+
+	return freq / div;
+}
diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c
index 8d86f97e3d..7843aed813 100644
--- a/arch/arm/mach-at91/armv7/cpu.c
+++ b/arch/arm/mach-at91/armv7/cpu.c
@@ -12,7 +12,6 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/at91_dbu.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_pit.h>
 #include <asm/arch/at91_gpbr.h>
@@ -65,12 +64,14 @@ void enable_caches(void)
 	dcache_enable();
 }
 
+#define ATMEL_CHIPID_CIDR_VERSION	0x1f
+
 unsigned int get_chip_id(void)
 {
-	return readl(ATMEL_BASE_DBGU + AT91_DBU_CIDR) & ~AT91_DBU_CIDR_MASK;
+	return readl(ATMEL_CHIPID_CIDR) & ~ATMEL_CHIPID_CIDR_VERSION;
 }
 
 unsigned int get_extension_chip_id(void)
 {
-	return readl(ATMEL_BASE_DBGU + AT91_DBU_EXID);
+	return readl(ATMEL_CHIPID_EXID);
 }
diff --git a/arch/arm/mach-at91/include/mach/at91_dbu.h b/arch/arm/mach-at91/include/mach/at91_dbu.h
index 7346fc0569..3181138322 100644
--- a/arch/arm/mach-at91/include/mach/at91_dbu.h
+++ b/arch/arm/mach-at91/include/mach/at91_dbu.h
@@ -35,8 +35,4 @@ typedef struct at91_dbu {
 #define AT91_DBU_CID_ARCH_9xx		0x01900000
 #define AT91_DBU_CID_ARCH_9XExx	0x02900000
 
-#define AT91_DBU_CIDR_MASK		0x1f
-#define AT91_DBU_CIDR			0x40
-#define AT91_DBU_EXID			0x44
-
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 8a3fb942f7..5a51be6288 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -153,8 +153,20 @@ typedef struct at91_pmc {
 #define AT91_PMC_IXR_MOSCSELS		0x00010000
 
 #define AT91_PMC_PCR_PID_MASK		(0x3f)
+#define AT91_PMC_PCR_GCKCSS		(0x7 << 8)
+#define		AT91_PMC_PCR_GCKCSS_SLOW_CLK	(0x0 << 8)
+#define		AT91_PMC_PCR_GCKCSS_MAIN_CLK	(0x1 << 8)
+#define		AT91_PMC_PCR_GCKCSS_PLLA_CLK	(0x2 << 8)
+#define		AT91_PMC_PCR_GCKCSS_UPLL_CLK	(0x3 << 8)
+#define		AT91_PMC_PCR_GCKCSS_MCK_CLK	(0x4 << 8)
+#define		AT91_PMC_PCR_GCKCSS_AUDIO_CLK	(0x5 << 8)
 #define AT91_PMC_PCR_CMD_WRITE		(0x1 << 12)
+#define AT91_PMC_PCR_DIV		(0x3 << 16)
+#define AT91_PMC_PCR_GCKDIV		(0xff << 20)
+#define		AT91_PMC_PCR_GCKDIV_(x)		((x & 0xff) << 20)
+#define		AT91_PMC_PCR_GCKDIV_OFFSET	20
 #define AT91_PMC_PCR_EN			(0x1 << 28)
+#define AT91_PMC_PCR_GCKEN		(0x1 << 29)
 
 #define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
 #define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */
@@ -236,6 +248,7 @@ typedef struct at91_pmc {
 #define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */
 #define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */
 #define		AT91_PMC_PCK3RDY	(1 << 11)		/* Programmable Clock 3 */
+#define		AT91_PMC_GCKRDY		(1 << 24)
 
 #define		AT91_PMC_PROTKEY	0x504d4301	/* Activation Code */
 #endif
diff --git a/arch/arm/mach-at91/include/mach/atmel_sdhci.h b/arch/arm/mach-at91/include/mach/atmel_sdhci.h
new file mode 100644
index 0000000000..9652bc20c8
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/atmel_sdhci.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2015 Atmel Corporation
+ *		      Wenyou.Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ATMEL_SDHCI_H
+#define __ATMEL_SDHCI_H
+
+int atmel_sdhci_init(void *regbase, u32 id);
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/clk.h b/arch/arm/mach-at91/include/mach/clk.h
index 1d45e2dc11..ad839275ec 100644
--- a/arch/arm/mach-at91/include/mach/clk.h
+++ b/arch/arm/mach-at91/include/mach/clk.h
@@ -13,6 +13,13 @@
 #include <asm/arch/at91_pmc.h>
 #include <asm/global_data.h>
 
+#define GCK_CSS_SLOW_CLK	0
+#define GCK_CSS_MAIN_CLK	1
+#define GCK_CSS_PLLA_CLK	2
+#define GCK_CSS_UPLL_CLK	3
+#define GCK_CSS_MCK_CLK		4
+#define GCK_CSS_AUDIO_CLK	5
+
 static inline unsigned long get_cpu_clk_rate(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
@@ -119,4 +126,7 @@ static inline unsigned long get_pit_clk_rate(void)
 int at91_clock_init(unsigned long main_clock);
 void at91_periph_clk_enable(int id);
 void at91_periph_clk_disable(int id);
+int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div);
+u32 at91_get_periph_generated_clk(u32 id);
+
 #endif /* __ASM_ARM_ARCH_CLK_H__ */
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index b749cb3359..33f6c97c11 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -158,6 +158,9 @@
 #define ATMEL_BASE_RTC		0xfffffeb0
 /* Reserved:	0xfffffee0 - 0xffffffff */
 
+#define ATMEL_CHIPID_CIDR	0xffffee40
+#define ATMEL_CHIPID_EXID	0xffffee44
+
 /*
  * Internal Memory.
  */
diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
index 7773ace439..3da8aff27e 100644
--- a/arch/arm/mach-at91/include/mach/sama5d4.h
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h
@@ -144,6 +144,9 @@
 #define ATMEL_BASE_PIOE		0xfc06d000
 #define ATMEL_BASE_AIC		0xfc06e000
 
+#define ATMEL_CHIPID_CIDR	0xfc069040
+#define ATMEL_CHIPID_EXID	0xfc069044
+
 /*
  * Internal Memory.
  */
diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c
index 8ac53353e6..b2fb51d0ac 100644
--- a/arch/arm/mach-at91/spl_atmel.c
+++ b/arch/arm/mach-at91/spl_atmel.c
@@ -98,9 +98,4 @@ void board_init_f(ulong dummy)
 	preloader_console_init();
 
 	mem_init();
-
-	/* Clear the BSS. */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
-	board_init_r(NULL, 0);
 }
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 18eadf545f..3d31f9d524 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -159,8 +159,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 			div = PLL_DIV_1024;
 		else if (proid_is_exynos4412())
 			div = PLL_DIV_65535;
-		else if (proid_is_exynos5250() || proid_is_exynos5420()
-			 || proid_is_exynos5800())
+		else if (proid_is_exynos5250() || proid_is_exynos5420() ||
+			 proid_is_exynos5422())
 			div = PLL_DIV_65536;
 		else
 			return 0;
@@ -346,7 +346,7 @@ static struct clk_bit_info *get_clk_bit_info(int peripheral)
 	int i;
 	struct clk_bit_info *info;
 
-	if (proid_is_exynos5420() || proid_is_exynos5800())
+	if (proid_is_exynos5420() || proid_is_exynos5422())
 		info = exynos542x_bit_info;
 	else
 		info = exynos5_bit_info;
@@ -558,7 +558,7 @@ static unsigned long exynos542x_get_periph_rate(int peripheral)
 unsigned long clock_get_periph_rate(int peripheral)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
+		if (proid_is_exynos5420() || proid_is_exynos5422())
 			return exynos542x_get_periph_rate(peripheral);
 		return exynos5_get_periph_rate(peripheral);
 	} else {
@@ -1576,7 +1576,7 @@ static unsigned long exynos4_get_i2c_clk(void)
 unsigned long get_pll_clk(int pllreg)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
+		if (proid_is_exynos5420() || proid_is_exynos5422())
 			return exynos542x_get_pll_clk(pllreg);
 		return exynos5_get_pll_clk(pllreg);
 	} else if (cpu_is_exynos4()) {
@@ -1692,7 +1692,7 @@ void set_mmc_clk(int dev_index, unsigned int div)
 		div -= 1;
 
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
+		if (proid_is_exynos5420() || proid_is_exynos5422())
 			exynos5420_set_mmc_clk(dev_index, div);
 		else
 			exynos5_set_mmc_clk(dev_index, div);
@@ -1708,7 +1708,7 @@ unsigned long get_lcd_clk(void)
 	} else if (cpu_is_exynos5()) {
 		if (proid_is_exynos5420())
 			return exynos5420_get_lcd_clk();
-		else if (proid_is_exynos5800())
+		else if (proid_is_exynos5422())
 			return exynos5800_get_lcd_clk();
 		else
 			return exynos5_get_lcd_clk();
@@ -1740,7 +1740,7 @@ void set_mipi_clk(void)
 int set_spi_clk(int periph_id, unsigned int rate)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
+		if (proid_is_exynos5420() || proid_is_exynos5422())
 			return exynos5420_set_spi_clk(periph_id, rate);
 		return exynos5_set_spi_clk(periph_id, rate);
 	}
diff --git a/arch/arm/mach-exynos/clock_init_exynos5.c b/arch/arm/mach-exynos/clock_init_exynos5.c
index 0200fd154f..1b7498d9d5 100644
--- a/arch/arm/mach-exynos/clock_init_exynos5.c
+++ b/arch/arm/mach-exynos/clock_init_exynos5.c
@@ -971,7 +971,7 @@ static void exynos5420_system_clock_init(void)
 
 void system_clock_init(void)
 {
-	if (proid_is_exynos5420() || proid_is_exynos5800())
+	if (proid_is_exynos5420() || proid_is_exynos5422())
 		exynos5420_system_clock_init();
 	else
 		exynos5250_system_clock_init();
diff --git a/arch/arm/mach-exynos/common_setup.h b/arch/arm/mach-exynos/common_setup.h
index 67aac2d575..2829fb269e 100644
--- a/arch/arm/mach-exynos/common_setup.h
+++ b/arch/arm/mach-exynos/common_setup.h
@@ -78,7 +78,7 @@ static inline void configure_l2_ctlr(void)
 		CACHE_TAG_RAM_LATENCY_2_CYCLES |
 		CACHE_DATA_RAM_LATENCY_2_CYCLES;
 
-	if (proid_is_exynos5420() || proid_is_exynos5800()) {
+	if (proid_is_exynos5420() || proid_is_exynos5422()) {
 		val |= CACHE_ECC_AND_PARITY |
 			CACHE_TAG_RAM_LATENCY_3_CYCLES |
 			CACHE_DATA_RAM_LATENCY_3_CYCLES;
@@ -97,7 +97,7 @@ static inline void configure_l2_actlr(void)
 {
 	uint32_t val;
 
-	if (proid_is_exynos5420() || proid_is_exynos5800()) {
+	if (proid_is_exynos5420() || proid_is_exynos5422()) {
 		mrc_l2_aux_ctlr(val);
 		val |= CACHE_ENABLE_FORCE_L2_LOGIC |
 			CACHE_DISABLE_CLEAN_EVICT;
diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c
index 7c0b12ae51..25a9df9364 100644
--- a/arch/arm/mach-exynos/dmc_init_ddr3.c
+++ b/arch/arm/mach-exynos/dmc_init_ddr3.c
@@ -20,8 +20,8 @@
 #define TIMEOUT_US		10000
 #define NUM_BYTE_LANES		4
 #define DEFAULT_DQS		8
-#define DEFAULT_DQS_X4		(DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
-				|| (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)
+#define DEFAULT_DQS_X4		((DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
+				|| (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0))
 
 #ifdef CONFIG_EXYNOS5250
 static void reset_phy_ctrl(void)
@@ -856,10 +856,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
 	 */
 	val = readl(&drex0->concontrol);
 	val |= CONCONTROL_UPDATE_MODE;
-	writel(val , &drex0->concontrol);
+	writel(val, &drex0->concontrol);
 	val = readl(&drex1->concontrol);
 	val |= CONCONTROL_UPDATE_MODE;
-	writel(val , &drex1->concontrol);
+	writel(val, &drex1->concontrol);
 
 	return 0;
 }
diff --git a/arch/arm/mach-exynos/include/mach/adc.h b/arch/arm/mach-exynos/include/mach/adc.h
index a0e26d7052..9af51ab381 100644
--- a/arch/arm/mach-exynos/include/mach/adc.h
+++ b/arch/arm/mach-exynos/include/mach/adc.h
@@ -9,6 +9,39 @@
 #ifndef __ASM_ARM_ARCH_ADC_H_
 #define __ASM_ARM_ARCH_ADC_H_
 
+#define ADC_V2_CON1_SOFT_RESET		(0x2 << 1)
+#define ADC_V2_CON1_STC_EN		0x1
+
+#define ADC_V2_CON2_OSEL(x)		(((x) & 0x1) << 10)
+#define OSEL_2S				0x0
+#define OSEL_BINARY			0x1
+#define ADC_V2_CON2_ESEL(x)		(((x) & 0x1) << 9)
+#define ESEL_ADC_EVAL_TIME_40CLK	0x0
+#define ESEL_ADC_EVAL_TIME_20CLK	0x1
+#define ADC_V2_CON2_HIGHF(x)		(((x) & 0x1) << 8)
+#define HIGHF_CONV_RATE_30KSPS		0x0
+#define HIGHF_CONV_RATE_600KSPS		0x1
+#define ADC_V2_CON2_C_TIME(x)		(((x) & 0x7) << 4)
+#define ADC_V2_CON2_CHAN_SEL_MASK	0xf
+#define ADC_V2_CON2_CHAN_SEL(x)		((x) & ADC_V2_CON2_CHAN_SEL_MASK)
+
+#define ADC_V2_GET_STATUS_FLAG(x)	(((x) >> 2) & 0x1)
+#define FLAG_CONV_END			0x1
+
+#define ADC_V2_INT_DISABLE		0x0
+#define ADC_V2_INT_ENABLE		0x1
+#define INT_NOT_GENERATED		0x0
+#define INT_GENERATED			0x1
+
+#define ADC_V2_VERSION			0x80000008
+
+#define ADC_V2_MAX_CHANNEL		9
+
+/* For default 8 time convertion with sample rate 600 kSPS - 15us timeout */
+#define ADC_V2_CONV_TIMEOUT_US		15
+
+#define ADC_V2_DAT_MASK			0xfff
+
 #ifndef __ASSEMBLY__
 struct s5p_adc {
 	unsigned int adccon;
@@ -21,6 +54,17 @@ struct s5p_adc {
 	unsigned int adcmux;
 	unsigned int adcclrintpndnup;
 };
+
+struct exynos_adc_v2 {
+	unsigned int con1;
+	unsigned int con2;
+	unsigned int status;
+	unsigned int dat;
+	unsigned int int_en;
+	unsigned int int_status;
+	unsigned int reserved[2];
+	unsigned int version;
+};
 #endif
 
 #endif /* __ASM_ARM_ARCH_ADC_H_ */
diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h
index cb3d2cc06f..14a1692467 100644
--- a/arch/arm/mach-exynos/include/mach/cpu.h
+++ b/arch/arm/mach-exynos/include/mach/cpu.h
@@ -237,7 +237,7 @@ static inline void s5p_set_cpu_id(void)
 		 * Exynos5800 is a variant of Exynos5420
 		 * and has product id 0x5422
 		 */
-		s5p_cpu_id = 0x5800;
+		s5p_cpu_id = 0x5422;
 		break;
 	}
 }
@@ -267,7 +267,7 @@ IS_EXYNOS_TYPE(exynos4210, 0x4210)
 IS_EXYNOS_TYPE(exynos4412, 0x4412)
 IS_EXYNOS_TYPE(exynos5250, 0x5250)
 IS_EXYNOS_TYPE(exynos5420, 0x5420)
-IS_EXYNOS_TYPE(exynos5800, 0x5800)
+IS_EXYNOS_TYPE(exynos5422, 0x5422)
 
 #define SAMSUNG_BASE(device, base)				\
 static inline unsigned int __attribute__((no_instrument_function)) \
@@ -278,7 +278,7 @@ static inline unsigned int __attribute__((no_instrument_function)) \
 			return EXYNOS4X12_##base;		\
 		return EXYNOS4_##base;				\
 	} else if (cpu_is_exynos5()) {				\
-		if (proid_is_exynos5420() || proid_is_exynos5800())	\
+		if (proid_is_exynos5420() || proid_is_exynos5422())	\
 			return EXYNOS5420_##base;		\
 		return EXYNOS5_##base;				\
 	}							\
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index 9699954a7d..7fc8e61f9c 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -1398,7 +1398,7 @@ static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = {
 static inline struct gpio_info *get_gpio_data(void)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
+		if (proid_is_exynos5420() || proid_is_exynos5422())
 			return exynos5420_gpio_data;
 		else
 			return exynos5_gpio_data;
@@ -1415,7 +1415,7 @@ static inline struct gpio_info *get_gpio_data(void)
 static inline unsigned int get_bank_num(void)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
+		if (proid_is_exynos5420() || proid_is_exynos5422())
 			return EXYNOS5420_GPIO_NUM_PARTS;
 		else
 			return EXYNOS5_GPIO_NUM_PARTS;
diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c
index 179b29449e..12eb79cb0c 100644
--- a/arch/arm/mach-exynos/pinmux.c
+++ b/arch/arm/mach-exynos/pinmux.c
@@ -737,10 +737,10 @@ static int exynos4x12_mmc_config(int peripheral, int flags)
 		return -1;
 	}
 	for (i = start; i < (start + 7); i++) {
+		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
 		if (i == (start + 2))
 			continue;
 		gpio_cfg_pin(i,  func);
-		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
 		gpio_set_drv(i, S5P_GPIO_DRV_4X);
 	}
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
@@ -858,7 +858,7 @@ static int exynos4x12_pinmux_config(int peripheral, int flags)
 int exynos_pinmux_config(int peripheral, int flags)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
+		if (proid_is_exynos5420() || proid_is_exynos5422())
 			return exynos5420_pinmux_config(peripheral, flags);
 		else if (proid_is_exynos5250())
 			return exynos5_pinmux_config(peripheral, flags);
diff --git a/arch/arm/mach-exynos/power.c b/arch/arm/mach-exynos/power.c
index 1b12051656..cd2d6618ac 100644
--- a/arch/arm/mach-exynos/power.c
+++ b/arch/arm/mach-exynos/power.c
@@ -125,7 +125,7 @@ static void exynos5420_set_usbdev_phy_ctrl(unsigned int enable)
 void set_usbdrd_phy_ctrl(unsigned int enable)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
+		if (proid_is_exynos5420() || proid_is_exynos5422())
 			exynos5420_set_usbdev_phy_ctrl(enable);
 		else
 			exynos5_set_usbdrd_phy_ctrl(enable);
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index aab5d19b5f..f7737bfb22 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -4,6 +4,9 @@ choice
 	prompt "Marvell Kirkwood board select"
 	optional
 
+config TARGET_OPENRD
+	bool "Marvell OpenRD Board"
+
 config TARGET_DREAMPLUG
 	bool "DreamPlug Board"
 
@@ -51,6 +54,7 @@ endchoice
 config SYS_SOC
 	default "kirkwood"
 
+source "board/Marvell/openrd/Kconfig"
 source "board/Marvell/dreamplug/Kconfig"
 source "board/Marvell/guruplug/Kconfig"
 source "board/Marvell/sheevaplug/Kconfig"
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index df4756e4bd..5abcf70b28 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -9,3 +9,9 @@
 obj-y	= cpu.o
 obj-y	+= cache.o
 obj-y	+= mpp.o
+
+# cpu.o and cache.o contain CP15 instructions which cannot be run in
+# Thumb state, so build them for ARM state even with CONFIG_SYS_THUMB_BUILD
+
+CFLAGS_cpu.o := -marm
+CFLAGS_cache.o := -marm
diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c
index 771cce6fa3..346278e1be 100644
--- a/arch/arm/mach-mvebu/mbus.c
+++ b/arch/arm/mach-mvebu/mbus.c
@@ -52,7 +52,7 @@
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
-#include <linux/compat.h>
+#include <linux/log2.h>
 #include <linux/mbus.h>
 
 /* DDR target is the same on all platforms */
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 546ebcb52e..33dcad40f2 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -16,3 +16,13 @@ obj-y	+= timer.o
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
 obj-y	+= lowlevel_init.o
 endif
+
+# some files can only build in ARM or THUMB2, not THUMB1
+
+ifdef CONFIG_SYS_THUMB_BUILD
+ifndef CONFIG_HAS_THUMB2
+
+CFLAGS_cpu.o := -marm
+
+endif
+endif
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 8e59578f37..666a2ef8df 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -69,9 +69,9 @@ struct socfpga_reset_manager {
 #define RSTMGR_UART0		RSTMGR_DEFINE(1, 16)
 #define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 18)
 #define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 19)
-#define RSTMGR_QSPI		RSTMGR_DEFINE(0, 5)
-#define RSTMGR_SDMMC		RSTMGR_DEFINE(0, 22)
-#define RSTMGR_DMA		RSTMGR_DEFINE(0, 28)
+#define RSTMGR_QSPI		RSTMGR_DEFINE(1, 5)
+#define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 22)
+#define RSTMGR_DMA		RSTMGR_DEFINE(1, 28)
 #define RSTMGR_SDR		RSTMGR_DEFINE(1, 29)
 
 /* Create a human-readable reference to SoCFPGA reset. */
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 75924ad848..98431a91f8 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
 obj-$(CONFIG_PWM_TEGRA) += pwm.o
 endif
 
+obj-$(CONFIG_ARM64) += arm64-mmu.o
 obj-y += ap.o
 obj-y += board.o board2.o
 obj-y += cache.o
diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c
new file mode 100644
index 0000000000..c2276523cb
--- /dev/null
+++ b/arch/arm/mach-tegra/arm64-mmu.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2014 - 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ * (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c)
+ *
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SECTION_SHIFT_L1	30UL
+#define SECTION_SHIFT_L2	21UL
+#define BLOCK_SIZE_L0		0x8000000000UL
+#define BLOCK_SIZE_L1		(1 << SECTION_SHIFT_L1)
+#define BLOCK_SIZE_L2		(1 << SECTION_SHIFT_L2)
+
+#define TCR_TG1_4K		(1 << 31)
+#define TCR_EPD1_DISABLE	(1 << 23)
+#define TEGRA_VA_BITS		40
+#define TEGRA_TCR		TCR_TG1_4K | \
+				TCR_EPD1_DISABLE | \
+				TCR_SHARED_OUTER | \
+				TCR_SHARED_INNER | \
+				TCR_IRGN_WBWA | \
+				TCR_ORGN_WBWA | \
+				TCR_T0SZ(TEGRA_VA_BITS)
+
+#define MEMORY_ATTR	PMD_SECT_AF | PMD_SECT_INNER_SHARE |	\
+			PMD_ATTRINDX(MT_NORMAL) |	\
+			PMD_TYPE_SECT
+#define DEVICE_ATTR	PMD_SECT_AF | PMD_SECT_PXN |	\
+			PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) |	\
+			PMD_TYPE_SECT
+
+/* 4K size is required to place 512 entries in each level */
+#define TLB_TABLE_SIZE	0x1000
+
+/*
+ * This mmu table looks as below
+ * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0
+ * and other Level1 Table1.
+ * Level1 Table0 contains entries for each 1GB from 0 to 511GB.
+ * Level1 Table1 contains entries for each 1GB from 512GB to 1TB.
+ * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains
+ * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively.
+ */
+void mmu_setup(void)
+{
+	int el;
+	u64 i, section_l1t0, section_l1t1;
+	u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3;
+	u64 *level0_table = (u64 *)gd->arch.tlb_addr;
+	u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE);
+	u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE));
+	u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE));
+	u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE));
+	u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE));
+	u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE));
+
+	/* Invalidate all table entries */
+	memset(level0_table, 0, PGTABLE_SIZE);
+
+	level0_table[0] =
+		(u64)level1_table_0 | PMD_TYPE_TABLE;
+	level0_table[1] =
+		(u64)level1_table_1 | PMD_TYPE_TABLE;
+
+	/*
+	 * set level 1 table 0, covering 0 to 512GB
+	 * set level 1 table 1, covering 512GB to 1TB
+	 */
+	section_l1t0 = 0;
+	section_l1t1 = BLOCK_SIZE_L0;
+
+	for (i = 0; i < 512; i++) {
+		level1_table_0[i] = section_l1t0;
+		if (i >= 4)
+			level1_table_0[i] |= MEMORY_ATTR;
+		level1_table_1[i] = section_l1t1;
+		level1_table_1[i] |= MEMORY_ATTR;
+		section_l1t0 += BLOCK_SIZE_L1;
+		section_l1t1 += BLOCK_SIZE_L1;
+	}
+
+	level1_table_0[0] =
+		(u64)level2_table_0 | PMD_TYPE_TABLE;
+	level1_table_0[1] =
+		(u64)level2_table_1 | PMD_TYPE_TABLE;
+	level1_table_0[2] =
+		(u64)level2_table_2 | PMD_TYPE_TABLE;
+	level1_table_0[3] =
+		(u64)level2_table_3 | PMD_TYPE_TABLE;
+
+	section_l2t0 = 0;
+	section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */
+	section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */
+	section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */
+
+	for (i = 0; i < 512; i++) {
+		level2_table_0[i] = section_l2t0 | DEVICE_ATTR;
+		level2_table_1[i] = section_l2t1 | DEVICE_ATTR;
+		level2_table_2[i] = section_l2t2 | MEMORY_ATTR;
+		level2_table_3[i] = section_l2t3 | MEMORY_ATTR;
+		section_l2t0 += BLOCK_SIZE_L2;
+		section_l2t1 += BLOCK_SIZE_L2;
+		section_l2t2 += BLOCK_SIZE_L2;
+		section_l2t3 += BLOCK_SIZE_L2;
+	}
+
+	/* flush new MMU table */
+	flush_dcache_range(gd->arch.tlb_addr,
+			   gd->arch.tlb_addr + gd->arch.tlb_size);
+
+	/* point TTBR to the new table */
+	el = current_el();
+	set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
+			  TEGRA_TCR, MEMORY_ATTRIBUTES);
+
+	set_sctlr(get_sctlr() | CR_M);
+}
+
+u64 *arch_get_page_table(void)
+{
+	return (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE));
+}
diff --git a/arch/arm/mach-tegra/tegra114/Makefile b/arch/arm/mach-tegra/tegra114/Makefile
index 7489f5f146..ea7f7b717a 100644
--- a/arch/arm/mach-tegra/tegra114/Makefile
+++ b/arch/arm/mach-tegra/tegra114/Makefile
@@ -1,17 +1,7 @@
 #
 # Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
 #
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# SPDX-License-Identifier:	GPL-2.0
 #
 
 obj-$(CONFIG_SPL_BUILD) += cpu.o
diff --git a/arch/arm/mach-tegra/tegra30/Makefile b/arch/arm/mach-tegra/tegra30/Makefile
index bc250deba8..d3d3b6e7c4 100644
--- a/arch/arm/mach-tegra/tegra30/Makefile
+++ b/arch/arm/mach-tegra/tegra30/Makefile
@@ -1,17 +1,7 @@
 #
 # Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
 #
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# SPDX-License-Identifier:	GPL-2.0
 #
 
 obj-$(CONFIG_SPL_BUILD) += cpu.o
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 22ab798b96..9e6ac3a0ff 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -3,12 +3,8 @@ if ARCH_UNIPHIER
 config SYS_CONFIG_NAME
 	default "uniphier"
 
-config UNIPHIER_SMP
-	bool
-
 config ARCH_UNIPHIER_PH1_SLD3
 	bool "UniPhier PH1-sLD3 SoC"
-	select UNIPHIER_SMP
 	help
 	  This enables support for UniPhier PH1-sLD3 SoC.
 
@@ -20,7 +16,6 @@ config ARCH_UNIPHIER_PH1_LD4
 
 config ARCH_UNIPHIER_PH1_PRO4
 	bool "UniPhier PH1-Pro4 SoC"
-	select UNIPHIER_SMP
 	depends on !ARCH_UNIPHIER_PH1_SLD3 && \
 		   !ARCH_UNIPHIER_PH1_LD4 && \
 		   !ARCH_UNIPHIER_PH1_SLD8
@@ -35,7 +30,6 @@ config ARCH_UNIPHIER_PH1_SLD8
 
 config ARCH_UNIPHIER_PH1_PRO5
 	bool "UniPhier PH1-Pro5 SoC"
-	select UNIPHIER_SMP
 	depends on !ARCH_UNIPHIER_PH1_SLD3 && \
 		   !ARCH_UNIPHIER_PH1_LD4 && \
 		   !ARCH_UNIPHIER_PH1_SLD8
@@ -44,7 +38,6 @@ config ARCH_UNIPHIER_PH1_PRO5
 
 config ARCH_UNIPHIER_PROXSTREAM2
 	bool "UniPhier ProXstream2 SoC"
-	select UNIPHIER_SMP
 	depends on !ARCH_UNIPHIER_PH1_SLD3 && \
 		   !ARCH_UNIPHIER_PH1_LD4 && \
 		   !ARCH_UNIPHIER_PH1_SLD8
@@ -53,7 +46,6 @@ config ARCH_UNIPHIER_PROXSTREAM2
 
 config ARCH_UNIPHIER_PH1_LD6B
 	bool "UniPhier PH1-LD6b SoC"
-	select UNIPHIER_SMP
 	depends on !ARCH_UNIPHIER_PH1_SLD3 && \
 		   !ARCH_UNIPHIER_PH1_LD4 && \
 		   !ARCH_UNIPHIER_PH1_SLD8
diff --git a/arch/arm/mach-uniphier/bcu/Makefile b/arch/arm/mach-uniphier/bcu/Makefile
index 5b95bdad95..b8b0323cd2 100644
--- a/arch/arm/mach-uniphier/bcu/Makefile
+++ b/arch/arm/mach-uniphier/bcu/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3)	+= bcu-ph1-sld3.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= bcu-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= bcu-ph1-ld4.o
diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile
index 30c8874905..0797d6e615 100644
--- a/arch/arm/mach-uniphier/boot-mode/Makefile
+++ b/arch/arm/mach-uniphier/boot-mode/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 obj-y					+= boot-mode.o
 
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3)	+= boot-mode-ph1-sld3.o
diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile
index 4f397b986b..bc0f27c398 100644
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3)	+= clk-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= clk-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= clk-ph1-pro4.o
diff --git a/arch/arm/mach-uniphier/ddrphy/Makefile b/arch/arm/mach-uniphier/ddrphy/Makefile
index e2d109df57..d0f4bd3519 100644
--- a/arch/arm/mach-uniphier/ddrphy/Makefile
+++ b/arch/arm/mach-uniphier/ddrphy/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= ddrphy-training.o ddrphy-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= ddrphy-training.o ddrphy-ph1-pro4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= ddrphy-training.o ddrphy-ph1-sld8.o
diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile
index 393ea96f90..3e1e1b2bc8 100644
--- a/arch/arm/mach-uniphier/early-clk/Makefile
+++ b/arch/arm/mach-uniphier/early-clk/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3)	+= early-clk-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= early-clk-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= early-clk-ph1-ld4.o
diff --git a/arch/arm/mach-uniphier/early-pinctrl/Makefile b/arch/arm/mach-uniphier/early-pinctrl/Makefile
index e497d28f79..3be71fbf07 100644
--- a/arch/arm/mach-uniphier/early-pinctrl/Makefile
+++ b/arch/arm/mach-uniphier/early-pinctrl/Makefile
@@ -1 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3)	+= early-pinctrl-ph1-sld3.o
diff --git a/arch/arm/mach-uniphier/init/Makefile b/arch/arm/mach-uniphier/init/Makefile
index 98833b55de..ef80953623 100644
--- a/arch/arm/mach-uniphier/init/Makefile
+++ b/arch/arm/mach-uniphier/init/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 obj-y					+= init.o
 
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3)	+= init-ph1-sld3.o
diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S
index 66cad42dde..5936045e86 100644
--- a/arch/arm/mach-uniphier/lowlevel_init.S
+++ b/arch/arm/mach-uniphier/lowlevel_init.S
@@ -44,59 +44,6 @@ ENTRY(lowlevel_init)
 
 	bl	enable_mmu
 
-#ifdef CONFIG_UNIPHIER_SMP
-secondary_startup:
-	/*
-	 * Entry point for secondary CPUs
-	 *
-	 * The Boot ROM has already enabled MMU for the secondary CPUs as well
-	 * as for the primary one.  The MMU table embedded in the Boot ROM
-	 * prohibits the DRAM access, so it is impossible to bring the
-	 * secondary CPUs into DRAM directly.  They must jump here into SPL,
-	 * which is run on L2 cache.
-	 *
-	 * Boot Sequence
-	 *  [primary CPU]                    [secondary CPUs]
-	 *  start from Boot ROM             start from Boot ROM
-	 *     jump to SPL                    sleep in Boot ROM
-	 *  kick secondaries   ---(sev)--->    jump to SPL
-	 *  jump to U-Boot main               sleep in SPL
-	 *  jump to Linux
-	 *  kick secondaries   ---(sev)--->    jump to Linux
-	 */
-
-	/* branch by CPU ID */
-	mrc	p15, 0, r0, c0, c0, 5	@ MPIDR (Multiprocessor Affinity Register)
-	and  	r0, r0, #0x3
-	cmp	r0, #0x0
-	beq	primary_cpu
-	/* only for secondary CPUs */
-	ldr	r1, =ROM_BOOT_ROMRSV2	@ The last data access to L2 cache
-	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
-	orr	r0, r0, #CR_I		@ Enable ICache
-	bic	r0, r0, #(CR_C | CR_M)	@ MMU and Dcache must be disabled
-	mcr	p15, 0, r0, c1, c0, 0	@ before jumping to Linux
-	mov	r0, #0
-	str	r0, [r1]
-	b	1f
-	/*
-	 * L2 cache is shared among all the CPUs and it might be disabled by
-	 * the primary one.  Before that, the following 5 lines must be cached
-	 * on the Icaches of the secondary CPUs.
-	 */
-0:	wfe				@ kicked by Linux
-1:	ldr	r0, [r1]
-	cmp	r0, #0
-	bxne	r0			@ r0: Linux entry for secondary CPUs
-	b	0b
-primary_cpu:
-	ldr	r1, =ROM_BOOT_ROMRSV2
-	ldr	r0, =secondary_startup
-	str	r0, [r1]
-	ldr	r0, [r1]		@ make sure str is complete before sev
-	sev				@ kick the secondary CPU
-#endif
-
 	bl	setup_init_ram		@ RAM area for temporary stack pointer
 
 	mov	lr, r8			@ restore link
diff --git a/arch/arm/mach-uniphier/memconf/Makefile b/arch/arm/mach-uniphier/memconf/Makefile
index 42057a2077..a152f61266 100644
--- a/arch/arm/mach-uniphier/memconf/Makefile
+++ b/arch/arm/mach-uniphier/memconf/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 obj-y					+= memconf.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3)	+= memconf-ph1-sld3.o
 obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)	+= memconf-proxstream2.o
diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile
index 85175955d3..80a9cdaa80 100644
--- a/arch/arm/mach-uniphier/pinctrl/Makefile
+++ b/arch/arm/mach-uniphier/pinctrl/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3)	+= pinctrl-ph1-sld3.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= pinctrl-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= pinctrl-ph1-pro4.o
diff --git a/arch/arm/mach-uniphier/pll/Makefile b/arch/arm/mach-uniphier/pll/Makefile
index d33f99e446..ca88521a1d 100644
--- a/arch/arm/mach-uniphier/pll/Makefile
+++ b/arch/arm/mach-uniphier/pll/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3)	+= pll-init-ph1-sld3.o \
 					   pll-spectrum-ph1-sld3.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= pll-init-ph1-ld4.o \
diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile
index db622d2034..57eb44b646 100644
--- a/arch/arm/mach-uniphier/sbc/Makefile
+++ b/arch/arm/mach-uniphier/sbc/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3)	+= sbc-ph1-sld3.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= sbc-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= sbc-ph1-pro4.o
diff --git a/arch/arm/mach-uniphier/umc/Makefile b/arch/arm/mach-uniphier/umc/Makefile
index dd35e77dab..89b2dec118 100644
--- a/arch/arm/mach-uniphier/umc/Makefile
+++ b/arch/arm/mach-uniphier/umc/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= umc-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= umc-ph1-pro4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= umc-ph1-sld8.o
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 7a1aec45e7..afe6cc3edd 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -21,13 +21,6 @@ config TARGET_ZYNQ_MICROZED
 config TARGET_ZYNQ_PICOZED
 	bool "Zynq PicoZed"
 
-config TARGET_ZYNQ_ZC70X
-	bool "Zynq ZC702/ZC706 Board (deprecated)"
-	select ZYNQ_CUSTOM_INIT
-	help
-	  This option is deprecated.  Use TARGET_ZYNQ_ZC702
-	  or TARGET_ZYNQ_706.
-
 config TARGET_ZYNQ_ZC702
 	bool "Zynq ZC702 Board"
 
@@ -57,8 +50,7 @@ config SYS_CONFIG_NAME
 	default "zynq_zed" if TARGET_ZYNQ_ZED
 	default "zynq_microzed" if TARGET_ZYNQ_MICROZED
 	default "zynq_picozed" if TARGET_ZYNQ_PICOZED
-	default "zynq_zc70x" if TARGET_ZYNQ_ZC702 || TARGET_ZYNQ_ZC706 \
-			        || TARGET_ZYNQ_ZC70X
+	default "zynq_zc70x" if TARGET_ZYNQ_ZC702 || TARGET_ZYNQ_ZC706
 	default "zynq_zc770" if TARGET_ZYNQ_ZC770
 	default "zynq_zybo" if TARGET_ZYNQ_ZYBO
 
diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c
index 7bdac3b12d..723019d252 100644
--- a/arch/arm/mach-zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c
@@ -4,11 +4,12 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include <debug_uart.h>
 #include <spl.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
 #include <asm/spl.h>
+#include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -17,11 +18,12 @@ void board_init_f(ulong dummy)
 {
 	ps7_init();
 
-	/* Clear the BSS. */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
 	arch_cpu_init();
-	board_init_r(NULL, 0);
+	/*
+	 * The debug UART can be used from this point:
+	 * debug_uart_init();
+	 * printch('x');
+	 */
 }
 
 #ifdef CONFIG_SPL_BOARD_INIT
diff --git a/arch/arm/mach-zynq/u-boot-spl.lds b/arch/arm/mach-zynq/u-boot-spl.lds
index 0f2f756f83..ecdf6a031e 100644
--- a/arch/arm/mach-zynq/u-boot-spl.lds
+++ b/arch/arm/mach-zynq/u-boot-spl.lds
@@ -38,10 +38,18 @@ SECTIONS
 	} > .sram
 
 	. = ALIGN(4);
+#ifdef CONFIG_SPL_DM
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list_*_driver_*)));
+		KEEP(*(SORT(.u_boot_list_*_uclass_*)));
+	} > .sram
+
+	. = ALIGN(4);
+#endif
 
 	. = .;
 
-	__image_copy_end = .;
+	_image_binary_end = .;
 
 	_end = .;
 
diff --git a/arch/arm/thumb1/include/asm/proc-armv/system.h b/arch/arm/thumb1/include/asm/proc-armv/system.h
new file mode 100644
index 0000000000..7dfbf3d33d
--- /dev/null
+++ b/arch/arm/thumb1/include/asm/proc-armv/system.h
@@ -0,0 +1,69 @@
+/*
+ *  Thumb-1 drop-in for the linux/include/asm-arm/proc-armv/system.h
+ *
+ *  (C) Copyright 2015
+ *  Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * The original file does not build in Thumb mode. However, in U-Boot
+ * we don't use interrupt context, so we can redefine these as empty
+ * memory barriers, which makes Thumb-1 compiler happy.
+ *
+ *  SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Use the same macro name as linux/include/asm-arm/proc-armv/system.h
+ * here, so that if the original ever gets included after us, it won't
+ * try to re-redefine anything.
+ */
+
+#ifndef __ASM_PROC_SYSTEM_H
+#define __ASM_PROC_SYSTEM_H
+
+/*
+ * Redefine all original macros with static inline functions containing
+ * a simple memory barrier, so that they produce the same instruction
+ * ordering constraints as their original counterparts.
+ * We use static inline functions rather than macros so that we can tell
+ * the compiler to not complain about unused arguments.
+ */
+
+static inline void local_irq_save(
+	unsigned long flags __attribute__((unused)))
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
+static inline void local_irq_enable(void)
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
+static inline void local_irq_disable(void)
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
+static inline void __stf(void)
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
+static inline void __clf(void)
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
+static inline void local_save_flags(
+	unsigned long flags __attribute__((unused)))
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
+static inline void local_irq_restore(
+	unsigned long flags __attribute__((unused)))
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
+#endif /*  __ASM_PROC_SYSTEM_H */
diff --git a/arch/avr32/include/asm/bitops.h b/arch/avr32/include/asm/bitops.h
index 0ec678487d..0d425c20f9 100644
--- a/arch/avr32/include/asm/bitops.h
+++ b/arch/avr32/include/asm/bitops.h
@@ -6,4 +6,9 @@
 #ifndef __ASM_AVR32_BITOPS_H
 #define __ASM_AVR32_BITOPS_H
 
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
 #endif /* __ASM_AVR32_BITOPS_H */
diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile
index cfbcd3124f..7cd0bbf24e 100644
--- a/arch/blackfin/cpu/Makefile
+++ b/arch/blackfin/cpu/Makefile
@@ -6,7 +6,7 @@
 # (C) Copyright 2000-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
-# Licensed under the GPL-2 or later.
+# SPDX-License-Identifier:	GPL-2.0+
 #
 
 extra-y := init.elf
diff --git a/arch/blackfin/cpu/jtag-console.c b/arch/blackfin/cpu/jtag-console.c
index b0abeda90a..29e7a441bc 100644
--- a/arch/blackfin/cpu/jtag-console.c
+++ b/arch/blackfin/cpu/jtag-console.c
@@ -183,7 +183,7 @@ int drv_jtag_console_init(void)
 
 	memset(&dev, 0x00, sizeof(dev));
 	strcpy(dev.name, "jtag");
-	dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+	dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
 	dev.putc = jtag_putc;
 	dev.puts = jtag_puts;
 	dev.tstc = jtag_tstc;
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
index cd7e356459..6cde6dbfde 100644
--- a/arch/blackfin/include/asm/bitops.h
+++ b/arch/blackfin/include/asm/bitops.h
@@ -15,6 +15,10 @@
 
 #include <asm/byteorder.h>
 #include <asm/system.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
 
 #ifdef __KERNEL__
 /*
diff --git a/arch/blackfin/include/asm/delay.h b/arch/blackfin/include/asm/delay.h
index 97401a7ce2..f146efd6e7 100644
--- a/arch/blackfin/include/asm/delay.h
+++ b/arch/blackfin/include/asm/delay.h
@@ -16,7 +16,7 @@
  * Delay routines, using a pre-computed "loops_per_second" value.
  */
 
-extern __inline__ void __delay(unsigned long loops)
+static __inline__ void __delay(unsigned long loops)
 {
 	__asm__ __volatile__("1:\t%0 += -1;\n\t"
 			     "cc = %0 == 0;\n\t"
@@ -31,7 +31,7 @@ extern __inline__ void __delay(unsigned long loops)
  * first constant multiplications gets optimized away if the delay is
  * a constant)
  */
-extern __inline__ void __udelay(unsigned long usecs)
+static __inline__ void __udelay(unsigned long usecs)
 {
 	__delay(usecs);
 }
diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h
index f9c434b4a3..4a3f6b97ad 100644
--- a/arch/m68k/include/asm/bitops.h
+++ b/arch/m68k/include/asm/bitops.h
@@ -6,25 +6,28 @@
 #define _M68K_BITOPS_H
 
 #include <asm/byteorder.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
 
 extern void set_bit(int nr, volatile void *addr);
 extern void clear_bit(int nr, volatile void *addr);
 extern void change_bit(int nr, volatile void *addr);
-extern int test_and_set_bit(int nr, volatile void *addr);
 extern int test_and_clear_bit(int nr, volatile void *addr);
 extern int test_and_change_bit(int nr, volatile void *addr);
 
 #ifdef __KERNEL__
 
 
-extern inline int test_bit(int nr, __const__ volatile void *addr)
+static inline int test_bit(int nr, __const__ volatile void *addr)
 {
 	__const__ unsigned int *p = (__const__ unsigned int *) addr;
 
 	return (p[nr >> 5] & (1UL << (nr & 31))) != 0;
 }
 
-extern inline int test_and_set_bit(int nr, volatile void *vaddr)
+static inline int test_and_set_bit(int nr, volatile void *vaddr)
 {
 	char retval;
 
diff --git a/arch/m68k/include/asm/byteorder.h b/arch/m68k/include/asm/byteorder.h
index 908a99b7c8..7244b75820 100644
--- a/arch/m68k/include/asm/byteorder.h
+++ b/arch/m68k/include/asm/byteorder.h
@@ -22,25 +22,25 @@
 		(((__u32)(x) & (__u32)0x00ff0000UL) >>  8) | \
 		(((__u32)(x)) >> 24) ))
 
-extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
+static __inline__ unsigned ld_le16(const volatile unsigned short *addr)
 {
 	unsigned result = *addr;
 	return __sw16(result);
 }
 
-extern __inline__ void st_le16(volatile unsigned short *addr,
+static __inline__ void st_le16(volatile unsigned short *addr,
 			       const unsigned val)
 {
 	*addr = __sw16(val);
 }
 
-extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
+static __inline__ unsigned ld_le32(const volatile unsigned *addr)
 {
 	unsigned result = *addr;
 	return __sw32(result);
 }
 
-extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
+static __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
 {
 	*addr = __sw32(val);
 }
diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h
index 2d2a51901b..384308b747 100644
--- a/arch/m68k/include/asm/io.h
+++ b/arch/m68k/include/asm/io.h
@@ -67,28 +67,28 @@
 
 #define mb() __asm__ __volatile__ ("" : : : "memory")
 
-extern inline void _insb(volatile u8 * port, void *buf, int ns)
+static inline void _insb(volatile u8 * port, void *buf, int ns)
 {
 	u8 *data = (u8 *) buf;
 	while (ns--)
 		*data++ = *port;
 }
 
-extern inline void _outsb(volatile u8 * port, const void *buf, int ns)
+static inline void _outsb(volatile u8 * port, const void *buf, int ns)
 {
 	u8 *data = (u8 *) buf;
 	while (ns--)
 		*port = *data++;
 }
 
-extern inline void _insw(volatile u16 * port, void *buf, int ns)
+static inline void _insw(volatile u16 * port, void *buf, int ns)
 {
 	u16 *data = (u16 *) buf;
 	while (ns--)
 		*data++ = __sw16(*port);
 }
 
-extern inline void _outsw(volatile u16 * port, const void *buf, int ns)
+static inline void _outsw(volatile u16 * port, const void *buf, int ns)
 {
 	u16 *data = (u16 *) buf;
 	while (ns--) {
@@ -97,14 +97,14 @@ extern inline void _outsw(volatile u16 * port, const void *buf, int ns)
 	}
 }
 
-extern inline void _insl(volatile u32 * port, void *buf, int nl)
+static inline void _insl(volatile u32 * port, void *buf, int nl)
 {
 	u32 *data = (u32 *) buf;
 	while (nl--)
 		*data++ = __sw32(*port);
 }
 
-extern inline void _outsl(volatile u32 * port, const void *buf, int nl)
+static inline void _outsl(volatile u32 * port, const void *buf, int nl)
 {
 	u32 *data = (u32 *) buf;
 	while (nl--) {
@@ -113,14 +113,14 @@ extern inline void _outsl(volatile u32 * port, const void *buf, int nl)
 	}
 }
 
-extern inline void _insw_ns(volatile u16 * port, void *buf, int ns)
+static inline void _insw_ns(volatile u16 * port, void *buf, int ns)
 {
 	u16 *data = (u16 *) buf;
 	while (ns--)
 		*data++ = *port;
 }
 
-extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns)
+static inline void _outsw_ns(volatile u16 * port, const void *buf, int ns)
 {
 	u16 *data = (u16 *) buf;
 	while (ns--) {
@@ -128,14 +128,14 @@ extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns)
 	}
 }
 
-extern inline void _insl_ns(volatile u32 * port, void *buf, int nl)
+static inline void _insl_ns(volatile u32 * port, void *buf, int nl)
 {
 	u32 *data = (u32 *) buf;
 	while (nl--)
 		*data++ = *port;
 }
 
-extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl)
+static inline void _outsl_ns(volatile u32 * port, const void *buf, int nl)
 {
 	u32 *data = (u32 *) buf;
 	while (nl--) {
@@ -159,52 +159,52 @@ extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl)
 /*
  * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
  */
-extern inline int in_8(volatile u8 * addr)
+static inline int in_8(volatile u8 * addr)
 {
 	return (int)*addr;
 }
 
-extern inline void out_8(volatile u8 * addr, int val)
+static inline void out_8(volatile u8 * addr, int val)
 {
 	*addr = (u8) val;
 }
 
-extern inline int in_le16(volatile u16 * addr)
+static inline int in_le16(volatile u16 * addr)
 {
 	return __sw16(*addr);
 }
 
-extern inline int in_be16(volatile u16 * addr)
+static inline int in_be16(volatile u16 * addr)
 {
 	return (*addr & 0xFFFF);
 }
 
-extern inline void out_le16(volatile u16 * addr, int val)
+static inline void out_le16(volatile u16 * addr, int val)
 {
 	*addr = __sw16(val);
 }
 
-extern inline void out_be16(volatile u16 * addr, int val)
+static inline void out_be16(volatile u16 * addr, int val)
 {
 	*addr = (u16) val;
 }
 
-extern inline unsigned in_le32(volatile u32 * addr)
+static inline unsigned in_le32(volatile u32 * addr)
 {
 	return __sw32(*addr);
 }
 
-extern inline unsigned in_be32(volatile u32 * addr)
+static inline unsigned in_be32(volatile u32 * addr)
 {
 	return (*addr);
 }
 
-extern inline void out_le32(volatile unsigned *addr, int val)
+static inline void out_le32(volatile unsigned *addr, int val)
 {
 	*addr = __sw32(val);
 }
 
-extern inline void out_be32(volatile unsigned *addr, int val)
+static inline void out_be32(volatile unsigned *addr, int val)
 {
 	*addr = val;
 }
diff --git a/arch/microblaze/dts/Makefile b/arch/microblaze/dts/Makefile
index 6d4a11f62f..5e70d9e110 100644
--- a/arch/microblaze/dts/Makefile
+++ b/arch/microblaze/dts/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 dtb-y += microblaze-generic.dtb
 
 targets += $(dtb-y)
diff --git a/arch/microblaze/include/asm/bitops.h b/arch/microblaze/include/asm/bitops.h
index 0ac78d76f9..d24f2cf9d3 100644
--- a/arch/microblaze/include/asm/bitops.h
+++ b/arch/microblaze/include/asm/bitops.h
@@ -7,6 +7,10 @@
 
 #include <asm/byteorder.h>	/* swab32 */
 #include <asm/system.h>		/* save_flags */
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
 
 #ifdef __KERNEL__
 /*
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index b5c2a6367d..c31ff6efb4 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -17,6 +17,11 @@
 #include <asm/sgidefs.h>
 #include <asm/system.h>
 
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
 /*
  * clear_bit() doesn't provide any barrier for the compiler.
  */
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index 9c647aa428..eed159cd46 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -15,24 +15,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define	LINUX_MAX_ENVS		256
 #define	LINUX_MAX_ARGS		256
 
-#if defined(CONFIG_MALTA)
-#define mips_boot_malta		1
-#else
-#define mips_boot_malta		0
-#endif
-
-#if defined(CONFIG_MIPS_BOOT_CMDLINE_LEGACY)
-#define mips_boot_cmdline_legacy	1
-#else
-#define mips_boot_cmdline_legacy	0
-#endif
-
-#if defined(CONFIG_MIPS_BOOT_ENV_LEGACY)
-#define mips_boot_env_legacy	1
-#else
-#define mips_boot_env_legacy	0
-#endif
-
 static int linux_argc;
 static char **linux_argv;
 static char *linux_argp;
@@ -62,50 +44,6 @@ void arch_lmb_reserve(struct lmb *lmb)
 	lmb_reserve(lmb, sp, CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp);
 }
 
-static int boot_setup_linux(bootm_headers_t *images)
-{
-	int ret;
-	ulong rd_len;
-
-	rd_len = images->rd_end - images->rd_start;
-	ret = boot_ramdisk_high(&images->lmb, images->rd_start,
-		rd_len, &images->initrd_start, &images->initrd_end);
-	if (ret)
-		return ret;
-
-#if defined(CONFIG_MIPS_BOOT_FDT) && defined(CONFIG_OF_LIBFDT)
-	if (images->ft_len) {
-		boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr);
-
-		ret = boot_relocate_fdt(&images->lmb, &images->ft_addr,
-			&images->ft_len);
-		if (ret)
-			return ret;
-	}
-#endif
-
-	return 0;
-}
-
-static void boot_setup_fdt(bootm_headers_t *images)
-{
-#if defined(CONFIG_MIPS_BOOT_FDT) && defined(CONFIG_OF_LIBFDT)
-	u64 mem_start = 0;
-	u64 mem_size = gd->ram_size;
-
-	debug("## setup FDT\n");
-
-	fdt_chosen(images->ft_addr);
-	fdt_fixup_memory_banks(images->ft_addr, &mem_start, &mem_size, 1);
-	fdt_fixup_ethernet(images->ft_addr);
-	fdt_initrd(images->ft_addr, images->initrd_start, images->initrd_end);
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-	ft_board_setup(images->ft_addr, gd->bd);
-#endif
-#endif
-}
-
 static void linux_cmdline_init(void)
 {
 	linux_argc = 1;
@@ -197,18 +135,6 @@ static void linux_cmdline_append(bootm_headers_t *images)
 	}
 }
 
-static void boot_cmdline_linux(bootm_headers_t *images)
-{
-	if (mips_boot_cmdline_legacy && !images->ft_len) {
-		linux_cmdline_legacy(images);
-
-		if (!mips_boot_env_legacy)
-			linux_cmdline_append(images);
-
-		linux_cmdline_dump();
-	}
-}
-
 static void linux_env_init(void)
 {
 	linux_env = (char **)(((ulong) linux_argp + 15) & ~15);
@@ -225,7 +151,7 @@ static void linux_env_set(const char *env_name, const char *env_val)
 		strcpy(linux_env_p, env_name);
 		linux_env_p += strlen(env_name);
 
-		if (mips_boot_malta) {
+		if (CONFIG_IS_ENABLED(MALTA)) {
 			linux_env_p++;
 			linux_env[++linux_env_idx] = linux_env_p;
 		} else {
@@ -246,14 +172,15 @@ static void linux_env_legacy(bootm_headers_t *images)
 	const char *cp;
 	ulong rd_start, rd_size;
 
-#ifdef CONFIG_MEMSIZE_IN_BYTES
-	sprintf(env_buf, "%lu", (ulong)gd->ram_size);
-	debug("## Giving linux memsize in bytes, %lu\n", (ulong)gd->ram_size);
-#else
-	sprintf(env_buf, "%lu", (ulong)(gd->ram_size >> 20));
-	debug("## Giving linux memsize in MB, %lu\n",
-	      (ulong)(gd->ram_size >> 20));
-#endif /* CONFIG_MEMSIZE_IN_BYTES */
+	if (CONFIG_IS_ENABLED(MEMSIZE_IN_BYTES)) {
+		sprintf(env_buf, "%lu", (ulong)gd->ram_size);
+		debug("## Giving linux memsize in bytes, %lu\n",
+		      (ulong)gd->ram_size);
+	} else {
+		sprintf(env_buf, "%lu", (ulong)(gd->ram_size >> 20));
+		debug("## Giving linux memsize in MB, %lu\n",
+		      (ulong)(gd->ram_size >> 20));
+	}
 
 	rd_start = UNCACHED_SDRAM(images->initrd_start);
 	rd_size = images->initrd_end - images->initrd_start;
@@ -282,19 +209,87 @@ static void linux_env_legacy(bootm_headers_t *images)
 	if (cp)
 		linux_env_set("eth1addr", cp);
 
-	if (mips_boot_malta) {
+	if (CONFIG_IS_ENABLED(MALTA)) {
 		sprintf(env_buf, "%un8r", gd->baudrate);
 		linux_env_set("modetty0", env_buf);
 	}
 }
 
+static int boot_reloc_ramdisk(bootm_headers_t *images)
+{
+	ulong rd_len = images->rd_end - images->rd_start;
+
+	/*
+	 * In case of legacy uImage's, relocation of ramdisk is already done
+	 * by do_bootm_states() and should not repeated in 'bootm prep'.
+	 */
+	if (images->state & BOOTM_STATE_RAMDISK) {
+		debug("## Ramdisk already relocated\n");
+		return 0;
+	}
+
+	return boot_ramdisk_high(&images->lmb, images->rd_start,
+		rd_len, &images->initrd_start, &images->initrd_end);
+}
+
+static int boot_reloc_fdt(bootm_headers_t *images)
+{
+	/*
+	 * In case of legacy uImage's, relocation of FDT is already done
+	 * by do_bootm_states() and should not repeated in 'bootm prep'.
+	 */
+	if (images->state & BOOTM_STATE_FDT) {
+		debug("## FDT already relocated\n");
+		return 0;
+	}
+
+#if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT)
+	boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr);
+	return boot_relocate_fdt(&images->lmb, &images->ft_addr,
+		&images->ft_len);
+#else
+	return 0;
+#endif
+}
+
+int arch_fixup_memory_node(void *blob)
+{
+#if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT)
+	u64 mem_start = 0;
+	u64 mem_size = gd->ram_size;
+
+	return fdt_fixup_memory_banks(blob, &mem_start, &mem_size, 1);
+#else
+	return 0;
+#endif
+}
+
+static int boot_setup_fdt(bootm_headers_t *images)
+{
+	return image_setup_libfdt(images, images->ft_addr, images->ft_len,
+		&images->lmb);
+}
+
 static void boot_prep_linux(bootm_headers_t *images)
 {
-	if (mips_boot_env_legacy && !images->ft_len)
-		linux_env_legacy(images);
+	boot_reloc_ramdisk(images);
 
-	if (images->ft_len)
+	if (CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && images->ft_len) {
+		boot_reloc_fdt(images);
 		boot_setup_fdt(images);
+	} else {
+		if (CONFIG_IS_ENABLED(CONFIG_MIPS_BOOT_ENV_LEGACY))
+			linux_env_legacy(images);
+
+		if (CONFIG_IS_ENABLED(MIPS_BOOT_CMDLINE_LEGACY)) {
+			linux_cmdline_legacy(images);
+
+			if (!CONFIG_IS_ENABLED(CONFIG_MIPS_BOOT_ENV_LEGACY))
+				linux_cmdline_append(images);
+
+			linux_cmdline_dump();
+		}
+	}
 }
 
 static void boot_jump_linux(bootm_headers_t *images)
@@ -307,13 +302,13 @@ static void boot_jump_linux(bootm_headers_t *images)
 
 	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
 
-	if (mips_boot_malta)
+	if (CONFIG_IS_ENABLED(MALTA))
 		linux_extra = gd->ram_size;
 
-#ifdef CONFIG_BOOTSTAGE_FDT
+#if CONFIG_IS_ENABLED(BOOTSTAGE_FDT)
 	bootstage_fdt_add_report();
 #endif
-#ifdef CONFIG_BOOTSTAGE_REPORT
+#if CONFIG_IS_ENABLED(BOOTSTAGE_REPORT)
 	bootstage_report();
 #endif
 
@@ -327,35 +322,28 @@ static void boot_jump_linux(bootm_headers_t *images)
 int do_bootm_linux(int flag, int argc, char * const argv[],
 			bootm_headers_t *images)
 {
-	int ret;
-
 	/* No need for those on MIPS */
 	if (flag & BOOTM_STATE_OS_BD_T)
 		return -1;
 
-	if (flag & BOOTM_STATE_OS_CMDLINE) {
-		boot_cmdline_linux(images);
+	/*
+	 * Cmdline init has been moved to 'bootm prep' because it has to be
+	 * done after relocation of ramdisk to always pass correct values
+	 * for rd_start and rd_size to Linux kernel.
+	 */
+	if (flag & BOOTM_STATE_OS_CMDLINE)
 		return 0;
-	}
 
 	if (flag & BOOTM_STATE_OS_PREP) {
 		boot_prep_linux(images);
 		return 0;
 	}
 
-	if (flag & BOOTM_STATE_OS_GO) {
+	if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
 		boot_jump_linux(images);
 		return 0;
 	}
 
-	ret = boot_setup_linux(images);
-	if (ret)
-		return ret;
-
-	boot_cmdline_linux(images);
-	boot_prep_linux(images);
-	boot_jump_linux(images);
-
 	/* does not return */
 	return 1;
 }
diff --git a/arch/nds32/include/asm/bitops.h b/arch/nds32/include/asm/bitops.h
index f1aa9a356b..7ee37c37bc 100644
--- a/arch/nds32/include/asm/bitops.h
+++ b/arch/nds32/include/asm/bitops.h
@@ -21,6 +21,10 @@
 #ifdef __KERNEL__
 
 #include <asm/system.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
 
 #define smp_mb__before_clear_bit()	do { } while (0)
 #define smp_mb__after_clear_bit()	do { } while (0)
diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c
index ff0fa20798..f6d5cd399a 100644
--- a/arch/nios2/cpu/cpu.c
+++ b/arch/nios2/cpu/cpu.c
@@ -117,7 +117,9 @@ static int altera_nios2_probe(struct udevice *dev)
 		"altr,has-initda", 0);
 	gd->arch.has_mmu = fdtdec_get_int(blob, node,
 		"altr,has-mmu", 0);
-	gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x8000000;
+	gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x80000000;
+	gd->arch.mem_region_base = gd->arch.has_mmu ? 0xc0000000 : 0x00000000;
+	gd->arch.physaddr_mask = gd->arch.has_mmu ? 0x1fffffff : 0x7fffffff;
 
 	return 0;
 }
diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S
index 8758e7e847..54787c53ca 100644
--- a/arch/nios2/cpu/start.S
+++ b/arch/nios2/cpu/start.S
@@ -81,6 +81,7 @@ _cur:	movhi	r5, %hi(_cur - _start)
 	mov	r8, r4
 	movhi	r5, %hi(_start)
 	ori	r5, r5, %lo(_start)	/* r5 <- linked _start */
+	mov	sp, r5		/* initial stack below u-boot code */
 	beq	r4, r5, 3f
 
 	movhi	r6, %hi(CONFIG_SYS_MONITOR_LEN)
@@ -100,8 +101,6 @@ _cur:	movhi	r5, %hi(_cur - _start)
 _reloc:
 
 	/* STACK INIT -- zero top two words for call back chain. */
-	movhi	sp, %hi(CONFIG_SYS_INIT_SP)
-	ori	sp, sp, %lo(CONFIG_SYS_INIT_SP)
 	addi	sp, sp, -8
 	stw	r0, 0(sp)
 	stw	r0, 4(sp)
@@ -159,7 +158,7 @@ relocate_code:
 	ori	r6, r6, %lo(__bss_end)
 	beq	r5, r6, 5f
 
-4:	stwio	r0, 0(r5)
+4:	stw	r0, 0(r5)
 	addi	r5, r5, 4
 	bne	r5, r6, 4b
 5:
diff --git a/arch/nios2/dts/10m50_devboard.dts b/arch/nios2/dts/10m50_devboard.dts
new file mode 100644
index 0000000000..e89dbb2331
--- /dev/null
+++ b/arch/nios2/dts/10m50_devboard.dts
@@ -0,0 +1,267 @@
+/*
+ *  Copyright (C) 2015 Altera Corporation
+ *
+ * This file is generated by sopc2dts.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+	model = "Altera NiosII Max10";
+	compatible = "altr,niosii-max10";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu: cpu@0 {
+			device_type = "cpu";
+			compatible = "altr,nios2-1.1";
+			reg = <0x00000000>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			altr,exception-addr = <0xc8000120>;
+			altr,fast-tlb-miss-addr = <0xc0000100>;
+			altr,has-div = <1>;
+			altr,has-initda = <1>;
+			altr,has-mmu = <1>;
+			altr,has-mul = <1>;
+			altr,implementation = "fast";
+			altr,pid-num-bits = <8>;
+			altr,reset-addr = <0xd4000000>;
+			altr,tlb-num-entries = <256>;
+			altr,tlb-num-ways = <16>;
+			altr,tlb-ptr-sz = <8>;
+			clock-frequency = <75000000>;
+			dcache-line-size = <32>;
+			dcache-size = <32768>;
+			icache-line-size = <32>;
+			icache-size = <32768>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x08000000 0x08000000>,
+			<0x00000000 0x00000400>;
+	};
+
+	sopc0: sopc@0 {
+		device_type = "soc";
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "altr,avalon", "simple-bus";
+		bus-frequency = <75000000>;
+
+		jtag_uart: serial@18001530 {
+			compatible = "altr,juart-1.0";
+			reg = <0x18001530 0x00000008>;
+			interrupt-parent = <&cpu>;
+			interrupts = <7>;
+		};
+
+		a_16550_uart_0: serial@18001600 {
+			compatible = "altr,16550-FIFO32", "ns16550a";
+			reg = <0x18001600 0x00000200>;
+			interrupt-parent = <&cpu>;
+			interrupts = <1>;
+			auto-flow-control = <1>;
+			clock-frequency = <50000000>;
+			fifo-size = <32>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+		};
+
+		ext_flash: quadspi@0x180014a0 {
+			compatible = "altr,quadspi-1.0";
+			reg = <0x180014a0 0x00000020>,
+				<0x14000000 0x04000000>;
+			reg-names = "avl_csr", "avl_mem";
+			interrupt-parent = <&cpu>;
+			interrupts = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			flash0: nor0@0 {
+				compatible = "micron,n25q512a";
+				#address-cells = <1>;
+				#size-cells = <1>;
+			};
+		};
+
+		sysid: sysid@18001528 {
+			compatible = "altr,sysid-1.0";
+			reg = <0x18001528 0x00000008>;
+		};
+
+		rgmii_0_eth_tse_0: ethernet@400 {
+			compatible = "altr,tse-msgdma-1.0", "altr,tse-1.0";
+			reg = <0x00000400 0x00000400>,
+				<0x00000820 0x00000020>,
+				<0x00000800 0x00000020>,
+				<0x000008c0 0x00000008>,
+				<0x00000840 0x00000020>,
+				<0x00000860 0x00000020>;
+			reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp",
+				  "tx_csr", "tx_desc";
+			interrupt-parent = <&cpu>;
+			interrupts = <2 3>;
+			interrupt-names = "rx_irq", "tx_irq";
+			rx-fifo-depth = <8192>;
+			tx-fifo-depth = <8192>;
+			address-bits = <48>;
+			max-frame-size = <1518>;
+			local-mac-address = [00 00 00 00 00 00];
+			altr,has-supplementary-unicast;
+			altr,enable-sup-addr = <1>;
+			altr,has-hash-multicast-filter;
+			altr,enable-hash = <1>;
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy0>;
+			rgmii_0_eth_tse_0_mdio: mdio {
+				compatible = "altr,tse-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				phy0: ethernet-phy@0 {
+					reg = <0>;
+					device_type = "ethernet-phy";
+				};
+			};
+		};
+
+		enet_pll: clock@0 {
+			compatible = "altr,pll-1.0";
+			#clock-cells = <1>;
+
+			enet_pll_c0: enet_pll_c0 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <125000000>;
+				clock-output-names = "enet_pll-c0";
+			};
+
+			enet_pll_c1: enet_pll_c1 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <25000000>;
+				clock-output-names = "enet_pll-c1";
+			};
+
+			enet_pll_c2: enet_pll_c2 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <2500000>;
+				clock-output-names = "enet_pll-c2";
+			};
+		};
+
+		sys_pll: clock@1 {
+			compatible = "altr,pll-1.0";
+			#clock-cells = <1>;
+
+			sys_pll_c0: sys_pll_c0 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <100000000>;
+				clock-output-names = "sys_pll-c0";
+			};
+
+			sys_pll_c1: sys_pll_c1 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <50000000>;
+				clock-output-names = "sys_pll-c1";
+			};
+
+			sys_pll_c2: sys_pll_c2 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <75000000>;
+				clock-output-names = "sys_pll-c2";
+			};
+		};
+
+		sys_clk_timer: timer@18001440 {
+			compatible = "altr,timer-1.0";
+			reg = <0x18001440 0x00000020>;
+			interrupt-parent = <&cpu>;
+			interrupts = <0>;
+			clock-frequency = <75000000>;
+		};
+
+		led_pio: gpio@180014d0 {
+			compatible = "altr,pio-1.0";
+			reg = <0x180014d0 0x00000010>;
+			altr,gpio-bank-width = <4>;
+			resetvalue = <15>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-bank-name = "led";
+		};
+
+		uart_0: serial@0x18001420 {
+			compatible = "altr,uart-1.0";
+			reg = <0x18001420 0x00000020>;
+			interrupt-parent = <&cpu>;
+			interrupts = <1>;
+			clock-frequency = <75000000>;
+			current-speed = <115200>;
+		};
+
+		button_pio: gpio@180014c0 {
+			compatible = "altr,pio-1.0";
+			reg = <0x180014c0 0x00000010>;
+			interrupt-parent = <&cpu>;
+			interrupts = <6>;
+			altr,gpio-bank-width = <3>;
+			altr,interrupt-type = <2>;
+			edge_type = <1>;
+			level_trigger = <0>;
+			resetvalue = <0>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-bank-name = "button";
+		};
+
+		sys_clk_timer_1: timer@880 {
+			compatible = "altr,timer-1.0";
+			reg = <0x00000880 0x00000020>;
+			interrupt-parent = <&cpu>;
+			interrupts = <5>;
+			clock-frequency = <75000000>;
+		};
+
+		fpga_leds: leds {
+			compatible = "gpio-leds";
+
+			led_fpga0: fpga0 {
+				label = "fpga_led0";
+				gpios = <&led_pio 0 1>;
+			};
+
+			led_fpga1: fpga1 {
+				label = "fpga_led1";
+				gpios = <&led_pio 1 1>;
+			};
+
+			led_fpga2: fpga2 {
+				label = "fpga_led2";
+				gpios = <&led_pio 2 1>;
+			};
+
+			led_fpga3: fpga3 {
+				label = "fpga_led3";
+				gpios = <&led_pio 3 1>;
+			};
+		};
+	};
+
+	chosen {
+		bootargs = "debug console=ttyS0,115200";
+		stdout-path = &uart_0;
+	};
+};
diff --git a/arch/nios2/dts/Makefile b/arch/nios2/dts/Makefile
index b40eca9e0a..f22fabf881 100644
--- a/arch/nios2/dts/Makefile
+++ b/arch/nios2/dts/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 dtb-y += $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%).dtb
 
 targets += $(dtb-y)
diff --git a/arch/nios2/include/asm/bitops.h b/arch/nios2/include/asm/bitops.h
index 3e17964f25..ee46f3722c 100644
--- a/arch/nios2/include/asm/bitops.h
+++ b/arch/nios2/include/asm/bitops.h
@@ -13,4 +13,9 @@
 #include <asm/bitops/non-atomic.h>
 #include <asm/bitops/ffs.h>
 
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
 #endif /* __ASM_NIOS2_BITOPS_H */
diff --git a/arch/nios2/include/asm/global_data.h b/arch/nios2/include/asm/global_data.h
index d6a2cfab4f..9863fd9f88 100644
--- a/arch/nios2/include/asm/global_data.h
+++ b/arch/nios2/include/asm/global_data.h
@@ -18,6 +18,8 @@ struct arch_global_data {
 	int has_initda;
 	int has_mmu;
 	u32 io_region_base;
+	u32 mem_region_base;
+	u32 physaddr_mask;
 };
 
 #include <asm-generic/global_data.h>
diff --git a/arch/nios2/include/asm/io.h b/arch/nios2/include/asm/io.h
index e7da35b0c9..95d88012dd 100644
--- a/arch/nios2/include/asm/io.h
+++ b/arch/nios2/include/asm/io.h
@@ -18,15 +18,19 @@ static inline void sync(void)
  * that can be used to access the memory range with the caching
  * properties specified by "flags".
  */
-#define MAP_NOCACHE	(0)
-#define MAP_WRCOMBINE	(0)
-#define MAP_WRBACK	(0)
-#define MAP_WRTHROUGH	(0)
+#define MAP_NOCACHE	1
+#define MAP_WRCOMBINE	0
+#define MAP_WRBACK	0
+#define MAP_WRTHROUGH	0
 
 static inline void *
 map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
 {
-	return (void *)paddr;
+	DECLARE_GLOBAL_DATA_PTR;
+	if (flags)
+		return (void *)(paddr | gd->arch.io_region_base);
+	else
+		return (void *)(paddr | gd->arch.mem_region_base);
 }
 
 /*
@@ -40,10 +44,7 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
 static inline phys_addr_t virt_to_phys(void * vaddr)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	if (gd->arch.has_mmu)
-		return (phys_addr_t)vaddr & 0x1fffffff;
-	else
-		return (phys_addr_t)vaddr & 0x7fffffff;
+	return (phys_addr_t)vaddr & gd->arch.physaddr_mask;
 }
 
 static inline void *ioremap(unsigned long physaddr, unsigned long size)
@@ -172,4 +173,8 @@ static inline void outsl (unsigned long port, const void *src, unsigned long cou
 #define setbits_8(addr, set) setbits(8, addr, set)
 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
 
+#define memset_io(a, b, c)		memset((void *)(a), (b), (c))
+#define memcpy_fromio(a, b, c)		memcpy((a), (void *)(b), (c))
+#define memcpy_toio(a, b, c)		memcpy((void *)(a), (b), (c))
+
 #endif /* __ASM_NIOS2_IO_H_ */
diff --git a/arch/openrisc/include/asm/bitops.h b/arch/openrisc/include/asm/bitops.h
index 6d0b57c014..28c4658672 100644
--- a/arch/openrisc/include/asm/bitops.h
+++ b/arch/openrisc/include/asm/bitops.h
@@ -12,6 +12,10 @@
 #define PLATFORM_FFS
 #include <asm/bitops/ffs.h>
 
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
 #define hweight32(x) generic_hweight32(x)
 #define hweight16(x) generic_hweight16(x)
 #define hweight8(x) generic_hweight8(x)
diff --git a/arch/powerpc/cpu/Makefile b/arch/powerpc/cpu/Makefile
index 88b5298be0..b182aa66f3 100644
--- a/arch/powerpc/cpu/Makefile
+++ b/arch/powerpc/cpu/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 obj-$(CONFIG_MPC83xx) += mpc8xxx/
 obj-$(CONFIG_MPC85xx) += mpc8xxx/
 obj-$(CONFIG_MPC86xx) += mpc8xxx/
diff --git a/arch/powerpc/cpu/mpc512x/u-boot.lds b/arch/powerpc/cpu/mpc512x/u-boot.lds
index 9658b21951..b32f74e002 100644
--- a/arch/powerpc/cpu/mpc512x/u-boot.lds
+++ b/arch/powerpc/cpu/mpc512x/u-boot.lds
@@ -24,7 +24,6 @@ SECTIONS
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
     KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
     *(.fixup)
diff --git a/arch/powerpc/cpu/mpc5xx/u-boot.lds b/arch/powerpc/cpu/mpc5xx/u-boot.lds
index 719846526f..6a5357124d 100644
--- a/arch/powerpc/cpu/mpc5xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc5xx/u-boot.lds
@@ -33,7 +33,6 @@ SECTIONS
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
     KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot.lds b/arch/powerpc/cpu/mpc5xxx/u-boot.lds
index cd9e23fbb7..aa80d3dbb1 100644
--- a/arch/powerpc/cpu/mpc5xxx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc5xxx/u-boot.lds
@@ -28,7 +28,6 @@ SECTIONS
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
     KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
diff --git a/arch/powerpc/cpu/mpc8260/u-boot.lds b/arch/powerpc/cpu/mpc8260/u-boot.lds
index 50cbf85d23..469fc293eb 100644
--- a/arch/powerpc/cpu/mpc8260/u-boot.lds
+++ b/arch/powerpc/cpu/mpc8260/u-boot.lds
@@ -27,7 +27,6 @@ SECTIONS
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
     KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
diff --git a/arch/powerpc/cpu/mpc83xx/law.c b/arch/powerpc/cpu/mpc83xx/law.c
index 66c88b697e..262ae7f711 100644
--- a/arch/powerpc/cpu/mpc83xx/law.c
+++ b/arch/powerpc/cpu/mpc83xx/law.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <asm/fsl_law.h>
 #include <asm/mmu.h>
+#include <linux/log2.h>
 
 int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
 {
@@ -20,7 +21,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
 	if (start == 0)
 		start_align = 1ull << (LAW_SIZE_2G + 1);
 	else
-		start_align = 1ull << (ffs64(start) - 1);
+		start_align = 1ull << (__ffs64(start) - 1);
 	law_sz = min(start_align, sz);
 	law_sz_enc = __ilog2_u64(law_sz) - 1;
 
@@ -40,7 +41,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
 	if (sz) {
 		start += law_sz;
 
-		start_align = 1ull << (ffs64(start) - 1);
+		start_align = 1ull << (__ffs64(start) - 1);
 		law_sz = min(start_align, sz);
 		law_sz_enc = __ilog2_u64(law_sz) - 1;
 		ecm = &immap->sysconf.ddrlaw[1];
diff --git a/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds
index 774772beaf..4101eaf3f3 100644
--- a/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds
@@ -24,7 +24,6 @@ SECTIONS
 		_GOT2_TABLE_ = .;
 		KEEP(*(.got2))
 		KEEP(*(.got))
-		PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
 	}
 	__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
 
diff --git a/arch/powerpc/cpu/mpc83xx/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot.lds
index 3c177fa291..dbd8bbe23c 100644
--- a/arch/powerpc/cpu/mpc83xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc83xx/u-boot.lds
@@ -26,7 +26,6 @@ SECTIONS
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
     KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index ae0823af65..0b89157fca 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -149,6 +149,9 @@ config TARGET_XPEDITE550X
 config TARGET_UCP1020
 	bool "Support uCP1020"
 
+config TARGET_CYRUS
+	bool "Support Varisys Cyrus"
+
 endchoice
 
 source "board/freescale/b4860qds/Kconfig"
@@ -185,6 +188,7 @@ source "board/gdsys/p1022/Kconfig"
 source "board/keymile/kmp204x/Kconfig"
 source "board/sbc8548/Kconfig"
 source "board/socrates/Kconfig"
+source "board/varisys/cyrus/Kconfig"
 source "board/xes/xpedite520x/Kconfig"
 source "board/xes/xpedite537x/Kconfig"
 source "board/xes/xpedite550x/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index d4c3d9df9b..7270be1b28 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -13,6 +13,7 @@
 #include <asm/processor.h>
 #include <linux/ctype.h>
 #include <asm/io.h>
+#include <asm/fsl_fdt.h>
 #include <asm/fsl_portals.h>
 #include <hwconfig.h>
 #ifdef CONFIG_FSL_ESDHC
@@ -943,3 +944,13 @@ int ft_verify_fdt(void *fdt)
 
 	return 1;
 }
+
+void fdt_del_diu(void *blob)
+{
+	int nodeoff = 0;
+
+	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+				"fsl,diu")) >= 0) {
+		fdt_del_node(blob, nodeoff);
+	}
+}
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index d954fe2fd2..e732969e41 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -131,7 +131,8 @@ void get_sys_info(sys_info_t *sys_info)
 	 * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
 	 */
 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
-	defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080)
+	defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \
+	defined(CONFIG_PPC_T2081)
 	svr = get_svr();
 	switch (SVR_SOC_VER(svr)) {
 	case SVR_T4240:
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 8e0508f362..cf31eb2ef3 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -14,6 +14,8 @@
 #include <addr_map.h>
 #endif
 
+#include <linux/log2.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 void invalidate_tlb(u8 tlb)
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
index f933b21944..0399f93e6e 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
@@ -44,7 +44,6 @@ SECTIONS
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
     KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
index b83c55388c..f04456442c 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
@@ -22,7 +22,6 @@ SECTIONS
 		_GOT2_TABLE_ = .;
 		KEEP(*(.got2))
 		KEEP(*(.got))
-		PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
 		_FIXUP_TABLE_ = .;
 		KEEP(*(.fixup))
 	}
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index 5ae7b3eedb..889a4c2400 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -29,7 +29,6 @@ SECTIONS
 		_GOT2_TABLE_ = .;
 		KEEP(*(.got2))
 		KEEP(*(.got))
-		PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
 		_FIXUP_TABLE_ = .;
 		KEEP(*(.fixup))
 	}
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds
index 2cf0b25952..f15eaf3805 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@@ -50,7 +50,6 @@ SECTIONS
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
     KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
diff --git a/arch/powerpc/cpu/mpc86xx/u-boot.lds b/arch/powerpc/cpu/mpc86xx/u-boot.lds
index 58467c2cc8..6c48f40992 100644
--- a/arch/powerpc/cpu/mpc86xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc86xx/u-boot.lds
@@ -32,7 +32,6 @@ SECTIONS
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
     KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c
index 659e6889bf..15cee3fd4a 100644
--- a/arch/powerpc/cpu/mpc8xx/video.c
+++ b/arch/powerpc/cpu/mpc8xx/video.c
@@ -1089,7 +1089,6 @@ int drv_video_init (void)
 	memset (&videodev, 0, sizeof (videodev));
 
 	strcpy (videodev.name, "video");
-	videodev.ext = DEV_EXT_VIDEO;	/* Video extensions */
 	videodev.flags = DEV_FLAGS_OUTPUT;	/* Output only */
 	videodev.putc = video_putc;	/* 'putc' function */
 	videodev.puts = video_puts;	/* 'puts' function */
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile
index e95539e0a3..ac45e0e3df 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -1,9 +1,7 @@
 #
 # Copyright 2009-2010 Freescale Semiconductor, Inc.
 #
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# Version 2 as published by the Free Software Foundation.
+# SPDX-License-Identifier:	GPL-2.0
 #
 
 MINIMAL=
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index 33d53a8cfe..24baad442e 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -11,6 +11,7 @@
 #include <linux/compiler.h>
 #include <asm/fsl_law.h>
 #include <asm/io.h>
+#include <linux/log2.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -187,7 +188,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
 	if (start == 0)
 		start_align = 1ull << (LAW_SIZE_32G + 1);
 	else
-		start_align = 1ull << (ffs64(start) - 1);
+		start_align = 1ull << (__ffs64(start) - 1);
 	law_sz = min(start_align, sz);
 	law_sz_enc = __ilog2_u64(law_sz) - 1;
 
@@ -202,7 +203,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
 	if (sz) {
 		start += law_sz;
 
-		start_align = 1ull << (ffs64(start) - 1);
+		start_align = 1ull << (__ffs64(start) - 1);
 		law_sz = min(start_align, sz);
 		law_sz_enc = __ilog2_u64(law_sz) - 1;
 
diff --git a/arch/powerpc/cpu/ppc4xx/u-boot.lds b/arch/powerpc/cpu/ppc4xx/u-boot.lds
index 198050853a..55dd4e1300 100644
--- a/arch/powerpc/cpu/ppc4xx/u-boot.lds
+++ b/arch/powerpc/cpu/ppc4xx/u-boot.lds
@@ -46,7 +46,6 @@ SECTIONS
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
     KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index ad104b9315..5d9f5c2822 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 dtb-$(CONFIG_TARGET_CANYONLANDS) += arches.dtb canyonlands.dtb glacier.dtb
 
 targets += $(dtb-y)
diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h
index 43a2bb2b3e..87efcca68a 100644
--- a/arch/powerpc/include/asm/atomic.h
+++ b/arch/powerpc/include/asm/atomic.h
@@ -19,7 +19,7 @@ typedef struct { int counter; } atomic_t;
 extern void atomic_clear_mask(unsigned long mask, unsigned long *addr);
 extern void atomic_set_mask(unsigned long mask, unsigned long *addr);
 
-extern __inline__ int atomic_add_return(int a, atomic_t *v)
+static __inline__ int atomic_add_return(int a, atomic_t *v)
 {
 	int t;
 
@@ -35,7 +35,7 @@ extern __inline__ int atomic_add_return(int a, atomic_t *v)
 	return t;
 }
 
-extern __inline__ int atomic_sub_return(int a, atomic_t *v)
+static __inline__ int atomic_sub_return(int a, atomic_t *v)
 {
 	int t;
 
@@ -51,7 +51,7 @@ extern __inline__ int atomic_sub_return(int a, atomic_t *v)
 	return t;
 }
 
-extern __inline__ int atomic_inc_return(atomic_t *v)
+static __inline__ int atomic_inc_return(atomic_t *v)
 {
 	int t;
 
@@ -67,7 +67,7 @@ extern __inline__ int atomic_inc_return(atomic_t *v)
 	return t;
 }
 
-extern __inline__ int atomic_dec_return(atomic_t *v)
+static __inline__ int atomic_dec_return(atomic_t *v)
 {
 	int t;
 
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index a6bcf3c3fe..96491b6e4e 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -6,13 +6,7 @@
 #define _PPC_BITOPS_H
 
 #include <asm/byteorder.h>
-
-extern void set_bit(int nr, volatile void *addr);
-extern void clear_bit(int nr, volatile void *addr);
-extern void change_bit(int nr, volatile void *addr);
-extern int test_and_set_bit(int nr, volatile void *addr);
-extern int test_and_clear_bit(int nr, volatile void *addr);
-extern int test_and_change_bit(int nr, volatile void *addr);
+#include <asm-generic/bitops/__ffs.h>
 
 /*
  * Arguably these bit operations don't imply any memory barrier or
@@ -34,7 +28,7 @@ extern int test_and_change_bit(int nr, volatile void *addr);
  * These used to be if'd out here because using : "cc" as a constraint
  * resulted in errors from egcs.  Things may be OK with gcc-2.95.
  */
-extern __inline__ void set_bit(int nr, volatile void * addr)
+static __inline__ void set_bit(int nr, volatile void * addr)
 {
 	unsigned long old;
 	unsigned long mask = 1 << (nr & 0x1f);
@@ -51,7 +45,7 @@ extern __inline__ void set_bit(int nr, volatile void * addr)
 	: "cc" );
 }
 
-extern __inline__ void clear_bit(int nr, volatile void *addr)
+static __inline__ void clear_bit(int nr, volatile void *addr)
 {
 	unsigned long old;
 	unsigned long mask = 1 << (nr & 0x1f);
@@ -68,7 +62,7 @@ extern __inline__ void clear_bit(int nr, volatile void *addr)
 	: "cc");
 }
 
-extern __inline__ void change_bit(int nr, volatile void *addr)
+static __inline__ void change_bit(int nr, volatile void *addr)
 {
 	unsigned long old;
 	unsigned long mask = 1 << (nr & 0x1f);
@@ -85,7 +79,7 @@ extern __inline__ void change_bit(int nr, volatile void *addr)
 	: "cc");
 }
 
-extern __inline__ int test_and_set_bit(int nr, volatile void *addr)
+static __inline__ int test_and_set_bit(int nr, volatile void *addr)
 {
 	unsigned int old, t;
 	unsigned int mask = 1 << (nr & 0x1f);
@@ -104,7 +98,7 @@ extern __inline__ int test_and_set_bit(int nr, volatile void *addr)
 	return (old & mask) != 0;
 }
 
-extern __inline__ int test_and_clear_bit(int nr, volatile void *addr)
+static __inline__ int test_and_clear_bit(int nr, volatile void *addr)
 {
 	unsigned int old, t;
 	unsigned int mask = 1 << (nr & 0x1f);
@@ -123,7 +117,7 @@ extern __inline__ int test_and_clear_bit(int nr, volatile void *addr)
 	return (old & mask) != 0;
 }
 
-extern __inline__ int test_and_change_bit(int nr, volatile void *addr)
+static __inline__ int test_and_change_bit(int nr, volatile void *addr)
 {
 	unsigned int old, t;
 	unsigned int mask = 1 << (nr & 0x1f);
@@ -143,7 +137,7 @@ extern __inline__ int test_and_change_bit(int nr, volatile void *addr)
 }
 #endif /* __INLINE_BITOPS */
 
-extern __inline__ int test_bit(int nr, __const__ volatile void *addr)
+static __inline__ int test_bit(int nr, __const__ volatile void *addr)
 {
 	__const__ unsigned int *p = (__const__ unsigned int *) addr;
 
@@ -152,7 +146,7 @@ extern __inline__ int test_bit(int nr, __const__ volatile void *addr)
 
 /* Return the bit position of the most significant 1 bit in a word */
 /* - the result is undefined when x == 0 */
-extern __inline__ int __ilog2(unsigned int x)
+static __inline__ int __ilog2(unsigned int x)
 {
 	int lz;
 
@@ -160,7 +154,7 @@ extern __inline__ int __ilog2(unsigned int x)
 	return 31 - lz;
 }
 
-extern __inline__ int ffz(unsigned int x)
+static __inline__ int ffz(unsigned int x)
 {
 	if ((x = ~x) == 0)
 		return 32;
@@ -209,16 +203,6 @@ static inline int fls64(__u64 x)
 #error BITS_PER_LONG not 32 or 64
 #endif
 
-static inline int __ilog2_u64(u64 n)
-{
-	return fls64(n) - 1;
-}
-
-static inline int ffs64(u64 x)
-{
-	return __ilog2_u64(x & -x) + 1ull;
-}
-
 #ifdef __KERNEL__
 
 /*
@@ -226,7 +210,7 @@ static inline int ffs64(u64 x)
  * the libc and compiler builtin ffs routines, therefore
  * differs in spirit from the above ffz (man ffs).
  */
-extern __inline__ int ffs(int x)
+static __inline__ int ffs(int x)
 {
 	return __ilog2(x & -x) + 1;
 }
@@ -250,7 +234,7 @@ extern __inline__ int ffs(int x)
 #define find_first_zero_bit(addr, size) \
 	find_next_zero_bit((addr), (size), 0)
 
-extern __inline__ unsigned long find_next_zero_bit(void * addr,
+static __inline__ unsigned long find_next_zero_bit(void * addr,
 	unsigned long size, unsigned long offset)
 {
 	unsigned int * p = ((unsigned int *) addr) + (offset >> 5);
@@ -298,7 +282,7 @@ found_middle:
 #define ext2_clear_bit(nr, addr)	test_and_clear_bit((nr) ^ 0x18, addr)
 
 #else
-extern __inline__ int ext2_set_bit(int nr, void * addr)
+static __inline__ int ext2_set_bit(int nr, void * addr)
 {
 	int		mask;
 	unsigned char	*ADDR = (unsigned char *) addr;
@@ -311,7 +295,7 @@ extern __inline__ int ext2_set_bit(int nr, void * addr)
 	return oldbit;
 }
 
-extern __inline__ int ext2_clear_bit(int nr, void * addr)
+static __inline__ int ext2_clear_bit(int nr, void * addr)
 {
 	int		mask;
 	unsigned char	*ADDR = (unsigned char *) addr;
@@ -325,7 +309,7 @@ extern __inline__ int ext2_clear_bit(int nr, void * addr)
 }
 #endif	/* __KERNEL__ */
 
-extern __inline__ int ext2_test_bit(int nr, __const__ void * addr)
+static __inline__ int ext2_test_bit(int nr, __const__ void * addr)
 {
 	__const__ unsigned char	*ADDR = (__const__ unsigned char *) addr;
 
diff --git a/arch/powerpc/include/asm/byteorder.h b/arch/powerpc/include/asm/byteorder.h
index 3f5bcf63a1..f731d18e76 100644
--- a/arch/powerpc/include/asm/byteorder.h
+++ b/arch/powerpc/include/asm/byteorder.h
@@ -5,7 +5,7 @@
 
 #ifdef __GNUC__
 
-extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
+static __inline__ unsigned ld_le16(const volatile unsigned short *addr)
 {
 	unsigned val;
 
@@ -13,12 +13,12 @@ extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
 	return val;
 }
 
-extern __inline__ void st_le16(volatile unsigned short *addr, const unsigned val)
+static __inline__ void st_le16(volatile unsigned short *addr, const unsigned val)
 {
 	__asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
 }
 
-extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
+static __inline__ unsigned ld_le32(const volatile unsigned *addr)
 {
 	unsigned val;
 
@@ -26,7 +26,7 @@ extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
 	return val;
 }
 
-extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
+static __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
 {
 	__asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
 }
diff --git a/arch/powerpc/include/asm/fsl_dtsec.h b/arch/powerpc/include/asm/fsl_dtsec.h
deleted file mode 100644
index 41b8398ecd..0000000000
--- a/arch/powerpc/include/asm/fsl_dtsec.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __DTSEC_H__
-#define __DTSEC_H__
-
-#include <asm/types.h>
-
-struct dtsec {
-	u32	tsec_id;	/* controller ID and version */
-	u32	tsec_id2;	/* controller ID and configuration */
-	u32	ievent;		/* interrupt event */
-	u32	imask;		/* interrupt mask */
-	u32	res0;
-	u32	ecntrl;		/* ethernet control and configuration */
-	u32	ptv;		/* pause time value */
-	u32	tbipa;		/* TBI PHY address */
-	u32	res1[8];
-	u32	tctrl;		/* Transmit control register */
-	u32	res2[3];
-	u32	rctrl;		/* Receive control register */
-	u32	res3[11];
-	u32	igaddr[8];	/* Individual group address */
-	u32	gaddr[8];	/* group address */
-	u32	res4[16];
-	u32	maccfg1;	/* MAC configuration register 1 */
-	u32	maccfg2;	/* MAC configuration register 2 */
-	u32	ipgifg;		/* inter-packet/inter-frame gap */
-	u32	hafdup;		/* half-duplex control */
-	u32	maxfrm;		/* Maximum frame size */
-	u32	res5[3];
-	u32	miimcfg;	/* MII management configuration */
-	u32	miimcom;	/* MII management command */
-	u32	miimadd;	/* MII management address */
-	u32	miimcon;	/* MII management control */
-	u32	miimstat;	/* MII management status */
-	u32	miimind;	/* MII management indicator */
-	u32	res6;
-	u32	ifstat;		/* Interface status */
-	u32	macstnaddr1;	/* MAC station address 1 */
-	u32	macstnaddr2;	/* MAC station address 2 */
-	u32	res7[46];
-	/* transmit and receive counter */
-	u32	tr64;		/* Tx and Rx 64 bytes frame */
-	u32	tr127;		/* Tx and Rx 65 to 127 bytes frame */
-	u32	tr255;		/* Tx and Rx 128 to 255 bytes frame */
-	u32	tr511;		/* Tx and Rx 256 to 511 bytes frame */
-	u32	tr1k;		/* Tx and Rx 512 to 1023 bytes frame */
-	u32	trmax;		/* Tx and Rx 1024 to 1518 bytes frame */
-	u32	trmgv;		/* Tx and Rx 1519 to 1522 good VLAN frame */
-	/* receive counters */
-	u32	rbyt;		/* Receive byte counter */
-	u32	rpkt;		/* Receive packet counter */
-	u32	rfcs;		/* Receive FCS error */
-	u32	rmca;		/* Receive multicast packet */
-	u32	rbca;		/* Receive broadcast packet */
-	u32	rxcf;		/* Receive control frame */
-	u32	rxpf;		/* Receive pause frame */
-	u32	rxuo;		/* Receive unknown OP code */
-	u32	raln;		/* Receive alignment error */
-	u32	rflr;		/* Receive frame length error */
-	u32	rcde;		/* Receive code error */
-	u32	rcse;		/* Receive carrier sense error */
-	u32	rund;		/* Receive undersize packet */
-	u32	rovr;		/* Receive oversize packet */
-	u32	rfrg;		/* Receive fragments counter */
-	u32	rjbr;		/* Receive jabber counter */
-	u32	rdrp;		/* Receive drop counter */
-	/* transmit counters */
-	u32	tbyt;		/* Transmit byte counter */
-	u32	tpkt;		/* Transmit packet */
-	u32	tmca;		/* Transmit multicast packet */
-	u32	tbca;		/* Transmit broadcast packet */
-	u32	txpf;		/* Transmit pause control frame */
-	u32	tdfr;		/* Transmit deferral packet */
-	u32	tedf;		/* Transmit excessive deferral pkt */
-	u32	tscl;		/* Transmit single collision pkt */
-	u32	tmcl;		/* Transmit multiple collision pkt */
-	u32	tlcl;		/* Transmit late collision pkt */
-	u32	txcl;		/* Transmit excessive collision */
-	u32	tncl;		/* Transmit total collision */
-	u32	res8;
-	u32	tdrp;		/* Transmit drop frame */
-	u32	tjbr;		/* Transmit jabber frame */
-	u32	tfcs;		/* Transmit FCS error */
-	u32	txcf;		/* Transmit control frame */
-	u32	tovr;		/* Transmit oversize frame */
-	u32	tund;		/* Transmit undersize frame */
-	u32	tfrg;		/* Transmit fragments frame */
-	/* counter controls */
-	u32	car1;		/* carry register 1 */
-	u32	car2;		/* carry register 2 */
-	u32	cam1;		/* carry register 1 mask */
-	u32	cam2;		/* carry register 2 mask */
-	u32	res9[80];
-};
-
-
-/* TBI register addresses */
-#define TBI_CR			0x00
-#define TBI_SR			0x01
-#define TBI_ANA			0x04
-#define TBI_ANLPBPA		0x05
-#define TBI_ANEX		0x06
-#define TBI_TBICON		0x11
-
-/* TBI MDIO register bit fields*/
-#define TBICON_CLK_SELECT	0x0020
-#define TBIANA_ASYMMETRIC_PAUSE 0x0100
-#define TBIANA_SYMMETRIC_PAUSE  0x0080
-#define TBIANA_HALF_DUPLEX	0x0040
-#define TBIANA_FULL_DUPLEX	0x0020
-#define TBICR_PHY_RESET		0x8000
-#define TBICR_ANEG_ENABLE	0x1000
-#define TBICR_RESTART_ANEG	0x0200
-#define TBICR_FULL_DUPLEX	0x0100
-#define TBICR_SPEED1_SET	0x0040
-
-/* IEVENT - interrupt events register */
-#define IEVENT_BABR	0x80000000 /* Babbling receive error */
-#define IEVENT_RXC	0x40000000 /* pause control frame received */
-#define IEVENT_MSRO	0x04000000 /* MIB counter overflow */
-#define IEVENT_GTSC	0x02000000 /* Graceful transmit stop complete */
-#define IEVENT_BABT	0x01000000 /* Babbling transmit error */
-#define IEVENT_TXC	0x00800000 /* control frame transmitted */
-#define IEVENT_TXE	0x00400000 /* Transmit channel error */
-#define IEVENT_LC	0x00040000 /* Late collision occurred */
-#define IEVENT_CRL	0x00020000 /* Collision retry exceed limit */
-#define IEVENT_XFUN	0x00010000 /* Transmit FIFO underrun */
-#define IEVENT_ABRT	0x00008000 /* Transmit packet abort */
-#define IEVENT_MMRD	0x00000400 /* MII management read complete */
-#define IEVENT_MMWR	0x00000200 /* MII management write complete */
-#define IEVENT_GRSC	0x00000100 /* Graceful stop complete */
-#define IEVENT_TDPE	0x00000002 /* Internal data parity error on Tx */
-#define IEVENT_RDPE	0x00000001 /* Internal data parity error on Rx */
-
-#define IEVENT_CLEAR_ALL	0xffffffff
-
-/* IMASK - interrupt mask register */
-#define IMASK_BREN	0x80000000 /* Babbling receive enable */
-#define IMASK_RXCEN	0x40000000 /* receive control enable */
-#define IMASK_MSROEN	0x04000000 /* MIB counter overflow enable */
-#define IMASK_GTSCEN	0x02000000 /* Graceful Tx stop complete enable */
-#define IMASK_BTEN	0x01000000 /* Babbling transmit error enable */
-#define IMASK_TXCEN	0x00800000 /* control frame transmitted enable */
-#define IMASK_TXEEN	0x00400000 /* Transmit channel error enable */
-#define IMASK_LCEN	0x00040000 /* Late collision interrupt enable */
-#define IMASK_CRLEN	0x00020000 /* Collision retry exceed limit */
-#define IMASK_XFUNEN	0x00010000 /* Transmit FIFO underrun enable */
-#define IMASK_ABRTEN	0x00008000 /* Transmit packet abort enable */
-#define IMASK_MMRDEN	0x00000400 /* MII management read complete enable */
-#define IMASK_MMWREN	0x00000200 /* MII management write complete enable */
-#define IMASK_GRSCEN	0x00000100 /* Graceful stop complete interrupt enable */
-#define IMASK_TDPEEN	0x00000002 /* Internal data parity error on Tx enable */
-#define IMASK_RDPEEN	0x00000001 /* Internal data parity error on Rx enable */
-
-#define IMASK_MASK_ALL	0x00000000
-
-/* ECNTRL - ethernet control register */
-#define ECNTRL_CFG_RO	0x80000000 /* GMIIM, RPM, R100M, SGMIIM bits are RO */
-#define ECNTRL_CLRCNT	0x00004000 /* clear all statistics */
-#define ECNTRL_AUTOZ	0x00002000 /* auto zero MIB counter */
-#define ECNTRL_STEN	0x00001000 /* enable internal counters to update */
-#define ECNTRL_GMIIM	0x00000040 /* 1- GMII or RGMII interface mode */
-#define ECNTRL_TBIM	0x00000020 /* 1- Ten-bit interface mode */
-#define ECNTRL_RPM	0x00000010 /* 1- RGMII reduced-pin mode */
-#define ECNTRL_R100M	0x00000008 /* 1- RGMII 100 Mbps, SGMII 100 Mbps
-				      0- RGMII 10 Mbps, SGMII 10 Mbps */
-#define ECNTRL_SGMIIM	0x00000002 /* 1- SGMII interface mode */
-#define ECNTRL_TBIM	0x00000020 /* 1- TBI Interface mode (for SGMII) */
-
-#define ECNTRL_DEFAULT	(ECNTRL_TBIM | ECNTRL_R100M | ECNTRL_SGMIIM)
-
-/* TCTRL - Transmit control register */
-#define TCTRL_THDF	0x00000800 /* Transmit half-duplex flow control */
-#define TCTRL_TTSE	0x00000040 /* Transmit time-stamp enable */
-#define TCTRL_GTS	0x00000020 /* Graceful transmit stop */
-#define TCTRL_RFC_PAUSE	0x00000010 /* Receive flow control pause frame */
-
-/* RCTRL - Receive control register */
-#define RCTRL_PAL_MASK	0x001f0000 /* packet alignment padding length */
-#define RCTRL_PAL_SHIFT	16
-#define RCTRL_CFA	0x00008000 /* control frame accept enable */
-#define RCTRL_GHTX	0x00000800 /* group address hash table extend */
-#define RCTRL_RTSE	0x00000040 /* receive 1588 time-stamp enable */
-#define RCTRL_GRS	0x00000020 /* graceful receive stop */
-#define RCTRL_BC_REJ	0x00000010 /* broadcast frame reject */
-#define RCTRL_BC_MPROM	0x00000008 /* all multicast/broadcast frames received */
-#define RCTRL_RSF	0x00000004 /* receive short frame(17~63 bytes) enable */
-#define RCTRL_EMEN	0x00000002 /* Exact match MAC address enable */
-#define RCTRL_UPROM	0x00000001 /* all unicast frame received */
-
-/* MACCFG1 - MAC configuration 1 register */
-#define MACCFG1_SOFT_RST	0x80000000 /* place the MAC in reset */
-#define MACCFG1_RST_RXMAC	0x00080000 /* reset receive MAC control block */
-#define MACCFG1_RST_TXMAC	0x00040000 /* reet transmit MAC control block */
-#define MACCFG1_RST_RXFUN	0x00020000 /* reset receive function block */
-#define MACCFG1_RST_TXFUN	0x00010000 /* reset transmit function block */
-#define MACCFG1_LOOPBACK	0x00000100 /* MAC loopback */
-#define MACCFG1_RX_FLOW		0x00000020 /* Receive flow */
-#define MACCFG1_TX_FLOW		0x00000010 /* Transmit flow */
-#define MACCFG1_SYNC_RXEN	0x00000008 /* Frame reception enabled */
-#define MACCFG1_RX_EN		0x00000004 /* Rx enable */
-#define MACCFG1_SYNC_TXEN	0x00000002 /* Frame transmission is enabled */
-#define MACCFG1_TX_EN		0x00000001 /* Tx enable */
-#define MACCFG1_RXTX_EN		(MACCFG1_RX_EN | MACCFG1_TX_EN)
-
-/* MACCFG2 - MAC configuration 2 register */
-#define MACCFG2_PRE_LEN_MASK	0x0000f000 /* preamble length */
-#define MACCFG2_PRE_LEN(x)	((x << 12) & MACCFG2_PRE_LEN_MASK)
-#define MACCFG2_IF_MODE_MASK	0x00000300
-#define MACCFG2_IF_MODE_NIBBLE	0x00000100 /* MII, 10/100 Mbps MII/RMII */
-#define MACCFG2_IF_MODE_BYTE	0x00000200 /* GMII/TBI, 1000 GMII/TBI */
-#define MACCFG2_PRE_RX_EN	0x00000080 /* receive preamble enable */
-#define MACCFG2_PRE_TX_EN	0x00000040 /* tx preable enable */
-#define MACCFG2_HUGE_FRAME	0x00000020 /* >= max frame len enable */
-#define MACCFG2_LEN_CHECK	0x00000010 /* MAC check frame's length Rx */
-#define MACCFG2_MAG_EN		0x00000008 /* magic packet enable */
-#define MACCFG2_PAD_CRC		0x00000004 /* pad and append CRC */
-#define MACCFG2_CRC_EN		0x00000002 /* MAC appends a CRC on all frames */
-#define MACCFG2_FULL_DUPLEX	0x00000001 /* Full deplex mode */
-
-struct fsl_enet_mac;
-
-void init_dtsec(struct fsl_enet_mac *mac, void *base, void *phyregs,
-		int max_rx_len);
-
-#endif
diff --git a/arch/powerpc/include/asm/fsl_fdt.h b/arch/powerpc/include/asm/fsl_fdt.h
new file mode 100644
index 0000000000..82e8f45644
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_fdt.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _FSL_FDT_H_
+#define _FSL_FDT_H_
+
+void fdt_del_diu(void *blob);
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_fman.h b/arch/powerpc/include/asm/fsl_fman.h
deleted file mode 100644
index 4d04415ba8..0000000000
--- a/arch/powerpc/include/asm/fsl_fman.h
+++ /dev/null
@@ -1,463 +0,0 @@
-/*
- * MPC85xx Internal Memory Map
- *
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __FSL_FMAN_H__
-#define __FSL_FMAN_H__
-
-#include <asm/types.h>
-
-typedef struct fm_bmi_common {
-	u32	fmbm_init;	/* BMI initialization */
-	u32	fmbm_cfg1;	/* BMI configuration1 */
-	u32	fmbm_cfg2;	/* BMI configuration2 */
-	u32	res0[0x5];
-	u32	fmbm_ievr;	/* interrupt event register */
-	u32	fmbm_ier;	/* interrupt enable register */
-	u32	fmbm_ifr;	/* interrupt force register */
-	u32	res1[0x5];
-	u32	fmbm_arb[0x8];	/* BMI arbitration */
-	u32	res2[0x28];
-	u32	fmbm_gde;	/* global debug enable */
-	u32	fmbm_pp[0x3f];	/* BMI port parameters */
-	u32	res3;
-	u32	fmbm_pfs[0x3f];	/* BMI port FIFO size */
-	u32	res4;
-	u32	fmbm_ppid[0x3f];/* port partition ID */
-} fm_bmi_common_t;
-
-typedef struct fm_qmi_common {
-	u32	fmqm_gc;	/* general configuration register */
-	u32	res0;
-	u32	fmqm_eie;	/* error interrupt event register */
-	u32	fmqm_eien;	/* error interrupt enable register */
-	u32	fmqm_eif;	/* error interrupt force register */
-	u32	fmqm_ie;	/* interrupt event register */
-	u32	fmqm_ien;	/* interrupt enable register */
-	u32	fmqm_if;	/* interrupt force register */
-	u32	fmqm_gs;	/* global status register */
-	u32	fmqm_ts;	/* task status register */
-	u32	fmqm_etfc;	/* enqueue total frame counter */
-	u32	fmqm_dtfc;	/* dequeue total frame counter */
-	u32	fmqm_dc0;	/* dequeue counter 0 */
-	u32	fmqm_dc1;	/* dequeue counter 1 */
-	u32	fmqm_dc2;	/* dequeue counter 2 */
-	u32	fmqm_dc3;	/* dequeue counter 3 */
-	u32	fmqm_dfnoc;	/* dequeue FQID not override counter */
-	u32	fmqm_dfcc;	/* dequeue FQID from context counter */
-	u32	fmqm_dffc;	/* dequeue FQID from FD counter */
-	u32	fmqm_dcc;	/* dequeue confirm counter */
-	u32	res1[0xc];
-	u32	fmqm_dtrc;	/* debug trap configuration register */
-	u32	fmqm_efddd;	/* enqueue frame descriptor dynamic debug */
-	u32	res3[0x2];
-	u32	res4[0xdc];	/* missing debug regs */
-} fm_qmi_common_t;
-
-typedef struct fm_bmi {
-	u8	res[1024];
-} fm_bmi_t;
-
-typedef struct fm_qmi {
-	u8	res[1024];
-} fm_qmi_t;
-
-struct fm_bmi_rx_port {
-	u32 fmbm_rcfg;	/* Rx configuration */
-	u32 fmbm_rst;	/* Rx status */
-	u32 fmbm_rda;	/* Rx DMA attributes */
-	u32 fmbm_rfp;	/* Rx FIFO parameters */
-	u32 fmbm_rfed;	/* Rx frame end data */
-	u32 fmbm_ricp;	/* Rx internal context parameters */
-	u32 fmbm_rim;	/* Rx internal margins */
-	u32 fmbm_rebm;	/* Rx external buffer margins */
-	u32 fmbm_rfne;	/* Rx frame next engine */
-	u32 fmbm_rfca;	/* Rx frame command attributes */
-	u32 fmbm_rfpne;	/* Rx frame parser next engine */
-	u32 fmbm_rpso;	/* Rx parse start offset */
-	u32 fmbm_rpp;	/* Rx policer profile */
-	u32 fmbm_rccb;	/* Rx coarse classification base */
-	u32 res1[0x2];
-	u32 fmbm_rprai[0x8];	/* Rx parse results array Initialization */
-	u32 fmbm_rfqid;		/* Rx frame queue ID */
-	u32 fmbm_refqid;	/* Rx error frame queue ID */
-	u32 fmbm_rfsdm;		/* Rx frame status discard mask */
-	u32 fmbm_rfsem;		/* Rx frame status error mask */
-	u32 fmbm_rfene;		/* Rx frame enqueue next engine */
-	u32 res2[0x23];
-	u32 fmbm_ebmpi[0x8];	/* buffer manager pool information */
-	u32 fmbm_acnt[0x8];	/* allocate counter */
-	u32 res3[0x8];
-	u32 fmbm_cgm[0x8];	/* congestion group map */
-	u32 fmbm_mpd;		/* BMan pool depletion */
-	u32 res4[0x1F];
-	u32 fmbm_rstc;		/* Rx statistics counters */
-	u32 fmbm_rfrc;		/* Rx frame counters */
-	u32 fmbm_rfbc;		/* Rx bad frames counter */
-	u32 fmbm_rlfc;		/* Rx large frames counter */
-	u32 fmbm_rffc;		/* Rx filter frames counter */
-	u32 fmbm_rfdc;		/* Rx frame discard counter */
-	u32 fmbm_rfldec;	/* Rx frames list DMA error counter */
-	u32 fmbm_rodc;		/* Rx out of buffers discard counter */
-	u32 fmbm_rbdc;		/* Rx buffers deallocate counter */
-	u32 res5[0x17];
-	u32 fmbm_rpc;		/* Rx performance counters */
-	u32 fmbm_rpcp;		/* Rx performance count parameters */
-	u32 fmbm_rccn;		/* Rx cycle counter */
-	u32 fmbm_rtuc;		/* Rx tasks utilization counter */
-	u32 fmbm_rrquc;		/* Rx receive queue utilization counter */
-	u32 fmbm_rduc;		/* Rx DMA utilization counter */
-	u32 fmbm_rfuc;		/* Rx FIFO utilization counter */
-	u32 fmbm_rpac;		/* Rx pause activation counter */
-	u32 res6[0x18];
-	u32 fmbm_rdbg;		/* Rx debug configuration */
-};
-
-/* FMBM_RCFG - Rx configuration */
-#define FMBM_RCFG_EN		0x80000000 /* port is enabled to receive data */
-#define FMBM_RCFG_FDOVR		0x02000000 /* frame discard override */
-#define FMBM_RCFG_IM		0x01000000 /* independent mode */
-
-/* FMBM_RST - Rx status */
-#define FMBM_RST_BSY		0x80000000 /* Rx port is busy */
-
-/* FMBM_RFCA - Rx frame command attributes */
-#define FMBM_RFCA_ORDER		0x80000000
-#define FMBM_RFCA_MR_MASK	0x003f0000
-#define FMBM_RFCA_MR(x)		((x << 16) & FMBM_RFCA_MR_MASK)
-
-/* FMBM_RSTC - Rx statistics */
-#define FMBM_RSTC_EN		0x80000000 /* statistics counters enable */
-
-struct fm_bmi_tx_port {
-	u32 fmbm_tcfg;	/* Tx configuration */
-	u32 fmbm_tst;	/* Tx status */
-	u32 fmbm_tda;	/* Tx DMA attributes */
-	u32 fmbm_tfp;	/* Tx FIFO parameters */
-	u32 fmbm_tfed;	/* Tx frame end data */
-	u32 fmbm_ticp;	/* Tx internal context parameters */
-	u32 fmbm_tfne;	/* Tx frame next engine */
-	u32 fmbm_tfca;	/* Tx frame command attributes */
-	u32 fmbm_tcfqid;/* Tx confirmation frame queue ID */
-	u32 fmbm_tfeqid;/* Tx error frame queue ID */
-	u32 fmbm_tfene;	/* Tx frame enqueue next engine */
-	u32 fmbm_trlmts;/* Tx rate limiter scale */
-	u32 fmbm_trlmt;	/* Tx rate limiter */
-	u32 res0[0x73];
-	u32 fmbm_tstc;	/* Tx statistics counters */
-	u32 fmbm_tfrc;	/* Tx frame counter */
-	u32 fmbm_tfdc;	/* Tx frames discard counter */
-	u32 fmbm_tfledc;/* Tx frame length error discard counter */
-	u32 fmbm_tfufdc;/* Tx frame unsupported format discard counter */
-	u32 fmbm_tbdc;	/* Tx buffers deallocate counter */
-	u32 res1[0x1a];
-	u32 fmbm_tpc;	/* Tx performance counters */
-	u32 fmbm_tpcp;	/* Tx performance count parameters */
-	u32 fmbm_tccn;	/* Tx cycle counter */
-	u32 fmbm_ttuc;	/* Tx tasks utilization counter */
-	u32 fmbm_ttcquc;/* Tx transmit confirm queue utilization counter */
-	u32 fmbm_tduc;	/* Tx DMA utilization counter */
-	u32 fmbm_tfuc;	/* Tx FIFO utilization counter */
-	u32 res2[0x19];
-	u32 fmbm_tdcfg;	/* Tx debug configuration */
-};
-
-/* FMBM_TCFG - Tx configuration */
-#define FMBM_TCFG_EN	0x80000000 /* port is enabled to transmit data */
-#define FMBM_TCFG_IM	0x01000000 /* independent mode enable */
-
-/* FMBM_TST - Tx status */
-#define FMBM_TST_BSY		0x80000000 /* Tx port is busy */
-
-/* FMBM_TFCA - Tx frame command attributes */
-#define FMBM_TFCA_ORDER		0x80000000
-#define FMBM_TFCA_MR_MASK	0x003f0000
-#define FMBM_TFCA_MR(x)		((x << 16) & FMBM_TFCA_MR_MASK)
-
-/* FMBM_TSTC - Tx statistics counters */
-#define FMBM_TSTC_EN		0x80000000
-
-/* FMBM_INIT - BMI initialization register */
-#define FMBM_INIT_START		0x80000000 /* init internal buffers */
-
-/* FMBM_CFG1 - BMI configuration 1 */
-#define FMBM_CFG1_FBPS_MASK	0x03ff0000 /* Free buffer pool size */
-#define FMBM_CFG1_FBPS_SHIFT	16
-#define FMBM_CFG1_FBPO_MASK	0x000003ff /* Free buffer pool offset */
-
-/* FMBM_IEVR - interrupt event */
-#define FMBM_IEVR_PEC		0x80000000 /* pipeline table ECC err detected */
-#define FMBM_IEVR_LEC		0x40000000 /* linked list RAM ECC error */
-#define FMBM_IEVR_SEC		0x20000000 /* statistics count RAM ECC error */
-#define FMBM_IEVR_CLEAR_ALL	(FMBM_IEVR_PEC | FMBM_IEVR_LEC | FMBM_IEVR_SEC)
-
-/* FMBM_IER - interrupt enable */
-#define FMBM_IER_PECE		0x80000000 /* PEC interrupt enable */
-#define FMBM_IER_LECE		0x40000000 /* LEC interrupt enable */
-#define FMBM_IER_SECE		0x20000000 /* SEC interrupt enable */
-
-#define FMBM_IER_DISABLE_ALL	0x00000000
-
-/* FMBM_PP - BMI Port Parameters */
-#define FMBM_PP_MXT_MASK	0x3f000000 /* Max # tasks */
-#define FMBM_PP_MXT(x)		(((x-1) << 24) & FMBM_PP_MXT_MASK)
-#define FMBM_PP_MXD_MASK	0x00000f00 /* Max DMA */
-#define FMBM_PP_MXD(x)		(((x-1) << 8) & FMBM_PP_MXD_MASK)
-
-/* FMBM_PFS - BMI Port FIFO Size */
-#define FMBM_PFS_IFSZ_MASK	0x000003ff /* Internal Fifo Size */
-#define FMBM_PFS_IFSZ(x)	(x & FMBM_PFS_IFSZ_MASK)
-
-/* FMQM_GC - global configuration */
-#define FMQM_GC_ENQ_EN		0x80000000 /* enqueue enable */
-#define FMQM_GC_DEQ_EN		0x40000000 /* dequeue enable */
-#define FMQM_GC_STEN		0x10000000 /* enable global stat counters */
-#define FMQM_GC_ENQ_THR_MASK	0x00003f00 /* max number of enqueue Tnum */
-#define FMQM_GC_ENQ(x)		((x << 8) &  FMQM_GC_ENQ_THR_MAS)
-#define FMQM_GC_DEQ_THR_MASK	0x0000003f /* max number of dequeue Tnum */
-#define FMQM_GC_DEQ(x)		(x & FMQM_GC_DEQ_THR_MASK)
-
-/* FMQM_EIE - error interrupt event register */
-#define FMQM_EIE_DEE		0x80000000 /* double-bit ECC error */
-#define FMQM_EIE_DFUPE		0x40000000 /* dequeue from unknown PortID */
-#define FMQM_EIE_CLEAR_ALL	(FMQM_EIE_DEE | FMQM_EIE_DFUPE)
-
-/* FMQM_EIEN - error interrupt enable register */
-#define FMQM_EIEN_DEEN		0x80000000 /* double-bit ECC error */
-#define FMQM_EIEN_DFUPEN	0x40000000 /* dequeue from unknown PortID */
-#define FMQM_EIEN_DISABLE_ALL	0x00000000
-
-/* FMQM_IE - interrupt event register */
-#define FMQM_IE_SEE		0x80000000 /* single-bit ECC error detected */
-#define FMQM_IE_CLEAR_ALL	FMQM_IE_SEE
-
-/* FMQM_IEN - interrupt enable register */
-#define FMQM_IEN_SEE		0x80000000 /* single-bit ECC err IRQ enable */
-#define FMQM_IEN_DISABLE_ALL	0x00000000
-
-/* NIA - next invoked action */
-#define NIA_ENG_RISC		0x00000000
-#define NIA_ENG_MASK		0x007c0000
-
-/* action code */
-#define NIA_RISC_AC_CC		0x00000006
-#define NIA_RISC_AC_IM_TX	0x00000008 /* independent mode Tx */
-#define NIA_RISC_AC_IM_RX	0x0000000a /* independent mode Rx */
-#define NIA_RISC_AC_HC		0x0000000c
-
-typedef struct fm_parser {
-	u8	res[1024];
-} fm_parser_t;
-
-typedef struct fm_policer {
-	u8	res[4*1024];
-} fm_policer_t;
-
-typedef struct fm_keygen {
-	u8	res[4*1024];
-} fm_keygen_t;
-
-typedef struct fm_dma {
-	u32	fmdmsr;		/* status register */
-	u32	fmdmmr;		/* mode register */
-	u32	fmdmtr;		/* bus threshold register */
-	u32	fmdmhy;		/* bus hysteresis register */
-	u32	fmdmsetr;	/* SOS emergency threshold register */
-	u32	fmdmtah;	/* transfer bus address high register */
-	u32	fmdmtal;	/* transfer bus address low register */
-	u32	fmdmtcid;	/* transfer bus communication ID register */
-	u32	fmdmra;		/* DMA bus internal ram address register */
-	u32	fmdmrd;		/* DMA bus internal ram data register */
-	u32	res0[0xb];
-	u32	fmdmdcr;	/* debug counter */
-	u32	fmdmemsr;	/* emrgency smoother register */
-	u32	res1;
-	u32	fmdmplr[32];	/* FM DMA PID-LIODN # register */
-	u32	res[0x3c8];
-} fm_dma_t;
-
-/* FMDMSR - Fman DMA status register */
-#define FMDMSR_CMDQNE		0x10000000 /* command queue not empty */
-#define FMDMSR_BER		0x08000000 /* bus err event occurred on bus */
-#define FMDMSR_RDB_ECC		0x04000000 /* read buffer ECC error */
-#define FMDMSR_WRB_SECC		0x02000000 /* write buf ECC err sys side */
-#define FMDMSR_WRB_FECC		0x01000000 /* write buf ECC err Fman side */
-#define FMDMSR_DPEXT_SECC	0x00800000 /* DP external ECC err sys side */
-#define FMDMSR_DPEXT_FECC	0x00400000 /* DP external ECC err Fman side */
-#define FMDMSR_DPDAT_SECC	0x00200000 /* DP data ECC err on sys side */
-#define FMDMSR_DPDAT_FECC	0x00100000 /* DP data ECC err on Fman side */
-#define FMDMSR_SPDAT_FECC	0x00080000 /* SP data ECC error Fman side */
-
-#define FMDMSR_CLEAR_ALL	(FMDMSR_BER | FMDMSR_RDB_ECC \
-				| FMDMSR_WRB_SECC | FMDMSR_WRB_FECC \
-				| FMDMSR_DPEXT_SECC | FMDMSR_DPEXT_FECC \
-				| FMDMSR_DPDAT_SECC | FMDMSR_DPDAT_FECC \
-				| FMDMSR_SPDAT_FECC)
-
-/* FMDMMR - FMan DMA mode register */
-#define FMDMMR_SBER		0x10000000 /* stop the DMA if a bus error */
-
-typedef struct fm_fpm {
-	u32	fpmtnc;		/* TNUM control */
-	u32	fpmprc;		/* Port_ID control */
-	u32	res0;
-	u32	fpmflc;		/* flush control */
-	u32	fpmdis1;	/* dispatch thresholds1 */
-	u32	fpmdis2;	/* dispatch thresholds2 */
-	u32	fmepi;		/* error pending interrupts */
-	u32	fmrie;		/* rams interrupt enable */
-	u32	fpmfcevent[0x4];/* FMan controller event 0-3 */
-	u32	res1[0x4];
-	u32	fpmfcmask[0x4];	/* FMan controller mask 0-3 */
-	u32	res2[0x4];
-	u32	fpmtsc1;	/* timestamp control1 */
-	u32	fpmtsc2;	/* timestamp control2 */
-	u32	fpmtsp;		/* time stamp */
-	u32	fpmtsf;		/* time stamp fraction */
-	u32	fpmrcr;		/* rams control and event */
-	u32	res3[0x3];
-	u32	fpmdrd[0x4];	/* data_ram data 0-3 */
-	u32	res4[0xc];
-	u32	fpmdra;		/* data ram access */
-	u32	fm_ip_rev_1;	/* IP block revision 1 */
-	u32	fm_ip_rev_2;	/* IP block revision 2 */
-	u32	fmrstc;		/* reset command */
-	u32	fmcld;		/* classifier debug control */
-	u32	fmnpi;		/* normal pending interrupts */
-	u32	res5;
-	u32	fmfpee;		/* event and enable */
-	u32	fpmcev[0x4];	/* CPU event 0-3 */
-	u32	res6[0x4];
-	u32	fmfp_ps[0x40];	/* port status */
-	u32	res7[0x260];
-	u32	fpmts[0x80];	/* task status */
-	u32	res8[0xa0];
-} fm_fpm_t;
-
-/* FMFP_PRC - FPM Port_ID Control Register */
-#define FMFPPRC_PORTID_MASK	0x3f000000
-#define FMFPPRC_PORTID_SHIFT	24
-#define FMFPPRC_ORA_SHIFT	16
-#define FMFPPRC_RISC1		0x00000001
-#define FMFPPRC_RISC2		0x00000002
-#define FMFPPRC_RISC_ALL	(FMFPPRC_RISC1 | FMFPPRC_RSIC2)
-
-/* FPM Flush Control Register */
-#define FMFP_FLC_DISP_LIM_NONE	0x00000000 /* no dispatch limitation */
-
-/* FMFP_EE - FPM event and enable register */
-#define FMFPEE_DECC		0x80000000 /* double ECC err on FPM ram */
-#define FMFPEE_STL		0x40000000 /* stall of task ... */
-#define FMFPEE_SECC		0x20000000 /* single ECC error */
-#define FMFPEE_RFM		0x00010000 /* release FMan */
-#define FMFPEE_DECC_EN		0x00008000 /* double ECC interrupt enable */
-#define FMFPEE_STL_EN		0x00004000 /* stall of task interrupt enable */
-#define FMFPEE_SECC_EN		0x00002000 /* single ECC err interrupt enable */
-#define FMFPEE_EHM		0x00000008 /* external halt enable */
-#define FMFPEE_UEC		0x00000004 /* FMan is not halted */
-#define FMFPEE_CER		0x00000002 /* only errornous task stalled */
-#define FMFPEE_DER		0x00000001 /* DMA error is just reported */
-
-#define FMFPEE_CLEAR_EVENT	(FMFPEE_DECC | FMFPEE_STL | FMFPEE_SECC | \
-				 FMFPEE_EHM | FMFPEE_UEC | FMFPEE_CER | \
-				 FMFPEE_DER | FMFPEE_RFM)
-
-/* FMFP_RCR - FMan Rams Control and Event */
-#define FMFP_RCR_MDEC		0x00008000 /* double ECC error in muram */
-#define FMFP_RCR_IDEC		0x00004000 /* double ECC error in iram */
-
-typedef struct fm_imem {
-	u32	iadd;		/* instruction address register */
-	u32	idata;		/* instruction data register */
-	u32	itcfg;		/* timing config register */
-	u32	iready;		/* ready register */
-	u8	res[0xff0];
-} fm_imem_t;
-#define IRAM_IADD_AIE		0x80000000 /* address auto increase enable */
-#define IRAM_READY		0x80000000 /* ready to use */
-
-typedef struct fm_soft_parser {
-	u8	res[4*1024];
-} fm_soft_parser_t;
-
-typedef struct fm_dtesc {
-	u8	res[4*1024];
-} fm_dtsec_t;
-
-typedef struct fm_mdio {
-	u8	res0[0x120];
-	u32	miimcfg;	/* MII management configuration reg */
-	u32	miimcom;	/* MII management command reg */
-	u32	miimadd;	/* MII management address reg */
-	u32	miimcon;	/* MII management control reg */
-	u32	miimstat;	/* MII management status reg  */
-	u32	miimind;	/* MII management indication reg */
-	u8	res1[0x1000 - 0x138];
-} fm_mdio_t;
-
-typedef struct fm_10gec {
-	u8	res[4*1024];
-} fm_10gec_t;
-
-typedef struct fm_10gec_mdio {
-	u8	res[4*1024];
-} fm_10gec_mdio_t;
-
-typedef struct fm_memac {
-	u8	res[4*1024];
-} fm_memac_t;
-
-typedef struct fm_memac_mdio {
-	u8	res[4*1024];
-} fm_memac_mdio_t;
-
-typedef struct fm_1588 {
-	u8	res[4*1024];
-} fm_1588_t;
-
-typedef struct ccsr_fman {
-	u8			muram[0x80000];
-	fm_bmi_common_t		fm_bmi_common;
-	fm_qmi_common_t		fm_qmi_common;
-	u8			res0[2048];
-	struct {
-		fm_bmi_t	fm_bmi;
-		fm_qmi_t	fm_qmi;
-		fm_parser_t	fm_parser;
-		u8		res[1024];
-	} port[63];
-	fm_policer_t		fm_policer;
-	fm_keygen_t		fm_keygen;
-	fm_dma_t		fm_dma;
-	fm_fpm_t		fm_fpm;
-	fm_imem_t		fm_imem;
-	u8			res1[8*1024];
-	fm_soft_parser_t	fm_soft_parser;
-	u8			res2[96*1024];
-#ifdef CONFIG_SYS_FMAN_V3
-	struct {
-		fm_memac_t		fm_memac;
-		fm_memac_mdio_t		fm_memac_mdio;
-	} memac[10];
-	u8			res4[32*1024];
-	fm_memac_mdio_t		fm_dedicated_mdio[2];
-#else
-	struct {
-		fm_dtsec_t	fm_dtesc;
-		fm_mdio_t	fm_mdio;
-	} mac_1g[8];		/* support up to 8 1g controllers */
-	struct {
-		fm_10gec_t		fm_10gec;
-		fm_10gec_mdio_t		fm_10gec_mdio;
-	} mac_10g[1];
-	u8			res4[48*1024];
-#endif
-	fm_1588_t		fm_1588;
-	u8			res5[4*1024];
-} ccsr_fman_t;
-
-#endif /*__FSL_FMAN_H__*/
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index 3b504875e0..8e1d22adef 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -10,6 +10,7 @@
 #define _FSL_LAW_H_
 
 #include <asm/io.h>
+#include <linux/log2.h>
 
 #define LAW_EN	0x80000000
 
diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h
index e5aab2a71f..ec25e16829 100644
--- a/arch/powerpc/include/asm/fsl_srio.h
+++ b/arch/powerpc/include/asm/fsl_srio.h
@@ -7,6 +7,8 @@
 #ifndef _FSL_SRIO_H_
 #define _FSL_SRIO_H_
 
+#include <linux/log2.h>
+
 enum atmu_size {
 	ATMU_SIZE_4K = 0xb,
 	ATMU_SIZE_8K,
diff --git a/arch/powerpc/include/asm/fsl_tgec.h b/arch/powerpc/include/asm/fsl_tgec.h
deleted file mode 100644
index 92fb777c25..0000000000
--- a/arch/powerpc/include/asm/fsl_tgec.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *	Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __TGEC_H__
-#define __TGEC_H__
-
-#include <phy.h>
-
-struct tgec {
-	/* 10GEC general control and status registers */
-	u32	tgec_id;	/* Controller ID register */
-	u32	res0;
-	u32	command_config;	/* Control and configuration register */
-	u32	mac_addr_0;	/* Lower 32 bits of 48-bit MAC address */
-	u32	mac_addr_1;	/* Upper 16 bits of 48-bit MAC address */
-	u32	maxfrm;		/* Maximum frame length register */
-	u32	pause_quant;	/* Pause quanta register */
-	u32	res1[4];
-	u32	hashtable_ctrl;	/* Hash table control register */
-	u32	res2[4];
-	u32	status;		/* MAC status register */
-	u32	tx_ipg_length;	/* Transmitter inter-packet-gap register */
-	u32	mac_addr_2;	/* Lower 32 bits of the 2nd 48-bit MAC addr */
-	u32	mac_addr_3;	/* Upper 16 bits of the 2nd 48-bit MAC addr */
-	u32	res3[4];
-	u32	imask;		/* Interrupt mask register */
-	u32	ievent;		/* Interrupt event register */
-	u32	res4[6];
-	/* 10GEC statistics counter registers */
-	u32	tx_frame_u;	/* Tx frame counter upper */
-	u32	tx_frame_l;	/* Tx frame counter lower */
-	u32	rx_frame_u;	/* Rx frame counter upper */
-	u32	rx_frame_l;	/* Rx frame counter lower */
-	u32	rx_frame_crc_err_u; /* Rx frame check sequence error upper */
-	u32	rx_frame_crc_err_l; /* Rx frame check sequence error lower */
-	u32	rx_align_err_u;	/* Rx alignment error upper */
-	u32	rx_align_err_l;	/* Rx alignment error lower */
-	u32	tx_pause_frame_u; /* Tx valid pause frame upper */
-	u32	tx_pause_frame_l; /* Tx valid pause frame lower */
-	u32	rx_pause_frame_u; /* Rx valid pause frame upper */
-	u32	rx_pause_frame_l; /* Rx valid pause frame upper */
-	u32	rx_long_err_u;	/* Rx too long frame error upper */
-	u32	rx_long_err_l;	/* Rx too long frame error lower */
-	u32	rx_frame_err_u;	/* Rx frame length error upper */
-	u32	rx_frame_err_l;	/* Rx frame length error lower */
-	u32	tx_vlan_u;	/* Tx VLAN frame upper */
-	u32	tx_vlan_l;	/* Tx VLAN frame lower */
-	u32	rx_vlan_u;	/* Rx VLAN frame upper */
-	u32	rx_vlan_l;	/* Rx VLAN frame lower */
-	u32	tx_oct_u;	/* Tx octets upper */
-	u32	tx_oct_l;	/* Tx octets lower */
-	u32	rx_oct_u;	/* Rx octets upper */
-	u32	rx_oct_l;	/* Rx octets lower */
-	u32	rx_uni_u;	/* Rx unicast frame upper */
-	u32	rx_uni_l;	/* Rx unicast frame lower */
-	u32	rx_multi_u;	/* Rx multicast frame upper */
-	u32	rx_multi_l;	/* Rx multicast frame lower */
-	u32	rx_brd_u;	/* Rx broadcast frame upper */
-	u32	rx_brd_l;	/* Rx broadcast frame lower */
-	u32	tx_frame_err_u;	/* Tx frame error upper */
-	u32	tx_frame_err_l;	/* Tx frame error lower */
-	u32	tx_uni_u;	/* Tx unicast frame upper */
-	u32	tx_uni_l;	/* Tx unicast frame lower */
-	u32	tx_multi_u;	/* Tx multicast frame upper */
-	u32	tx_multi_l;	/* Tx multicast frame lower */
-	u32	tx_brd_u;	/* Tx broadcast frame upper */
-	u32	tx_brd_l;	/* Tx broadcast frame lower */
-	u32	rx_drop_u;	/* Rx dropped packets upper */
-	u32	rx_drop_l;	/* Rx dropped packets lower */
-	u32	rx_eoct_u;	/* Rx ethernet octets upper */
-	u32	rx_eoct_l;	/* Rx ethernet octets lower */
-	u32	rx_pkt_u;	/* Rx packets upper */
-	u32	rx_pkt_l;	/* Rx packets lower */
-	u32	tx_undsz_u;	/* Undersized packet upper */
-	u32	tx_undsz_l;	/* Undersized packet lower */
-	u32	rx_64_u;	/* Rx 64 oct packet upper */
-	u32	rx_64_l;	/* Rx 64 oct packet lower */
-	u32	rx_127_u;	/* Rx 65 to 127 oct packet upper */
-	u32	rx_127_l;	/* Rx 65 to 127 oct packet lower */
-	u32	rx_255_u;	/* Rx 128 to 255 oct packet upper */
-	u32	rx_255_l;	/* Rx 128 to 255 oct packet lower */
-	u32	rx_511_u;	/* Rx 256 to 511 oct packet upper */
-	u32	rx_511_l;	/* Rx 256 to 511 oct packet lower */
-	u32	rx_1023_u;	/* Rx 512 to 1023 oct packet upper */
-	u32	rx_1023_l;	/* Rx 512 to 1023 oct packet lower */
-	u32	rx_1518_u;	/* Rx 1024 to 1518 oct packet upper */
-	u32	rx_1518_l;	/* Rx 1024 to 1518 oct packet lower */
-	u32	rx_1519_u;	/* Rx 1519 to max oct packet upper */
-	u32	rx_1519_l;	/* Rx 1519 to max oct packet lower */
-	u32	tx_oversz_u;	/* oversized packet upper */
-	u32	tx_oversz_l;	/* oversized packet lower */
-	u32	tx_jabber_u;	/* Jabber packet upper */
-	u32	tx_jabber_l;	/* Jabber packet lower */
-	u32	tx_frag_u;	/* Fragment packet upper */
-	u32	tx_frag_l;	/* Fragment packet lower */
-	u32	rx_err_u;	/* Rx frame error upper */
-	u32	rx_err_l;	/* Rx frame error lower */
-	u32	res5[0x39a];
-};
-
-/* EC10G_ID - 10-gigabit ethernet MAC controller ID */
-#define EC10G_ID_VER_MASK	0x0000ff00
-#define EC10G_ID_VER_SHIFT	8
-#define EC10G_ID_REV_MASK	0x000000ff
-
-/* COMMAND_CONFIG - command and configuration register */
-#define TGEC_CMD_CFG_EN_TIMESTAMP	0x00100000 /* enable IEEE1588 */
-#define TGEC_CMD_CFG_TX_ADDR_INS_SEL	0x00080000 /* Tx mac addr w/ second */
-#define TGEC_CMD_CFG_NO_LEN_CHK		0x00020000 /* payload len chk disable */
-#define TGEC_CMD_CFG_SEND_IDLE		0x00010000 /* send XGMII idle seqs */
-#define TGEC_CMD_CFG_RX_ER_DISC		0x00004000 /* Rx err frm discard enb */
-#define TGEC_CMD_CFG_CMD_FRM_EN		0x00002000 /* CMD frame RX enable */
-#define TGEC_CMD_CFG_STAT_CLR		0x00001000 /* clear stats */
-#define TGEC_CMD_CFG_TX_ADDR_INS	0x00000200 /* overwrite src MAC addr */
-#define TGEC_CMD_CFG_PAUSE_IGNORE	0x00000100 /* ignore pause frames */
-#define TGEC_CMD_CFG_PAUSE_FWD		0x00000080 /* fwd pause frames */
-#define TGEC_CMD_CFG_CRC_FWD		0x00000040 /* fwd Rx CRC frames */
-#define TGEC_CMD_CFG_PAD_EN		0x00000020 /* MAC remove Rx padding */
-#define TGEC_CMD_CFG_PROM_EN		0x00000010 /* promiscuous mode enable */
-#define TGEC_CMD_CFG_WAN_MODE		0x00000008 /* WAN mode enable */
-#define TGEC_CMD_CFG_RX_EN		0x00000002 /* MAC Rx path enable */
-#define TGEC_CMD_CFG_TX_EN		0x00000001 /* MAC Tx path enable */
-#define TGEC_CMD_CFG_RXTX_EN	(TGEC_CMD_CFG_RX_EN | TGEC_CMD_CFG_TX_EN)
-
-/* HASHTABLE_CTRL - Hashtable control register */
-#define HASHTABLE_CTRL_MCAST_EN	0x00000200 /* enable mulitcast Rx hash */
-#define HASHTABLE_CTRL_ADDR_MASK	0x000001ff
-
-/* TX_IPG_LENGTH - Transmit inter-packet gap length register */
-#define TX_IPG_LENGTH_IPG_LEN_MASK	0x000003ff
-
-/* IMASK - interrupt mask register */
-#define IMASK_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event mask */
-#define IMASK_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion mask */
-#define IMASK_REM_FAULT		0x00004000 /* remote fault mask */
-#define IMASK_LOC_FAULT		0x00002000 /* local fault mask */
-#define IMASK_TX_ECC_ER		0x00001000 /* Tx frame ECC error mask */
-#define IMASK_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow mask */
-#define IMASK_TX_ER		0x00000200 /* Tx frame error mask */
-#define IMASK_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow mask */
-#define IMASK_RX_ECC_ER		0x00000080 /* Rx frame ECC error mask */
-#define IMASK_RX_JAB_FRM	0x00000040 /* Rx jabber frame mask */
-#define IMASK_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame mask */
-#define IMASK_RX_RUNT_FRM	0x00000010 /* Rx runt frame mask */
-#define IMASK_RX_FRAG_FRM	0x00000008 /* Rx fragment frame mask */
-#define IMASK_RX_LEN_ER		0x00000004 /* Rx payload length error mask */
-#define IMASK_RX_CRC_ER		0x00000002 /* Rx CRC error mask */
-#define IMASK_RX_ALIGN_ER	0x00000001 /* Rx alignment error mask */
-
-#define IMASK_MASK_ALL		0x00000000
-
-/* IEVENT - interrupt event register */
-#define IEVENT_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event */
-#define IEVENT_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion */
-#define IEVENT_REM_FAULT	0x00004000 /* remote fault */
-#define IEVENT_LOC_FAULT	0x00002000 /* local fault */
-#define IEVENT_TX_ECC_ER	0x00001000 /* Tx frame ECC error */
-#define IEVENT_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow */
-#define IEVENT_TX_ER		0x00000200 /* Tx frame error */
-#define IEVENT_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow */
-#define IEVENT_RX_ECC_ER	0x00000080 /* Rx frame ECC error */
-#define IEVENT_RX_JAB_FRM	0x00000040 /* Rx jabber frame */
-#define IEVENT_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame */
-#define IEVENT_RX_RUNT_FRM	0x00000010 /* Rx runt frame */
-#define IEVENT_RX_FRAG_FRM	0x00000008 /* Rx fragment frame */
-#define IEVENT_RX_LEN_ER	0x00000004 /* Rx payload length error */
-#define IEVENT_RX_CRC_ER	0x00000002 /* Rx CRC error */
-#define IEVENT_RX_ALIGN_ER	0x00000001 /* Rx alignment error */
-
-#define IEVENT_CLEAR_ALL	0xffffffff
-
-struct tgec_mdio_controller {
-	u32	res0[0xc];
-	u32	mdio_stat;	/* MDIO configuration and status */
-	u32	mdio_ctl;	/* MDIO control */
-	u32	mdio_data;	/* MDIO data */
-	u32	mdio_addr;	/* MDIO address */
-};
-
-#define MDIO_STAT_CLKDIV(x)	(((x>>1) & 0xff) << 8)
-#define MDIO_STAT_BSY		(1 << 0)
-#define MDIO_STAT_RD_ER		(1 << 1)
-#define MDIO_CTL_DEV_ADDR(x)	(x & 0x1f)
-#define MDIO_CTL_PORT_ADDR(x)	((x & 0x1f) << 5)
-#define MDIO_CTL_PRE_DIS	(1 << 10)
-#define MDIO_CTL_SCAN_EN	(1 << 11)
-#define MDIO_CTL_POST_INC	(1 << 14)
-#define MDIO_CTL_READ		(1 << 15)
-
-#define MDIO_DATA(x)		(x & 0xffff)
-#define MDIO_DATA_BSY		(1 << 31)
-
-struct fsl_enet_mac;
-
-void init_tgec(struct fsl_enet_mac *mac, void *base, void *phyregs,
-		int max_rx_len);
-
-#endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 0c9d85ec96..101b8db0ee 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -19,7 +19,7 @@
 #include <fsl_sec.h>
 #include <fsl_sfp.h>
 #include <asm/fsl_lbc.h>
-#include <asm/fsl_fman.h>
+#include <fsl_fman.h>
 #include <fsl_immap.h>
 
 typedef struct ccsr_local {
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index a5257e9b62..a54fc468d5 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -163,7 +163,7 @@ static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
  * is actually performed (i.e. the data has come back) before we start
  * executing any following instructions.
  */
-extern inline u8 in_8(const volatile unsigned char __iomem *addr)
+static inline u8 in_8(const volatile unsigned char __iomem *addr)
 {
 	u8 ret;
 
@@ -174,7 +174,7 @@ extern inline u8 in_8(const volatile unsigned char __iomem *addr)
 	return ret;
 }
 
-extern inline void out_8(volatile unsigned char __iomem *addr, u8 val)
+static inline void out_8(volatile unsigned char __iomem *addr, u8 val)
 {
 	__asm__ __volatile__("sync;\n"
 			     "stb%U0%X0 %1,%0;\n"
@@ -182,7 +182,7 @@ extern inline void out_8(volatile unsigned char __iomem *addr, u8 val)
 			     : "r" (val));
 }
 
-extern inline u16 in_le16(const volatile unsigned short __iomem *addr)
+static inline u16 in_le16(const volatile unsigned short __iomem *addr)
 {
 	u16 ret;
 
@@ -193,7 +193,7 @@ extern inline u16 in_le16(const volatile unsigned short __iomem *addr)
 	return ret;
 }
 
-extern inline u16 in_be16(const volatile unsigned short __iomem *addr)
+static inline u16 in_be16(const volatile unsigned short __iomem *addr)
 {
 	u16 ret;
 
@@ -203,18 +203,18 @@ extern inline u16 in_be16(const volatile unsigned short __iomem *addr)
 	return ret;
 }
 
-extern inline void out_le16(volatile unsigned short __iomem *addr, u16 val)
+static inline void out_le16(volatile unsigned short __iomem *addr, u16 val)
 {
 	__asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
 			      "r" (val), "r" (addr));
 }
 
-extern inline void out_be16(volatile unsigned short __iomem *addr, u16 val)
+static inline void out_be16(volatile unsigned short __iomem *addr, u16 val)
 {
 	__asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
 }
 
-extern inline u32 in_le32(const volatile unsigned __iomem *addr)
+static inline u32 in_le32(const volatile unsigned __iomem *addr)
 {
 	u32 ret;
 
@@ -225,7 +225,7 @@ extern inline u32 in_le32(const volatile unsigned __iomem *addr)
 	return ret;
 }
 
-extern inline u32 in_be32(const volatile unsigned __iomem *addr)
+static inline u32 in_be32(const volatile unsigned __iomem *addr)
 {
 	u32 ret;
 
@@ -235,13 +235,13 @@ extern inline u32 in_be32(const volatile unsigned __iomem *addr)
 	return ret;
 }
 
-extern inline void out_le32(volatile unsigned __iomem *addr, u32 val)
+static inline void out_le32(volatile unsigned __iomem *addr, u32 val)
 {
 	__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
 			     "r" (val), "r" (addr));
 }
 
-extern inline void out_be32(volatile unsigned __iomem *addr, u32 val)
+static inline void out_be32(volatile unsigned __iomem *addr, u32 val)
 {
 	__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
 }
diff --git a/arch/powerpc/include/asm/iopin_8260.h b/arch/powerpc/include/asm/iopin_8260.h
index 619f3a8abe..617584d7c7 100644
--- a/arch/powerpc/include/asm/iopin_8260.h
+++ b/arch/powerpc/include/asm/iopin_8260.h
@@ -23,140 +23,140 @@ iopin_t;
 #define IOPIN_PORTC	2
 #define IOPIN_PORTD	3
 
-extern __inline__ void
+static __inline__ void
 iopin_set_high(iopin_t *iopin)
 {
     volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
     datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_low(iopin_t *iopin)
 {
     volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
     datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_high(iopin_t *iopin)
 {
     volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
     return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_low(iopin_t *iopin)
 {
     volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
     return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_out(iopin_t *iopin)
 {
     volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
     dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_in(iopin_t *iopin)
 {
     volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
     dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_out(iopin_t *iopin)
 {
     volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
     return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_in(iopin_t *iopin)
 {
     volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
     return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_odr(iopin_t *iopin)
 {
     volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
     odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_act(iopin_t *iopin)
 {
     volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
     odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_odr(iopin_t *iopin)
 {
     volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
     return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_act(iopin_t *iopin)
 {
     volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
     return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_ded(iopin_t *iopin)
 {
     volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
     parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_gen(iopin_t *iopin)
 {
     volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
     parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_ded(iopin_t *iopin)
 {
     volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
     return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_gen(iopin_t *iopin)
 {
     volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
     return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_opt2(iopin_t *iopin)
 {
     volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
     sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_opt1(iopin_t *iopin)
 {
     volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
     sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_opt2(iopin_t *iopin)
 {
     volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
     return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_opt1(iopin_t *iopin)
 {
     volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
diff --git a/arch/powerpc/include/asm/iopin_8xx.h b/arch/powerpc/include/asm/iopin_8xx.h
index 0123bafcad..8db0fa2a1c 100644
--- a/arch/powerpc/include/asm/iopin_8xx.h
+++ b/arch/powerpc/include/asm/iopin_8xx.h
@@ -26,7 +26,7 @@ typedef struct {
 #define IOPIN_PORTC	2
 #define IOPIN_PORTD	3
 
-extern __inline__ void
+static __inline__ void
 iopin_set_high(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
@@ -44,7 +44,7 @@ iopin_set_high(iopin_t *iopin)
 	}
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_low(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
@@ -62,7 +62,7 @@ iopin_set_low(iopin_t *iopin)
 	}
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_high(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
@@ -81,7 +81,7 @@ iopin_is_high(iopin_t *iopin)
 	return 0;
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_low(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
@@ -100,7 +100,7 @@ iopin_is_low(iopin_t *iopin)
 	return 0;
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_out(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
@@ -118,7 +118,7 @@ iopin_set_out(iopin_t *iopin)
 	}
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_in(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
@@ -136,7 +136,7 @@ iopin_set_in(iopin_t *iopin)
 	}
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_out(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
@@ -155,7 +155,7 @@ iopin_is_out(iopin_t *iopin)
 	return 0;
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_in(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
@@ -174,7 +174,7 @@ iopin_is_in(iopin_t *iopin)
 	return 0;
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_odr(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
@@ -186,7 +186,7 @@ iopin_set_odr(iopin_t *iopin)
 	}
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_act(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
@@ -198,7 +198,7 @@ iopin_set_act(iopin_t *iopin)
 	}
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_odr(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
@@ -211,7 +211,7 @@ iopin_is_odr(iopin_t *iopin)
 	return 0;
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_act(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
@@ -224,7 +224,7 @@ iopin_is_act(iopin_t *iopin)
 	return 0;
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_ded(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
@@ -242,7 +242,7 @@ iopin_set_ded(iopin_t *iopin)
 	}
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_gen(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
@@ -260,7 +260,7 @@ iopin_set_gen(iopin_t *iopin)
 	}
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_ded(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
@@ -279,7 +279,7 @@ iopin_is_ded(iopin_t *iopin)
 	return 0;
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_gen(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
@@ -298,7 +298,7 @@ iopin_is_gen(iopin_t *iopin)
 	return 0;
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_opt2(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTC) {
@@ -307,7 +307,7 @@ iopin_set_opt2(iopin_t *iopin)
 	}
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_opt1(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTC) {
@@ -316,7 +316,7 @@ iopin_set_opt1(iopin_t *iopin)
 	}
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_opt2(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTC) {
@@ -326,7 +326,7 @@ iopin_is_opt2(iopin_t *iopin)
 	return 0;
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_opt1(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTC) {
@@ -336,7 +336,7 @@ iopin_is_opt1(iopin_t *iopin)
 	return 0;
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_falledge(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTC) {
@@ -345,7 +345,7 @@ iopin_set_falledge(iopin_t *iopin)
 	}
 }
 
-extern __inline__ void
+static __inline__ void
 iopin_set_anyedge(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTC) {
@@ -354,7 +354,7 @@ iopin_set_anyedge(iopin_t *iopin)
 	}
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_falledge(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTC) {
@@ -364,7 +364,7 @@ iopin_is_falledge(iopin_t *iopin)
 	return 0;
 }
 
-extern __inline__ uint
+static __inline__ uint
 iopin_is_anyedge(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTC) {
diff --git a/arch/sandbox/dts/Makefile b/arch/sandbox/dts/Makefile
index 517b555475..0197569262 100644
--- a/arch/sandbox/dts/Makefile
+++ b/arch/sandbox/dts/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 dtb-$(CONFIG_SANDBOX) += sandbox.dtb
 dtb-$(CONFIG_UT_DM) += test.dtb
 
diff --git a/arch/sandbox/dts/sandbox_pmic.dtsi b/arch/sandbox/dts/sandbox_pmic.dtsi
index 44a26b18ca..ce261b930e 100644
--- a/arch/sandbox/dts/sandbox_pmic.dtsi
+++ b/arch/sandbox/dts/sandbox_pmic.dtsi
@@ -55,7 +55,7 @@
 		regulator-always-on;
 	};
 
-	buck2 {
+	buck2: buck2 {
 		regulator-name = "SUPPLY_3.3V";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 730de8a57f..e2c4971d74 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -189,6 +189,12 @@
 		};
 	};
 
+	adc@0 {
+		compatible = "sandbox,adc";
+		vdd-supply = <&buck2>;
+		vss-microvolts = <0>;
+	};
+
 	leds {
 		compatible = "gpio-leds";
 
diff --git a/arch/sandbox/include/asm/bitops.h b/arch/sandbox/include/asm/bitops.h
index f1a7aeee93..f27d5e98c5 100644
--- a/arch/sandbox/include/asm/bitops.h
+++ b/arch/sandbox/include/asm/bitops.h
@@ -21,6 +21,10 @@
 
 #include <linux/compiler.h>
 #include <asm/system.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
 
 #ifdef __KERNEL__
 
diff --git a/arch/sh/include/asm/bitops.h b/arch/sh/include/asm/bitops.h
index c57d628478..8cb8385d76 100644
--- a/arch/sh/include/asm/bitops.h
+++ b/arch/sh/include/asm/bitops.h
@@ -1,6 +1,11 @@
 #ifndef __ASM_SH_BITOPS_H
 #define __ASM_SH_BITOPS_H
 
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
 #ifdef __KERNEL__
 #include <asm/irqflags.h>
 /* For __swab32 */
diff --git a/arch/sparc/include/asm/bitops.h b/arch/sparc/include/asm/bitops.h
index fa39fa3fc6..c66f730c88 100644
--- a/arch/sparc/include/asm/bitops.h
+++ b/arch/sparc/include/asm/bitops.h
@@ -9,4 +9,9 @@
 #ifndef _SPARC_BITOPS_H
 #define _SPARC_BITOPS_H
 
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
 #endif				/* _SPARC_BITOPS_H */
diff --git a/arch/sparc/include/asm/irq.h b/arch/sparc/include/asm/irq.h
index bbe0204387..2faf7a074e 100644
--- a/arch/sparc/include/asm/irq.h
+++ b/arch/sparc/include/asm/irq.h
@@ -12,7 +12,7 @@
 #include <asm/psr.h>
 
 /* Set SPARC Processor Interrupt Level */
-extern inline void set_pil(unsigned int level)
+static inline void set_pil(unsigned int level)
 {
 	unsigned int psr = get_psr();
 
@@ -20,7 +20,7 @@ extern inline void set_pil(unsigned int level)
 }
 
 /* Get SPARC Processor Interrupt Level */
-extern inline unsigned int get_pil(void)
+static inline unsigned int get_pil(void)
 {
 	unsigned int psr = get_psr();
 	return (psr & PSR_PIL) >> PSR_PIL_OFS;
diff --git a/arch/sparc/include/asm/psr.h b/arch/sparc/include/asm/psr.h
index 70af8e0f54..a91bdc903c 100644
--- a/arch/sparc/include/asm/psr.h
+++ b/arch/sparc/include/asm/psr.h
@@ -42,7 +42,7 @@
 
 #ifndef __ASSEMBLY__
 /* Get the %psr register. */
-extern __inline__ unsigned int get_psr(void)
+static __inline__ unsigned int get_psr(void)
 {
 	unsigned int psr;
 	__asm__ __volatile__("rd	%%psr, %0\n\t"
@@ -53,7 +53,7 @@ extern __inline__ unsigned int get_psr(void)
 	return psr;
 }
 
-extern __inline__ void put_psr(unsigned int new_psr)
+static __inline__ void put_psr(unsigned int new_psr)
 {
 	__asm__ __volatile__("wr	%0, 0x0, %%psr\n\t" "nop\n\t" "nop\n\t" "nop\n\t":	/* no outputs */
 			     :"r"(new_psr)
@@ -67,7 +67,7 @@ extern __inline__ void put_psr(unsigned int new_psr)
 
 extern unsigned int fsr_storage;
 
-extern __inline__ unsigned int get_fsr(void)
+static __inline__ unsigned int get_fsr(void)
 {
 	unsigned int fsr = 0;
 
diff --git a/arch/sparc/include/asm/srmmu.h b/arch/sparc/include/asm/srmmu.h
index 74b15549fa..8da2f67f1c 100644
--- a/arch/sparc/include/asm/srmmu.h
+++ b/arch/sparc/include/asm/srmmu.h
@@ -148,7 +148,7 @@ extern void *srmmu_nocache_pool;
 #define __nocache_fix(VADDR) __va(__nocache_pa(VADDR))
 
 /* Accessing the MMU control register. */
-extern __inline__ unsigned int srmmu_get_mmureg(void)
+static __inline__ unsigned int srmmu_get_mmureg(void)
 {
 	unsigned int retval;
 	__asm__ __volatile__("lda [%%g0] %1, %0\n\t":
@@ -156,14 +156,14 @@ extern __inline__ unsigned int srmmu_get_mmureg(void)
 	return retval;
 }
 
-extern __inline__ void srmmu_set_mmureg(unsigned long regval)
+static __inline__ void srmmu_set_mmureg(unsigned long regval)
 {
 	__asm__ __volatile__("sta %0, [%%g0] %1\n\t"::"r"(regval),
 			     "i"(ASI_M_MMUREGS):"memory");
 
 }
 
-extern __inline__ void srmmu_set_ctable_ptr(unsigned long paddr)
+static __inline__ void srmmu_set_ctable_ptr(unsigned long paddr)
 {
 	paddr = ((paddr >> 4) & SRMMU_CTX_PMASK);
 	__asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(paddr),
@@ -171,7 +171,7 @@ extern __inline__ void srmmu_set_ctable_ptr(unsigned long paddr)
 			     "i"(ASI_M_MMUREGS):"memory");
 }
 
-extern __inline__ unsigned long srmmu_get_ctable_ptr(void)
+static __inline__ unsigned long srmmu_get_ctable_ptr(void)
 {
 	unsigned int retval;
 
@@ -181,13 +181,13 @@ extern __inline__ unsigned long srmmu_get_ctable_ptr(void)
 	return (retval & SRMMU_CTX_PMASK) << 4;
 }
 
-extern __inline__ void srmmu_set_context(int context)
+static __inline__ void srmmu_set_context(int context)
 {
 	__asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(context),
 			     "r"(SRMMU_CTX_REG), "i"(ASI_M_MMUREGS):"memory");
 }
 
-extern __inline__ int srmmu_get_context(void)
+static __inline__ int srmmu_get_context(void)
 {
 	register int retval;
 	__asm__ __volatile__("lda [%1] %2, %0\n\t":
@@ -196,7 +196,7 @@ extern __inline__ int srmmu_get_context(void)
 	return retval;
 }
 
-extern __inline__ unsigned int srmmu_get_fstatus(void)
+static __inline__ unsigned int srmmu_get_fstatus(void)
 {
 	unsigned int retval;
 
@@ -206,7 +206,7 @@ extern __inline__ unsigned int srmmu_get_fstatus(void)
 	return retval;
 }
 
-extern __inline__ unsigned int srmmu_get_faddr(void)
+static __inline__ unsigned int srmmu_get_faddr(void)
 {
 	unsigned int retval;
 
@@ -217,7 +217,7 @@ extern __inline__ unsigned int srmmu_get_faddr(void)
 }
 
 /* This is guaranteed on all SRMMU's. */
-extern __inline__ void srmmu_flush_whole_tlb(void)
+static __inline__ void srmmu_flush_whole_tlb(void)
 {
 	__asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x400),	/* Flush entire TLB!! */
 			     "i"(ASI_M_FLUSH_PROBE):"memory");
@@ -225,14 +225,14 @@ extern __inline__ void srmmu_flush_whole_tlb(void)
 }
 
 /* These flush types are not available on all chips... */
-extern __inline__ void srmmu_flush_tlb_ctx(void)
+static __inline__ void srmmu_flush_tlb_ctx(void)
 {
 	__asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x300),	/* Flush TLB ctx.. */
 			     "i"(ASI_M_FLUSH_PROBE):"memory");
 
 }
 
-extern __inline__ void srmmu_flush_tlb_region(unsigned long addr)
+static __inline__ void srmmu_flush_tlb_region(unsigned long addr)
 {
 	addr &= SRMMU_PGDIR_MASK;
 	__asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(addr | 0x200),	/* Flush TLB region.. */
@@ -240,7 +240,7 @@ extern __inline__ void srmmu_flush_tlb_region(unsigned long addr)
 
 }
 
-extern __inline__ void srmmu_flush_tlb_segment(unsigned long addr)
+static __inline__ void srmmu_flush_tlb_segment(unsigned long addr)
 {
 	addr &= SRMMU_REAL_PMD_MASK;
 	__asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(addr | 0x100),	/* Flush TLB segment.. */
@@ -248,7 +248,7 @@ extern __inline__ void srmmu_flush_tlb_segment(unsigned long addr)
 
 }
 
-extern __inline__ void srmmu_flush_tlb_page(unsigned long page)
+static __inline__ void srmmu_flush_tlb_page(unsigned long page)
 {
 	page &= PAGE_MASK;
 	__asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(page),	/* Flush TLB page.. */
@@ -256,7 +256,7 @@ extern __inline__ void srmmu_flush_tlb_page(unsigned long page)
 
 }
 
-extern __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr)
+static __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr)
 {
 	unsigned long retval;
 
@@ -268,7 +268,7 @@ extern __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr)
 	return retval;
 }
 
-extern __inline__ int srmmu_get_pte(unsigned long addr)
+static __inline__ int srmmu_get_pte(unsigned long addr)
 {
 	register unsigned long entry;
 
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 83a2b8c1cf..64e569432c 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
 dtb-y += bayleybay.dtb \
 	chromebook_link.dtb \
 	chromebox_panther.dtb \
diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h
index 5a7e4cba2b..f97dc66439 100644
--- a/arch/x86/include/asm/bitops.h
+++ b/arch/x86/include/asm/bitops.h
@@ -14,6 +14,10 @@
  * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
  */
 
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+
 #ifdef CONFIG_SMP
 #define LOCK_PREFIX "lock ; "
 #else
@@ -332,6 +336,20 @@ static __inline__ unsigned long ffz(unsigned long word)
 #ifdef __KERNEL__
 
 /**
+ * __ffs - find first set bit in word
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static inline unsigned long __ffs(unsigned long word)
+{
+	__asm__("rep; bsf %1,%0"
+		: "=r" (word)
+		: "rm" (word));
+	return word;
+}
+
+/**
  * ffs - find first bit set
  * @x: the word to search
  *
@@ -346,7 +364,8 @@ static __inline__ int ffs(int x)
 	__asm__("bsfl %1,%0\n\t"
 		"jnz 1f\n\t"
 		"movl $-1,%0\n"
-		"1:" : "=r" (r) : "g" (x));
+		"1:" : "=r" (r) : "rm" (x));
+
 	return r+1;
 }
 #define PLATFORM_FFS
author	Stefano Babic <sbabic@denx.de>	2015-11-12 17:13:26 +0100
committer	Stefano Babic <sbabic@denx.de>	2015-11-12 17:13:26 +0100
commit	5f5620ab2679608f94b3a77e51c77d0a770103bd (patch)
tree	ec983c06d2f62384909968bb870add121b8a1502 /arch
parent	78e9ca52edaab74ad645d719676ff4c24d2f462c (diff)
parent	038be18fd95aa6283eafb85ceabc0b880976424b (diff)