diff options
author | Shengzhou Liu <Shengzhou.Liu@nxp.com> | 2016-09-07 17:56:11 +0800 |
---|---|---|
committer | York Sun <york.sun@nxp.com> | 2016-09-14 14:10:44 -0700 |
commit | 5f5e8d92d56fb6d6bd792b067fe8931259d1b99a (patch) | |
tree | 4b023f24304ccd57b14076fa5c6a0d14fe2f357b /arch | |
parent | caa6e9b03aed3b5c9d1a0dfbec59391d646592a0 (diff) |
armv8: ls1046a: Enable DDR erratum for ls1046a
Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index b27087df78..81a5e7c6cf 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -240,6 +240,12 @@ #define GICC_BASE 0x01420000 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + +#define CONFIG_SYS_FSL_ERRATUM_A008511 +#define CONFIG_SYS_FSL_ERRATUM_A009801 +#define CONFIG_SYS_FSL_ERRATUM_A009803 +#define CONFIG_SYS_FSL_ERRATUM_A009942 +#define CONFIG_SYS_FSL_ERRATUM_A010165 #else #error SoC not defined #endif |