diff options
| author | Thomas Chou <thomas@wytron.com.tw> | 2015-09-09 13:08:05 +0800 |
|---|---|---|
| committer | Thomas Chou <thomas@wytron.com.tw> | 2015-10-23 07:28:50 +0800 |
| commit | 651389a0558ac8062076d8192faa2cadf0e6ee07 (patch) | |
| tree | 7524e4e97f95e7a6a8fba697f120c25617ba10fb /arch | |
| parent | e6500f86a6ddac4c4a2cfcbd517283665563ef70 (diff) | |
nios2: zap dly_clks
The dly_clks() in start.S is no use after switching to
generic timer. Remove it.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/nios2/cpu/start.S | 33 |
1 files changed, 0 insertions, 33 deletions
diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index f80b4f3a52..e92f06e530 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -175,39 +175,6 @@ relocate_code: callr r8 ret -/* - * dly_clks -- Nios2 (like Nios1) doesn't have a timebase in - * the core. For simple delay loops, we do our best by counting - * instruction cycles. - * - * Instruction performance varies based on the core. For cores - * with icache and static/dynamic branch prediction (II/f, II/s): - * - * Normal ALU (e.g. add, cmp, etc): 1 cycle - * Branch (correctly predicted, taken): 2 cycles - * Negative offset is predicted (II/s). - * - * For cores without icache and no branch prediction (II/e): - * - * Normal ALU (e.g. add, cmp, etc): 6 cycles - * Branch (no prediction): 6 cycles - * - * For simplicity, if an instruction cache is implemented we - * assume II/f or II/s. Otherwise, we use the II/e. - * - */ - .globl dly_clks - -dly_clks: - -#if (CONFIG_SYS_ICACHE_SIZE > 0) - subi r4, r4, 3 /* 3 clocks/loop */ -#else - subi r4, r4, 12 /* 12 clocks/loop */ -#endif - bge r4, r0, dly_clks - ret - .data .globl version_string |