diff options
| author | Ruchika Gupta <ruchika.gupta@freescale.com> | 2014-09-29 11:35:33 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-10-16 14:17:42 -0700 |
| commit | 7cad2e38d61e27ea59fb7944f7e647e97ef292d3 (patch) | |
| tree | 315fab51b9302a8977f19cfc8cb1b5cddbbb0af4 /arch | |
| parent | 4ba4a095da4f7d38270ee22cc1a1ce64fa47d009 (diff) | |
powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure boot
By default, PAMU's (IOMMU) are enabled in case of secure boot.
Disable/bypass them once the control reaches the bootloader.
For non-secure boot, PAMU's are already bypassed in the default
SoC configuration.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 1 |
2 files changed, 9 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 963e32676b..85d32fc612 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -426,7 +426,8 @@ ulong cpu_init_f(void) { ulong flag = 0; extern void m8560_cpm_reset (void); -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \ + (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_SECURE_BOOT) @@ -458,6 +459,12 @@ ulong cpu_init_f(void) #if defined(CONFIG_SYS_CPC_REINIT_F) disable_cpc_sram(); #endif + +#if defined(CONFIG_FSL_CORENET) + /* Put PAMU in bypass mode */ + out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS); +#endif + #endif #ifdef CONFIG_CPM2 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 88c1e08df5..0264523d64 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1912,6 +1912,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) u8 res24[64]; u32 pblsr; /* Preboot loader status */ u32 pamubypenr; /* PAMU bypass enable */ +#define FSL_CORENET_PAMU_BYPASS 0xffff0000 u32 dmacr1; /* DMA control */ u8 res25[4]; u32 gensr1; /* General status */ |