diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2018-12-04 11:10:21 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-01-09 16:27:39 +0100 |
| commit | 81653478ebcce72de0daac725f5756872133cfbc (patch) | |
| tree | ebe4621b7c6b1f700e695b76ab2b431d0349f9ab /arch | |
| parent | 52c2c97e7c5b3ba326bae53a7940e27878efd405 (diff) | |
ARM: vf610: ddrmc: do not write CR79 by default
The current value CTLUPD_AREF(0) is the reset value of the register,
so there is no need to write a value. If needed, the register can be
written using board specific CR settings.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/ddrmc-vf610.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/ddrmc-vf610.c b/arch/arm/mach-imx/ddrmc-vf610.c index 9739738a08..fa948f7812 100644 --- a/arch/arm/mach-imx/ddrmc-vf610.c +++ b/arch/arm/mach-imx/ddrmc-vf610.c @@ -190,7 +190,6 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]); writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) | DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]); - writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]); writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]); |