diff options
author | Wolfgang Denk <wd@denx.de> | 2012-07-08 19:16:14 +0200 |
---|---|---|
committer | Wolfgang Denk <wd@denx.de> | 2012-07-08 19:16:14 +0200 |
commit | 8246ff864de38935ff34108856a37a2caf6cbefc (patch) | |
tree | fb33f056c2ff6acd4619b7b0098d470c99bd1754 /arch | |
parent | c8a90646adb1c7ca82e856c603ec964b32759d98 (diff) | |
parent | feae34243f63fc319b40db7b92070a0718dc31a6 (diff) |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E
powerpc/mpc85xx: Workaround for erratum CPU_A011
powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
powerpc/P4080: Check SVR for CPU22 workaround
lib/powerpc: addrmap_phys_to_virt() should return a pointer
powerpc/85xx: clean up P1022DS board configuration header file
powerpc/85xx: fdt_set_phy_handle() should return an error code
powerpc/85xx: minor clean-ups to the P2020DS board header file
powerpc/p1010rdb: add readme document for p1010rdb
powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting
powerpc/mpc85xx:Add debugger support for e500v2 SoC
powerpc/85xx:Fix NAND code base to support debugger
powerpc/85xx:Make debug exception vector accessible
powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger
PATCH 1/4][v4] doc:Add documentation for e500 external debugger support
powerpc/p1010rdb: update mux config of p1010rdb board
powerpc/mpc85xx:Add BSC9131 RDB Support
powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
powerpc/85xx: Add USB device-tree fixup for various platforms
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/Makefile | 1 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/cmd_errata.c | 13 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 31 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 32 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 26 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/fdt.c | 11 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/p2041_serdes.c | 4 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/release.S | 39 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 90 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc8xxx/cpu.c | 43 | ||||
-rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 31 | ||||
-rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 119 | ||||
-rw-r--r-- | arch/powerpc/include/asm/io.h | 2 | ||||
-rw-r--r-- | arch/powerpc/include/asm/processor.h | 46 |
14 files changed, 336 insertions, 152 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index c512b337f1..7d65aa7363 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -70,6 +70,7 @@ COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o COBJS-$(CONFIG_PPC_P3060) += ddr-gen3.o COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o +COBJS-$(CONFIG_BSC9131) += ddr-gen3.o COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 2ed5a98424..4e1a54ad0c 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -33,9 +33,7 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (IS_SVR_REV(svr, 1, 0)) { switch (SVR_SOC_VER(svr)) { case SVR_P1013: - case SVR_P1013_E: case SVR_P1022: - case SVR_P1022_E: puts("Work-around for Erratum SATA A001 enabled\n"); } } @@ -51,7 +49,16 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) puts("Work-around for Erratum SERDES-A005 enabled\n"); #endif #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) - puts("Work-around for Erratum CPU22 enabled\n"); + if (SVR_MAJ(svr) < 3) + puts("Work-around for Erratum CPU22 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 + /* + * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + */ + if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) + puts("Work-around for Erratum CPU-A011 enabled\n"); #endif #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999) puts("Work-around for Erratum CPU-A003999 enabled\n"); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2cd5db7c59..fc6c2877d2 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -308,10 +308,18 @@ int cpu_init_r(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; #endif -#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) - flush_dcache(); - mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); - sync(); +#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ + defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) + /* + * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + */ + if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) { + flush_dcache(); + mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); + sync(); + } #endif puts ("L2: "); @@ -354,8 +362,7 @@ int cpu_init_r(void) break; case 0x1: if (ver == SVR_8540 || ver == SVR_8560 || - ver == SVR_8541 || ver == SVR_8541_E || - ver == SVR_8555 || ver == SVR_8555_E) { + ver == SVR_8541 || ver == SVR_8555) { puts("128 KB "); /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ cache_ctl = 0xc4000000; @@ -366,8 +373,7 @@ int cpu_init_r(void) break; case 0x2: if (ver == SVR_8540 || ver == SVR_8560 || - ver == SVR_8541 || ver == SVR_8541_E || - ver == SVR_8555 || ver == SVR_8555_E) { + ver == SVR_8541 || ver == SVR_8555) { puts("256 KB "); /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ cache_ctl = 0xc8000000; @@ -403,8 +409,7 @@ int cpu_init_r(void) puts("enabled\n"); } #elif defined(CONFIG_BACKSIDE_L2_CACHE) - if ((SVR_SOC_VER(svr) == SVR_P2040) || - (SVR_SOC_VER(svr) == SVR_P2040_E)) { + if (SVR_SOC_VER(svr) == SVR_P2040) { puts("N/A\n"); goto skip_l2; } @@ -506,9 +511,7 @@ skip_l2: */ if (IS_SVR_REV(svr, 1, 0) && ((SVR_SOC_VER(svr) == SVR_P1022) || - (SVR_SOC_VER(svr) == SVR_P1022_E) || - (SVR_SOC_VER(svr) == SVR_P1013) || - (SVR_SOC_VER(svr) == SVR_P1013_E))) { + (SVR_SOC_VER(svr) == SVR_P1013))) { fsl_sata_reg_t *reg; /* first SATA controller */ @@ -537,7 +540,7 @@ void arch_preboot_os(void) * disabled by the time we get called. */ msr = mfmsr(); - msr &= ~(MSR_ME|MSR_CE|MSR_DE); + msr &= ~(MSR_ME|MSR_CE); mtmsr(msr); setup_ivors(); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 091af7c95a..dacfdd15ea 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2011 Freescale Semiconductor, Inc + * Copyright 2009-2012 Freescale Semiconductor, Inc * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -53,6 +53,36 @@ void setup_ifc(void) asm volatile("isync;msync;tlbwe;isync"); +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) +/* + * TLB entry for debuggging in AS1 + * Create temporary TLB entry in AS0 to handle debug exception + * As on debug exception MSR is cleared i.e. Address space is changed + * to 0. A TLB entry (in AS0) is required to handle debug exception generated + * in AS1. + * + * TLB entry is created for IVPR + IVOR15 to map on valid OP code address + * bacause flash's physical address is going to change as + * CONFIG_SYS_FLASH_BASE_PHYS. + */ + _mas0 = MAS0_TLBSEL(1) | + MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB); + _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT | + MAS1_TSIZE(BOOKE_PAGESZ_4M); + _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G); + _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX); + _mas7 = FSL_BOOKE_MAS7(flash_phys); + + mtspr(MAS0, _mas0); + mtspr(MAS1, _mas1); + mtspr(MAS2, _mas2); + mtspr(MAS3, _mas3); + mtspr(MAS7, _mas7); + + asm volatile("isync;msync;tlbwe;isync"); +#endif + + /* Change flash's physical address */ out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0); out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c index f33db021f1..bf7a6f6be6 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c @@ -26,32 +26,6 @@ void cpu_init_f(void) { -#ifdef CONFIG_FSL_LBC - fsl_lbc_t *lbc = LBC_BASE_ADDR; - - /* - * LCRR - Clock Ratio Register - set up local bus timing - * when needed - */ - out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8); - -#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) - set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); -#else -#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM must be defined -#endif -#endif -#ifdef CONFIG_FSL_IFC -#ifndef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 -#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) - set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); - set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); - set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); -#endif -#endif -#endif - #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 977770e99d..21c3ad49bf 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -139,16 +139,14 @@ static inline u32 l2cache_size(void) break; case 0x1: if (ver == SVR_8540 || ver == SVR_8560 || - ver == SVR_8541 || ver == SVR_8541_E || - ver == SVR_8555 || ver == SVR_8555_E) + ver == SVR_8541 || ver == SVR_8555) return 128; else return 256; break; case 0x2: if (ver == SVR_8540 || ver == SVR_8560 || - ver == SVR_8541 || ver == SVR_8541_E || - ver == SVR_8555 || ver == SVR_8555_E) + ver == SVR_8541 || ver == SVR_8555) return 256; else return 512; @@ -231,8 +229,7 @@ static inline void ft_fixup_l2cache(void *blob) int has_l2 = 1; /* P2040/P2040E has no L2, so dont set any L2 props */ - if ((SVR_SOC_VER(get_svr()) == SVR_P2040) || - (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) + if (SVR_SOC_VER(get_svr()) == SVR_P2040) has_l2 = 0; size = (l2cfg0 & 0x3fff) * 64 * 1024; @@ -407,7 +404,7 @@ static void ft_fixup_qe_snum(void *blob) unsigned int svr; svr = mfspr(SPRN_SVR); - if (SVR_SOC_VER(svr) == SVR_8569_E) { + if (SVR_SOC_VER(svr) == SVR_8569) { if(IS_SVR_REV(svr, 1, 0)) do_fixup_by_compat_u32(blob, "fsl,qe", "fsl,qe-num-snums", 46, 1); diff --git a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c index f68f28191f..eec4ffe516 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c @@ -78,7 +78,7 @@ enum srds_prtcl serdes_get_prtcl(int cfg, int lane) prtcl = serdes_cfg_tbl[cfg][lane]; /* P2040[e] does not support XAUI */ - if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1)) + if (ver == SVR_P2040 && prtcl == XAUI_FM1) prtcl = NONE; return prtcl; @@ -94,7 +94,7 @@ int is_serdes_prtcl_valid(u32 prtcl) return 0; /* P2040[e] does not support XAUI */ - if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1)) + if (ver == SVR_P2040 && prtcl == XAUI_FM1) return 0; for (i = 0; i < SRDS_MAX_LANES; i++) { diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index c81e19c0e9..1860684c11 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -143,23 +143,40 @@ __secondary_start_page: mtspr L1CSR2,r8 #endif -#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) - mfspr r8,L1CSR2 - oris r8,r8,(L1CSR2_DCWS)@h - mtspr L1CSR2,r8 +#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ + defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) + /* + * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + */ + mfspr r3,SPRN_SVR + rlwinm r6,r3,24,~0x800 /* clear E bit */ + + lis r5,SVR_P4080@h + ori r5,r5,SVR_P4080@l + cmpw r6,r5 + bne 1f + + rlwinm r3,r3,0,0xf0 + li r5,0x30 + cmpw r3,r5 + bge 2f +1: + mfspr r3,L1CSR2 + oris r3,r3,(L1CSR2_DCWS)@h + mtspr L1CSR2,r3 +2: #endif #ifdef CONFIG_BACKSIDE_L2_CACHE /* skip L2 setup on P2040/P2040E as they have no L2 */ - mfspr r2,SPRN_SVR + mfspr r3,SPRN_SVR + rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */ + lis r3,SVR_P2040@h ori r3,r3,SVR_P2040@l - cmpw r2,r3 - beq 3f - - lis r3,SVR_P2040_E@h - ori r3,r3,SVR_P2040_E@l - cmpw r2,r3 + cmpw r6,r3 beq 3f /* Enable/invalidate the L2 cache */ diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 8e99ef6c68..6aabc30c28 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -82,6 +82,9 @@ .globl _start_e500 _start_e500: +/* Enable debug exception */ + li r1,MSR_DE + mtmsr r1 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) /* ISBC uses L2 as stack. @@ -179,6 +182,72 @@ l2_disabled: andi. r1,r3,L1CSR0_DCE@l beq 2b +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL) +/* + * TLB entry for debuggging in AS1 + * Create temporary TLB entry in AS0 to handle debug exception + * As on debug exception MSR is cleared i.e. Address space is changed + * to 0. A TLB entry (in AS0) is required to handle debug exception generated + * in AS1. + */ + + lis r6,FSL_BOOKE_MAS0(1, + CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@h + ori r6,r6,FSL_BOOKE_MAS0(1, + CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@l + +#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) +/* + * TLB entry is created for IVPR + IVOR15 to map on valid OP code address + * bacause flash's virtual address maps to 0xff800000 - 0xffffffff. + * and this window is outside of 4K boot window. + */ + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@l + + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, + (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, + (MAS2_I|MAS2_G))@l + + /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ + lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l +#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l + + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@l + + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@l +#else +/* + * TLB entry is created for IVPR + IVOR15 to map on valid OP code address + * because "nexti" will resize TLB to 4K + */ + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l + + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, + (MAS2_I))@l + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@l +#endif + mtspr MAS0,r6 + mtspr MAS1,r7 + mtspr MAS2,r8 + mtspr MAS3,r9 + tlbwe + isync +#endif + /* * Ne need to setup interrupt vector for NAND SPL * because NAND SPL never compiles it. @@ -733,8 +802,8 @@ create_init_ram_area: msync tlbwe - lis r6,MSR_IS|MSR_DS@h - ori r6,r6,MSR_IS|MSR_DS@l + lis r6,MSR_IS|MSR_DS|MSR_DE@h + ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l lis r7,switch_as@h ori r7,r7,switch_as@l @@ -1372,17 +1441,24 @@ relocate_code: 7: sync /* Wait for all icbi to complete on bus */ isync - /* - * Re-point the IVPR at RAM - */ - mtspr IVPR,r10 - /* * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ addi r0,r10,in_ram - _start + _START_OFFSET + + /* + * As IVPR is going to point RAM address, + * Make sure IVOR15 has valid opcode to support debugger + */ + mtspr IVOR15,r0 + + /* + * Re-point the IVPR at RAM + */ + mtspr IVPR,r10 + mtlr r0 blr /* NEVER RETURNS! */ .globl in_ram diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 0365ca8aa2..cbc674211a 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Copyright 2009-2012 Freescale Semiconductor, Inc. * * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains @@ -37,82 +37,47 @@ DECLARE_GLOBAL_DATA_PTR; struct cpu_type cpu_type_list [] = { #if defined(CONFIG_MPC85xx) CPU_TYPE_ENTRY(8533, 8533, 1), - CPU_TYPE_ENTRY(8533, 8533_E, 1), CPU_TYPE_ENTRY(8535, 8535, 1), - CPU_TYPE_ENTRY(8535, 8535_E, 1), CPU_TYPE_ENTRY(8536, 8536, 1), - CPU_TYPE_ENTRY(8536, 8536_E, 1), CPU_TYPE_ENTRY(8540, 8540, 1), CPU_TYPE_ENTRY(8541, 8541, 1), - CPU_TYPE_ENTRY(8541, 8541_E, 1), CPU_TYPE_ENTRY(8543, 8543, 1), - CPU_TYPE_ENTRY(8543, 8543_E, 1), CPU_TYPE_ENTRY(8544, 8544, 1), - CPU_TYPE_ENTRY(8544, 8544_E, 1), CPU_TYPE_ENTRY(8545, 8545, 1), - CPU_TYPE_ENTRY(8545, 8545_E, 1), - CPU_TYPE_ENTRY(8547, 8547_E, 1), + CPU_TYPE_ENTRY(8547, 8547, 1), CPU_TYPE_ENTRY(8548, 8548, 1), - CPU_TYPE_ENTRY(8548, 8548_E, 1), CPU_TYPE_ENTRY(8555, 8555, 1), - CPU_TYPE_ENTRY(8555, 8555_E, 1), CPU_TYPE_ENTRY(8560, 8560, 1), CPU_TYPE_ENTRY(8567, 8567, 1), - CPU_TYPE_ENTRY(8567, 8567_E, 1), CPU_TYPE_ENTRY(8568, 8568, 1), - CPU_TYPE_ENTRY(8568, 8568_E, 1), CPU_TYPE_ENTRY(8569, 8569, 1), - CPU_TYPE_ENTRY(8569, 8569_E, 1), CPU_TYPE_ENTRY(8572, 8572, 2), - CPU_TYPE_ENTRY(8572, 8572_E, 2), CPU_TYPE_ENTRY(P1010, P1010, 1), - CPU_TYPE_ENTRY(P1010, P1010_E, 1), CPU_TYPE_ENTRY(P1011, P1011, 1), - CPU_TYPE_ENTRY(P1011, P1011_E, 1), CPU_TYPE_ENTRY(P1012, P1012, 1), - CPU_TYPE_ENTRY(P1012, P1012_E, 1), CPU_TYPE_ENTRY(P1013, P1013, 1), - CPU_TYPE_ENTRY(P1013, P1013_E, 1), - CPU_TYPE_ENTRY(P1014, P1014_E, 1), CPU_TYPE_ENTRY(P1014, P1014, 1), - CPU_TYPE_ENTRY(P1015, P1015_E, 1), CPU_TYPE_ENTRY(P1015, P1015, 1), - CPU_TYPE_ENTRY(P1016, P1016_E, 1), CPU_TYPE_ENTRY(P1016, P1016, 1), CPU_TYPE_ENTRY(P1017, P1017, 1), - CPU_TYPE_ENTRY(P1017, P1017_E, 1), CPU_TYPE_ENTRY(P1020, P1020, 2), - CPU_TYPE_ENTRY(P1020, P1020_E, 2), CPU_TYPE_ENTRY(P1021, P1021, 2), - CPU_TYPE_ENTRY(P1021, P1021_E, 2), CPU_TYPE_ENTRY(P1022, P1022, 2), - CPU_TYPE_ENTRY(P1022, P1022_E, 2), CPU_TYPE_ENTRY(P1023, P1023, 2), - CPU_TYPE_ENTRY(P1023, P1023_E, 2), CPU_TYPE_ENTRY(P1024, P1024, 2), - CPU_TYPE_ENTRY(P1024, P1024_E, 2), CPU_TYPE_ENTRY(P1025, P1025, 2), - CPU_TYPE_ENTRY(P1025, P1025_E, 2), CPU_TYPE_ENTRY(P2010, P2010, 1), - CPU_TYPE_ENTRY(P2010, P2010_E, 1), CPU_TYPE_ENTRY(P2020, P2020, 2), - CPU_TYPE_ENTRY(P2020, P2020_E, 2), CPU_TYPE_ENTRY(P2040, P2040, 4), - CPU_TYPE_ENTRY(P2040, P2040_E, 4), CPU_TYPE_ENTRY(P2041, P2041, 4), - CPU_TYPE_ENTRY(P2041, P2041_E, 4), CPU_TYPE_ENTRY(P3041, P3041, 4), - CPU_TYPE_ENTRY(P3041, P3041_E, 4), CPU_TYPE_ENTRY_MASK(P3060, P3060, 6, 0xf3), - CPU_TYPE_ENTRY_MASK(P3060, P3060_E, 6, 0xf3), CPU_TYPE_ENTRY(P4040, P4040, 4), - CPU_TYPE_ENTRY(P4040, P4040_E, 4), CPU_TYPE_ENTRY(P4080, P4080, 8), - CPU_TYPE_ENTRY(P4080, P4080_E, 8), CPU_TYPE_ENTRY(P5010, P5010, 1), - CPU_TYPE_ENTRY(P5010, P5010_E, 1), CPU_TYPE_ENTRY(P5020, P5020, 2), - CPU_TYPE_ENTRY(P5020, P5020_E, 2), + CPU_TYPE_ENTRY(BSC9130, 9130, 1), + CPU_TYPE_ENTRY(BSC9131, 9131, 1), #elif defined(CONFIG_MPC86xx) CPU_TYPE_ENTRY(8610, 8610, 1), CPU_TYPE_ENTRY(8641, 8641, 2), diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 191629b628..b6c44bb11d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -122,6 +122,7 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_FSL_SATA_V2 @@ -138,6 +139,7 @@ #elif defined(CONFIG_P1011) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -149,6 +151,7 @@ #elif defined(CONFIG_P1012) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -163,6 +166,7 @@ #elif defined(CONFIG_P1013) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_FSL_SATA_V2 @@ -175,6 +179,7 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_FSL_SATA_V2 @@ -190,6 +195,7 @@ #elif defined(CONFIG_P1015) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -201,6 +207,7 @@ #elif defined(CONFIG_P1016) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -228,6 +235,7 @@ #elif defined(CONFIG_P1020) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -238,6 +246,7 @@ #elif defined(CONFIG_P1021) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -251,6 +260,7 @@ #elif defined(CONFIG_P1022) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_FSL_SATA_V2 @@ -276,6 +286,7 @@ #elif defined(CONFIG_P1024) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -287,6 +298,7 @@ #elif defined(CONFIG_P1025) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -301,6 +313,7 @@ #elif defined(CONFIG_P2010) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -309,6 +322,7 @@ #elif defined(CONFIG_P2020) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -335,6 +349,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 @@ -359,6 +374,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 @@ -446,6 +462,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 #define CONFIG_SYS_P4080_ERRATUM_CPU22 +#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 @@ -505,6 +522,18 @@ #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#elif defined(CONFIG_BSC9131) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_FSL_SDHC_V2_3 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + #else #error Processor type not defined for this platform #endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 632e3c1669..53d563ed0a 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1,7 +1,7 @@ /* * MPC85xx Internal Memory Map * - * Copyright 2007-2011 Freescale Semiconductor, Inc. + * Copyright 2007-2012 Freescale Semiconductor, Inc. * * Copyright(c) 2002,2003 Motorola Inc. * Xianghua Xiao (x.xiao@motorola.com) @@ -1934,7 +1934,11 @@ typedef struct ccsr_gur { #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 #else +#ifdef CONFIG_BSC9131 +#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 +#else #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 +#endif #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 #endif #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 @@ -2081,6 +2085,50 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_SPI_MASK 0x00600000 #define MPC85xx_PMUXCR_SPI 0x00000000 #endif +#if defined(CONFIG_BSC9131) +#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000 +#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000 +#define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000 +#define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000 +#define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000 +#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000 +#define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000 +#define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000 +#define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000 +#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000 +#define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000 +#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000 +#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000 +#define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000 +#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000 +#define MPC85xx_PMUXCR_SDHC_USIM 0x00010000 +#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000 +#define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000 +#define MPC85xx_PMUXCR_SDHC_RESV 0x00004000 +#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000 +#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000 +#define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000 +#define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000 +#define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000 +#define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400 +#define MPC85xx_PMUXCR_USB_RSVD 0x00000C00 +#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800 +#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100 +#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200 +#define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300 +#define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040 +#define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080 +#define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0 +#define MPC85xx_PMUXCR_SPI1_UART3 0x00000010 +#define MPC85xx_PMUXCR_SPI1_SIM 0x00000020 +#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030 +#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004 +#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008 +#define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C +#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001 +#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002 +#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003 +#endif u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ #if defined(CONFIG_P1010) || defined(CONFIG_P1014) #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 @@ -2111,7 +2159,69 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000 #define MPC85xx_PMUXCR2_USB 0x00150000 #endif +#if defined(CONFIG_BSC9131) +#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000 +#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000 +#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000 +#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000 +#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000 +#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000 +#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000 +#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000 +#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000 +#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000 +#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000 +#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000 +#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000 +#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000 +#define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000 +#define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000 +#define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000 +#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000 +#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000 +#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000 +#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000 +#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000 +#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000 +#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000 +#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000 +#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000 +#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000 +#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000 +#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000 +#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400 +#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800 +#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00 +#define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100 +#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300 +#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040 +#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0 +#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010 +#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020 +#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030 +#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004 +#define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001 +#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002 + u32 pmuxcr3; + +#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000 +#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000 +#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000 +#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000 +#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000 +#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000 +#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000 +#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000 +#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000 +#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000 +#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000 +#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000 +#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000 +#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000 + u32 pmuxcr4; +#else u8 res6[8]; +#endif u32 devdisr; /* Device disable control */ #define MPC85xx_DEVDISR_PCI1 0x80000000 #define MPC85xx_DEVDISR_PCI2 0x40000000 @@ -2166,7 +2276,14 @@ typedef struct ccsr_gur { u32 ddrdllcr; /* DDR DLL control */ u8 res14[12]; u32 lbcdllcr; /* LBC DLL control */ +#if defined(CONFIG_BSC9131) + u8 res15[12]; + u32 halt_req_mask; +#define HALTED_TO_HALT_REQ_MASK_0 0x80000000 + u8 res18[232]; +#else u8 res15[248]; +#endif u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */ u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */ u32 ddrioovcr; /* DDR IO Override Control */ diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index 56ac9fe6c5..6b52a94ffb 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -295,7 +295,7 @@ static inline void * map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { #ifdef CONFIG_ADDR_MAP - return (void *)(addrmap_phys_to_virt(paddr)); + return addrmap_phys_to_virt(paddr); #else return (void *)((unsigned long)paddr); #endif diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 4e32639821..4eb88e9096 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1036,7 +1036,7 @@ #define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ /* Some parts define SVR[0:23] as the SOC version */ -#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ +#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC w/o E bit*/ /* whether MPC8xxxE (i.e. has SEC) */ #if defined(CONFIG_MPC85xx) @@ -1055,87 +1055,55 @@ */ #define SVR_8533 0x803400 -#define SVR_8533_E 0x803C00 #define SVR_8535 0x803701 -#define SVR_8535_E 0x803F01 #define SVR_8536 0x803700 -#define SVR_8536_E 0x803F00 #define SVR_8540 0x803000 #define SVR_8541 0x807200 -#define SVR_8541_E 0x807A00 #define SVR_8543 0x803200 -#define SVR_8543_E 0x803A00 #define SVR_8544 0x803401 -#define SVR_8544_E 0x803C01 #define SVR_8545 0x803102 -#define SVR_8545_E 0x803902 -#define SVR_8547_E 0x803901 +#define SVR_8547 0x803101 #define SVR_8548 0x803100 -#define SVR_8548_E 0x803900 #define SVR_8555 0x807100 -#define SVR_8555_E 0x807900 #define SVR_8560 0x807000 #define SVR_8567 0x807501 -#define SVR_8567_E 0x807D01 #define SVR_8568 0x807500 -#define SVR_8568_E 0x807D00 #define SVR_8569 0x808000 -#define SVR_8569_E 0x808800 #define SVR_8572 0x80E000 -#define SVR_8572_E 0x80E800 #define SVR_P1010 0x80F100 -#define SVR_P1010_E 0x80F900 #define SVR_P1011 0x80E500 -#define SVR_P1011_E 0x80ED00 #define SVR_P1012 0x80E501 -#define SVR_P1012_E 0x80ED01 #define SVR_P1013 0x80E700 -#define SVR_P1013_E 0x80EF00 #define SVR_P1014 0x80F101 -#define SVR_P1014_E 0x80F901 #define SVR_P1015 0x80E502 -#define SVR_P1015_E 0x80ED02 #define SVR_P1016 0x80E503 -#define SVR_P1016_E 0x80ED03 #define SVR_P1017 0x80F700 -#define SVR_P1017_E 0x80FF00 #define SVR_P1020 0x80E400 -#define SVR_P1020_E 0x80EC00 #define SVR_P1021 0x80E401 -#define SVR_P1021_E 0x80EC01 #define SVR_P1022 0x80E600 -#define SVR_P1022_E 0x80EE00 #define SVR_P1023 0x80F600 -#define SVR_P1023_E 0x80FE00 #define SVR_P1024 0x80E402 -#define SVR_P1024_E 0x80EC02 #define SVR_P1025 0x80E403 -#define SVR_P1025_E 0x80EC03 #define SVR_P2010 0x80E300 -#define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200 -#define SVR_P2020_E 0x80EA00 #define SVR_P2040 0x821000 -#define SVR_P2040_E 0x821800 #define SVR_P2041 0x821001 -#define SVR_P2041_E 0x821801 #define SVR_P3041 0x821103 -#define SVR_P3041_E 0x821903 #define SVR_P3060 0x820002 -#define SVR_P3060_E 0x820802 #define SVR_P4040 0x820100 -#define SVR_P4040_E 0x820900 #define SVR_P4080 0x820000 -#define SVR_P4080_E 0x820800 #define SVR_P5010 0x822100 -#define SVR_P5010_E 0x822900 #define SVR_P5020 0x822000 -#define SVR_P5020_E 0x822800 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 #define SVR_8641D 0x809001 +#define SVR_9130 0x860001 +#define SVR_9130_E 0x860801 +#define SVR_9131 0x860000 +#define SVR_9131_E 0x860800 + #define SVR_Unknown 0xFFFFFF #define _GLOBAL(n)\ |