Merge branch 'master' of git://git.denx.de/u-boot-sh

- RZ/A1 addition.
- Old board removal.

13 files changed, 963 insertions, 343 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5be959bf8b..f91c590f6d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -785,7 +785,7 @@ config ARCH_QEMU
 
 config ARCH_RMOBILE
 	bool "Renesas ARM SoCs"
-	select BOARD_EARLY_INIT_F
+	select BOARD_EARLY_INIT_F if !RZA1
 	select DM
 	select DM_SERIAL
 	imply CMD_DM
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8e082f2840..a199f3f988 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -603,6 +603,9 @@ dtb-$(CONFIG_RCAR_GEN3) += \
 	r8a77990-ebisu-u-boot.dtb \
 	r8a77995-draak-u-boot.dtb
 
+dtb-$(CONFIG_RZA1) += \
+	r7s72100-gr-peach-u-boot.dtb
+
 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
 	keystone-k2l-evm.dtb \
 	keystone-k2e-evm.dtb \
diff --git a/arch/arm/dts/r7s72100-gr-peach-u-boot.dts b/arch/arm/dts/r7s72100-gr-peach-u-boot.dts
new file mode 100644
index 0000000000..28247d19d7
--- /dev/null
+++ b/arch/arm/dts/r7s72100-gr-peach-u-boot.dts
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the GR Peach board
+ *
+ * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include "r7s72100-gr-peach.dts"
+
+/ {
+	aliases {
+		spi0 = &rpc;
+	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+
+	leds {
+		led1 {
+			label = "peach:bottom:red";
+		};
+
+		led-red {
+			label = "peach:tri:red";
+			gpios = <&port6 13 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-green {
+			label = "peach:tri:green";
+			gpios = <&port6 14 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-blue {
+			label = "peach:tri:blue";
+			gpios = <&port6 15 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	rpc: rpc@0xee200000 {
+		compatible = "renesas,rpc-r7s72100", "renesas,rpc";
+		reg = <0x3fefa000 0x100>, <0x18000000 0x08000000>;
+		bank-width = <2>;
+		num-cs = <1>;
+		status = "okay";
+		spi-max-frequency = <50000000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		flash0: spi-flash@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "jedec,spi-nor";
+			spi-max-frequency = <50000000>;
+			spi-tx-bus-width = <1>;
+			spi-rx-bus-width = <1>;
+			reg = <0>;
+			status = "okay";
+		};
+	};
+};
+
+&ostm0 {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+	u-boot,dm-pre-reloc;
+};
+
+&scif2 {
+	u-boot,dm-pre-reloc;
+	clock = <66666666>;	/* ToDo: Replace by DM clock driver */
+};
+
+&scif2_pins {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/r7s72100-gr-peach.dts b/arch/arm/dts/r7s72100-gr-peach.dts
new file mode 100644
index 0000000000..fe1a4aa4d7
--- /dev/null
+++ b/arch/arm/dts/r7s72100-gr-peach.dts
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the GR-Peach board
+ *
+ * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
+ * Copyright (C) 2016 Renesas Electronics
+ */
+
+/dts-v1/;
+#include "r7s72100.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
+
+/ {
+	model = "GR-Peach";
+	compatible = "renesas,gr-peach", "renesas,r7s72100";
+
+	aliases {
+		serial0 = &scif2;
+	};
+
+	chosen {
+		bootargs = "ignore_loglevel rw root=/dev/mtdblock0";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@20000000 {
+		device_type = "memory";
+		reg = <0x20000000 0x00a00000>;
+	};
+
+	lbsc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+
+	flash@18000000 {
+		compatible = "mtd-rom";
+		probe-type = "map_rom";
+		reg = <0x18000000 0x00800000>;
+		bank-width = <4>;
+		device-width = <1>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		rootfs@600000 {
+			label = "rootfs";
+			reg = <0x00600000 0x00200000>;
+		};
+	};
+
+	leds {
+		status = "okay";
+		compatible = "gpio-leds";
+
+		led1 {
+			gpios = <&port6 12 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&pinctrl {
+	scif2_pins: serial2 {
+		/* P6_2 as RxD2; P6_3 as TxD2 */
+		pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
+	};
+
+	ether_pins: ether {
+		/* Ethernet on Ports 1,3,5,10 */
+		pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL   */
+			 <RZA1_PINMUX(3, 0, 2)>,  /* P3_0 = ET_TXCLK  */
+			 <RZA1_PINMUX(3, 3, 2)>,  /* P3_3 = ET_MDIO   */
+			 <RZA1_PINMUX(3, 4, 2)>,  /* P3_4 = ET_RXCLK  */
+			 <RZA1_PINMUX(3, 5, 2)>,  /* P3_5 = ET_RXER   */
+			 <RZA1_PINMUX(3, 6, 2)>,  /* P3_6 = ET_RXDV   */
+			 <RZA1_PINMUX(5, 9, 2)>,  /* P5_9 = ET_MDC    */
+			 <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER  */
+			 <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN  */
+			 <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS   */
+			 <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0  */
+			 <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1  */
+			 <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2  */
+			 <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3  */
+			 <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0  */
+			 <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1  */
+			 <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
+			 <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
+	};
+};
+
+&extal_clk {
+	clock-frequency = <13333000>;
+};
+
+&usb_x1_clk {
+	clock-frequency = <48000000>;
+};
+
+&mtu2 {
+	status = "okay";
+};
+
+&ostm0 {
+	status = "okay";
+};
+
+&ostm1 {
+	status = "okay";
+};
+
+&scif2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&scif2_pins>;
+
+	status = "okay";
+};
+
+&ether {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ether_pins>;
+
+	status = "okay";
+
+	renesas,no-ether-link;
+	phy-handle = <&phy0>;
+
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+
+		reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <5>;
+	};
+};
diff --git a/arch/arm/dts/r7s72100.dtsi b/arch/arm/dts/r7s72100.dtsi
new file mode 100644
index 0000000000..2211f88ede
--- /dev/null
+++ b/arch/arm/dts/r7s72100.dtsi
@@ -0,0 +1,705 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r7s72100 SoC
+ *
+ * Copyright (C) 2013-14 Renesas Solutions Corp.
+ * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
+ */
+
+#include <dt-bindings/clock/r7s72100-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "renesas,r7s72100";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		spi0 = &spi0;
+		spi1 = &spi1;
+		spi2 = &spi2;
+		spi3 = &spi3;
+		spi4 = &spi4;
+	};
+
+	/* Fixed factor clocks */
+	b_clk: b {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&cpg_clocks R7S72100_CLK_PLL>;
+		clock-mult = <1>;
+		clock-div = <3>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+			clock-frequency = <400000000>;
+			clocks = <&cpg_clocks R7S72100_CLK_I>;
+			next-level-cache = <&L2>;
+		};
+	};
+
+	/* External clocks */
+	extal_clk: extal {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		/* If clk present, value must be set by board */
+		clock-frequency = <0>;
+	};
+
+	p0_clk: p0 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&cpg_clocks R7S72100_CLK_PLL>;
+		clock-mult = <1>;
+		clock-div = <12>;
+	};
+
+	p1_clk: p1 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&cpg_clocks R7S72100_CLK_PLL>;
+		clock-mult = <1>;
+		clock-div = <6>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a9-pmu";
+		interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	rtc_x1_clk: rtc_x1 {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		/* If clk present, value must be set by board to 32678 */
+		clock-frequency = <0>;
+	};
+
+	rtc_x3_clk: rtc_x3 {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		/* If clk present, value must be set by board to 4000000 */
+		clock-frequency = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		L2: cache-controller@3ffff000 {
+			compatible = "arm,pl310-cache";
+			reg = <0x3ffff000 0x1000>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			arm,early-bresp-disable;
+			arm,full-line-zero-disable;
+			cache-unified;
+			cache-level = <2>;
+		};
+
+		scif0: serial@e8007000 {
+			compatible = "renesas,scif-r7s72100", "renesas,scif";
+			reg = <0xe8007000 64>;
+			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
+			clock-names = "fck";
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		scif1: serial@e8007800 {
+			compatible = "renesas,scif-r7s72100", "renesas,scif";
+			reg = <0xe8007800 64>;
+			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
+			clock-names = "fck";
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		scif2: serial@e8008000 {
+			compatible = "renesas,scif-r7s72100", "renesas,scif";
+			reg = <0xe8008000 64>;
+			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
+			clock-names = "fck";
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		scif3: serial@e8008800 {
+			compatible = "renesas,scif-r7s72100", "renesas,scif";
+			reg = <0xe8008800 64>;
+			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
+			clock-names = "fck";
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		scif4: serial@e8009000 {
+			compatible = "renesas,scif-r7s72100", "renesas,scif";
+			reg = <0xe8009000 64>;
+			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
+			clock-names = "fck";
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		scif5: serial@e8009800 {
+			compatible = "renesas,scif-r7s72100", "renesas,scif";
+			reg = <0xe8009800 64>;
+			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
+			clock-names = "fck";
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		scif6: serial@e800a000 {
+			compatible = "renesas,scif-r7s72100", "renesas,scif";
+			reg = <0xe800a000 64>;
+			interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
+			clock-names = "fck";
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		scif7: serial@e800a800 {
+			compatible = "renesas,scif-r7s72100", "renesas,scif";
+			reg = <0xe800a800 64>;
+			interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
+			clock-names = "fck";
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		spi0: spi@e800c800 {
+			compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+			reg = <0xe800c800 0x24>;
+			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error", "rx", "tx";
+			clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
+			power-domains = <&cpg_clocks>;
+			num-cs = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi1: spi@e800d000 {
+			compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+			reg = <0xe800d000 0x24>;
+			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error", "rx", "tx";
+			clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
+			power-domains = <&cpg_clocks>;
+			num-cs = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi2: spi@e800d800 {
+			compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+			reg = <0xe800d800 0x24>;
+			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error", "rx", "tx";
+			clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
+			power-domains = <&cpg_clocks>;
+			num-cs = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi3: spi@e800e000 {
+			compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+			reg = <0xe800e000 0x24>;
+			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error", "rx", "tx";
+			clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
+			power-domains = <&cpg_clocks>;
+			num-cs = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi4: spi@e800e800 {
+			compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+			reg = <0xe800e800 0x24>;
+			interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error", "rx", "tx";
+			clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
+			power-domains = <&cpg_clocks>;
+			num-cs = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		usbhs0: usb@e8010000 {
+			compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
+			reg = <0xe8010000 0x1a0>;
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp7_clks R7S72100_CLK_USB0>;
+			renesas,buswait = <4>;
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		usbhs1: usb@e8207000 {
+			compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
+			reg = <0xe8207000 0x1a0>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp7_clks R7S72100_CLK_USB1>;
+			renesas,buswait = <4>;
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		mmcif: mmc@e804c800 {
+			compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
+			reg = <0xe804c800 0x80>;
+			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
+			power-domains = <&cpg_clocks>;
+			reg-io-width = <4>;
+			bus-width = <8>;
+			status = "disabled";
+		};
+
+		sdhi0: sd@e804e000 {
+			compatible = "renesas,sdhi-r7s72100";
+			reg = <0xe804e000 0x100>;
+			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
+				 <&mstp12_clks R7S72100_CLK_SDHI01>;
+			clock-names = "core", "cd";
+			power-domains = <&cpg_clocks>;
+			cap-sd-highspeed;
+			cap-sdio-irq;
+			status = "disabled";
+		};
+
+		sdhi1: sd@e804e800 {
+			compatible = "renesas,sdhi-r7s72100";
+			reg = <0xe804e800 0x100>;
+			interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
+				 <&mstp12_clks R7S72100_CLK_SDHI11>;
+			clock-names = "core", "cd";
+			power-domains = <&cpg_clocks>;
+			cap-sd-highspeed;
+			cap-sdio-irq;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@e8201000 {
+			compatible = "arm,pl390";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0xe8201000 0x1000>,
+				<0xe8202000 0x1000>;
+		};
+
+		ether: ethernet@e8203000 {
+			compatible = "renesas,ether-r7s72100";
+			reg = <0xe8203000 0x800>,
+			      <0xe8204800 0x200>;
+			interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
+			power-domains = <&cpg_clocks>;
+			phy-mode = "mii";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		ceu: camera@e8210000 {
+			reg = <0xe8210000 0x3000>;
+			compatible = "renesas,r7s72100-ceu";
+			interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp6_clks R7S72100_CLK_CEU>;
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		wdt: watchdog@fcfe0000 {
+			compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
+			reg = <0xfcfe0000 0x6>;
+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&p0_clk>;
+		};
+
+		/* Special CPG clocks */
+		cpg_clocks: cpg_clocks@fcfe0000 {
+			#clock-cells = <1>;
+			compatible = "renesas,r7s72100-cpg-clocks",
+				     "renesas,rz-cpg-clocks";
+			reg = <0xfcfe0000 0x18>;
+			clocks = <&extal_clk>, <&usb_x1_clk>;
+			clock-output-names = "pll", "i", "g";
+			#power-domain-cells = <0>;
+		};
+
+		/* MSTP clocks */
+		mstp3_clks: mstp3_clks@fcfe0420 {
+			#clock-cells = <1>;
+			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0xfcfe0420 4>;
+			clocks = <&p0_clk>;
+			clock-indices = <R7S72100_CLK_MTU2>;
+			clock-output-names = "mtu2";
+		};
+
+		mstp4_clks: mstp4_clks@fcfe0424 {
+			#clock-cells = <1>;
+			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0xfcfe0424 4>;
+			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
+				 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
+			clock-indices = <
+				R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
+				R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
+			>;
+			clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
+		};
+
+		mstp5_clks: mstp5_clks@fcfe0428 {
+			#clock-cells = <1>;
+			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0xfcfe0428 4>;
+			clocks = <&p0_clk>, <&p0_clk>;
+			clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
+			clock-output-names = "ostm0", "ostm1";
+		};
+
+		mstp6_clks: mstp6_clks@fcfe042c {
+			#clock-cells = <1>;
+			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0xfcfe042c 4>;
+			clocks = <&b_clk>, <&p0_clk>;
+			clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>;
+			clock-output-names = "ceu", "rtc";
+		};
+
+		mstp7_clks: mstp7_clks@fcfe0430 {
+			#clock-cells = <1>;
+			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0xfcfe0430 4>;
+			clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
+			clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
+			clock-output-names = "ether", "usb0", "usb1";
+		};
+
+		mstp8_clks: mstp8_clks@fcfe0434 {
+			#clock-cells = <1>;
+			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0xfcfe0434 4>;
+			clocks = <&p1_clk>;
+			clock-indices = <R7S72100_CLK_MMCIF>;
+			clock-output-names = "mmcif";
+		};
+
+		mstp9_clks: mstp9_clks@fcfe0438 {
+			#clock-cells = <1>;
+			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0xfcfe0438 4>;
+			clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
+			clock-indices = <
+				R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
+			>;
+			clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
+		};
+
+		mstp10_clks: mstp10_clks@fcfe043c {
+			#clock-cells = <1>;
+			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0xfcfe043c 4>;
+			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
+				 <&p1_clk>;
+			clock-indices = <
+				R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
+				R7S72100_CLK_SPI4
+			>;
+			clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
+		};
+		mstp12_clks: mstp12_clks@fcfe0444 {
+			#clock-cells = <1>;
+			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0xfcfe0444 4>;
+			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
+			clock-indices = <
+				R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
+				R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
+			>;
+			clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
+		};
+
+		pinctrl: pin-controller@fcfe3000 {
+			compatible = "renesas,r7s72100-ports";
+
+			reg = <0xfcfe3000 0x4230>;
+
+			port0: gpio-0 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl 0 0 6>;
+			};
+
+			port1: gpio-1 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl 0 16 16>;
+			};
+
+			port2: gpio-2 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl 0 32 16>;
+			};
+
+			port3: gpio-3 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl 0 48 16>;
+			};
+
+			port4: gpio-4 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl 0 64 16>;
+			};
+
+			port5: gpio-5 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl 0 80 11>;
+			};
+
+			port6: gpio-6 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl 0 96 16>;
+			};
+
+			port7: gpio-7 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl 0 112 16>;
+			};
+
+			port8: gpio-8 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl 0 128 16>;
+			};
+
+			port9: gpio-9 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl 0 144 8>;
+			};
+
+			port10: gpio-10 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl 0 160 16>;
+			};
+
+			port11: gpio-11 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl 0 176 16>;
+			};
+		};
+
+		ostm0: timer@fcfec000 {
+			compatible = "renesas,r7s72100-ostm", "renesas,ostm";
+			reg = <0xfcfec000 0x30>;
+			interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		ostm1: timer@fcfec400 {
+			compatible = "renesas,r7s72100-ostm", "renesas,ostm";
+			reg = <0xfcfec400 0x30>;
+			interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@fcfee000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+			reg = <0xfcfee000 0x44>;
+			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
+			clock-frequency = <100000>;
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@fcfee400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+			reg = <0xfcfee400 0x44>;
+			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
+			clock-frequency = <100000>;
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@fcfee800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+			reg = <0xfcfee800 0x44>;
+			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
+			clock-frequency = <100000>;
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@fcfeec00 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+			reg = <0xfcfeec00 0x44>;
+			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
+			clock-frequency = <100000>;
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		mtu2: timer@fcff0000 {
+			compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
+			reg = <0xfcff0000 0x400>;
+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tgi0a";
+			clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
+			clock-names = "fck";
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		rtc: rtc@fcff1000 {
+			compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
+			reg = <0xfcff1000 0x2e>;
+			interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "alarm", "period", "carry";
+			clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
+				 <&rtc_x3_clk>, <&extal_clk>;
+			clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+	};
+
+	usb_x1_clk: usb_x1 {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		/* If clk present, value must be set by board */
+		clock-frequency = <0>;
+	};
+};
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index babb5e9e84..a74f16d348 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -22,9 +22,14 @@ config RCAR_GEN3
 	imply CMD_MMC_SWRITE if MMC
 	imply SUPPORT_EMMC_RPMB if MMC
 
+config RZA1
+	prompt "Renesas ARM SoCs RZ/A1 (32bit)"
+	select CPU_V7A
+
 endchoice
 
 source "arch/arm/mach-rmobile/Kconfig.32"
 source "arch/arm/mach-rmobile/Kconfig.64"
+source "arch/arm/mach-rmobile/Kconfig.rza1"
 
 endif
diff --git a/arch/arm/mach-rmobile/Kconfig.rza1 b/arch/arm/mach-rmobile/Kconfig.rza1
new file mode 100644
index 0000000000..8cf033fb13
--- /dev/null
+++ b/arch/arm/mach-rmobile/Kconfig.rza1
@@ -0,0 +1,28 @@
+if RZA1
+
+# required by the Ethernet driver
+config R7S72100
+	bool
+	default y
+
+# required by serial and usb driver
+config CPU_RZA1
+	bool
+	default y
+
+choice
+	prompt "Renesas RZ/A1 board select"
+
+# Renesas Supported Boards
+config TARGET_GRPEACH
+	bool "GR-PEACH board"
+
+endchoice
+
+config SYS_SOC
+	default "rmobile"
+
+# Renesas Supported Boards
+source "board/renesas/grpeach/Kconfig"
+
+endif
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index aa5be52dfd..b0686ed203 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -26,6 +26,7 @@ void enable_caches(void)
 #endif
 
 #ifdef CONFIG_DISPLAY_CPUINFO
+#ifndef CONFIG_RZA1
 static u32 __rmobile_get_cpu_type(void)
 {
 	return 0x0;
@@ -105,4 +106,11 @@ int print_cpuinfo(void)
 
 	return 0;
 }
+#else
+int print_cpuinfo(void)
+{
+	printf("CPU: Renesas Electronics RZ/A1\n");
+	return 0;
+}
+#endif
 #endif /* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h
index c94b3ff509..aa8d43e59b 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -18,6 +18,7 @@
 #include <asm/arch/r8a7794.h>
 #elif defined(CONFIG_RCAR_GEN3)
 #include <asm/arch/rcar-gen3-base.h>
+#elif defined(CONFIG_R7S72100)
 #else
 #error "SOC Name not defined"
 #endif
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index d20761e66c..a5772da87a 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -75,10 +75,6 @@ config TARGET_AP325RXA
 	bool "Renesas AP-325RXA"
 	select CPU_SH4
 
-config TARGET_ECOVEC
-	bool "EcoVec"
-	select CPU_SH4A
-
 config TARGET_MIGOR
 	bool "Migo-R"
 	select CPU_SH4
@@ -111,10 +107,6 @@ config TARGET_SH7763RDP
 	bool "SH7763RDP"
 	select CPU_SH4
 
-config TARGET_SH7785LCR
-	bool "SH7785LCR"
-	select CPU_SH4A
-
 endchoice
 
 config SYS_ARCH
@@ -135,7 +127,6 @@ source "board/ms7722se/Kconfig"
 source "board/ms7750se/Kconfig"
 source "board/renesas/MigoR/Kconfig"
 source "board/renesas/ap325rxa/Kconfig"
-source "board/renesas/ecovec/Kconfig"
 source "board/renesas/r0p7734/Kconfig"
 source "board/renesas/r2dplus/Kconfig"
 source "board/renesas/r7780mp/Kconfig"
@@ -146,7 +137,6 @@ source "board/renesas/sh7752evb/Kconfig"
 source "board/renesas/sh7753evb/Kconfig"
 source "board/renesas/sh7757lcr/Kconfig"
 source "board/renesas/sh7763rdp/Kconfig"
-source "board/renesas/sh7785lcr/Kconfig"
 source "board/shmin/Kconfig"
 
 endmenu
diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h
index b558d6935c..5fc9c962d8 100644
--- a/arch/sh/include/asm/cpu_sh4.h
+++ b/arch/sh/include/asm/cpu_sh4.h
@@ -30,8 +30,6 @@
 # include <asm/cpu_sh7722.h>
 #elif defined (CONFIG_CPU_SH7723)
 # include <asm/cpu_sh7723.h>
-#elif defined (CONFIG_CPU_SH7724)
-# include <asm/cpu_sh7724.h>
 #elif defined (CONFIG_CPU_SH7734)
 # include <asm/cpu_sh7734.h>
 #elif defined (CONFIG_CPU_SH7752)
@@ -44,8 +42,6 @@
 # include <asm/cpu_sh7763.h>
 #elif defined (CONFIG_CPU_SH7780)
 # include <asm/cpu_sh7780.h>
-#elif defined (CONFIG_CPU_SH7785)
-# include <asm/cpu_sh7785.h>
 #else
 # error "Unknown SH4 variant"
 #endif
diff --git a/arch/sh/include/asm/cpu_sh7724.h b/arch/sh/include/asm/cpu_sh7724.h
deleted file mode 100644
index 7b217959ed..0000000000
--- a/arch/sh/include/asm/cpu_sh7724.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008, 2011 Renesas Solutions Corp.
- *
- * SH7724 Internal I/O register
- */
-
-#ifndef _ASM_CPU_SH7724_H_
-#define _ASM_CPU_SH7724_H_
-
-#define CACHE_OC_NUM_WAYS	4
-#define CCR_CACHE_INIT	0x0000090d
-
-/* EXP */
-#define TRA		0xFF000020
-#define EXPEVT	0xFF000024
-#define INTEVT	0xFF000028
-
-/* MMU */
-#define PTEH	0xFF000000
-#define PTEL	0xFF000004
-#define TTB		0xFF000008
-#define TEA		0xFF00000C
-#define MMUCR	0xFF000010
-#define PASCR	0xFF000070
-#define IRMCR	0xFF000078
-
-/* CACHE */
-#define CCR		0xFF00001C
-#define RAMCR	0xFF000074
-
-/* INTC */
-
-/* BSC */
-#define MMSELR		0xFF800020
-#define CMNCR		0xFEC10000
-#define	CS0BCR		0xFEC10004
-#define CS2BCR		0xFEC10008
-#define CS4BCR		0xFEC10010
-#define CS5ABCR		0xFEC10014
-#define CS5BBCR		0xFEC10018
-#define CS6ABCR		0xFEC1001C
-#define CS6BBCR		0xFEC10020
-#define CS0WCR		0xFEC10024
-#define CS2WCR		0xFEC10028
-#define CS4WCR		0xFEC10030
-#define CS5AWCR		0xFEC10034
-#define CS5BWCR		0xFEC10038
-#define CS6AWCR		0xFEC1003C
-#define CS6BWCR		0xFEC10040
-#define RBWTCNT		0xFEC10054
-
-/* SBSC */
-#define SBSC_SDCR	0xFE400008
-#define SBSC_SDWCR	0xFE40000C
-#define SBSC_SDPCR	0xFE400010
-#define SBSC_RTCSR	0xFE400014
-#define SBSC_RTCNT	0xFE400018
-#define SBSC_RTCOR	0xFE40001C
-#define SBSC_RFCR	0xFE400020
-
-/* DSBC */
-#define DBKIND		0xFD000008
-#define DBSTATE		0xFD00000C
-#define DBEN		0xFD000010
-#define DBCMDCNT	0xFD000014
-#define DBCKECNT	0xFD000018
-#define DBCONF		0xFD000020
-#define DBTR0		0xFD000030
-#define DBTR1		0xFD000034
-#define DBTR2		0xFD000038
-#define DBTR3		0xFD00003C
-#define DBRFPDN0	0xFD000040
-#define DBRFPDN1	0xFD000044
-#define DBRFPDN2	0xFD000048
-#define DBRFSTS		0xFD00004C
-#define DBMRCNT		0xFD000060
-#define DBPDCNT0	0xFD000108
-
-/* DMAC */
-
-/* CPG */
-#define FRQCRA		0xA4150000
-#define FRQCRB		0xA4150004
-#define FRQCR		FRQCRA
-#define VCLKCR      0xA4150004
-#define SCLKACR     0xA4150008
-#define SCLKBCR     0xA415000C
-#define IRDACLKCR   0xA4150018
-#define PLLCR       0xA4150024
-#define DLLFRQ      0xA4150050
-
-/* LOW POWER MODE */
-#define STBCR       0xA4150020
-#define MSTPCR0     0xA4150030
-#define MSTPCR1     0xA4150034
-#define MSTPCR2     0xA4150038
-
-/* RWDT */
-#define RWTCNT      0xA4520000
-#define RWTCSR      0xA4520004
-#define WTCNT		RWTCNT
-
-/* TMU */
-#define TMU_BASE	0xFFD80000
-
-/* TPU */
-
-/* CMT */
-#define CMSTR       0xA44A0000
-#define CMCSR       0xA44A0060
-#define CMCNT       0xA44A0064
-#define CMCOR       0xA44A0068
-
-/* MSIOF */
-
-/* SCIF */
-#define SCIF0_BASE  0xFFE00000
-#define SCIF1_BASE  0xFFE10000
-#define SCIF2_BASE  0xFFE20000
-#define SCIF3_BASE  0xa4e30000
-#define SCIF4_BASE  0xa4e40000
-#define SCIF5_BASE  0xa4e50000
-
-/* RTC */
-/* IrDA */
-/* KEYSC */
-/* USB */
-/* IIC */
-/* FLCTL */
-/* VPU */
-/* VIO(CEU) */
-/* VIO(VEU) */
-/* VIO(BEU) */
-/* 2DG */
-/* LCDC */
-/* VOU */
-/* TSIF */
-/* SIU */
-/* ATAPI */
-
-/* PFC */
-#define PACR        0xA4050100
-#define PBCR        0xA4050102
-#define PCCR        0xA4050104
-#define PDCR        0xA4050106
-#define PECR        0xA4050108
-#define PFCR        0xA405010A
-#define PGCR        0xA405010C
-#define PHCR        0xA405010E
-#define PJCR        0xA4050110
-#define PKCR        0xA4050112
-#define PLCR        0xA4050114
-#define PMCR        0xA4050116
-#define PNCR        0xA4050118
-#define PQCR        0xA405011A
-#define PRCR        0xA405011C
-#define PSCR        0xA405011E
-#define PTCR        0xA4050140
-#define PUCR        0xA4050142
-#define PVCR        0xA4050144
-#define PWCR        0xA4050146
-#define PXCR        0xA4050148
-#define PYCR        0xA405014A
-#define PZCR        0xA405014C
-#define PSELA       0xA405014E
-#define PSELB       0xA4050150
-#define PSELC       0xA4050152
-#define PSELD       0xA4050154
-#define PSELE       0xA4050156
-#define HIZCRA      0xA4050158
-#define HIZCRB      0xA405015A
-#define HIZCRC      0xA405015C
-#define HIZCRD      0xA405015E
-#define MSELCRA     0xA4050180
-#define MSELCRB     0xA4050182
-#define PULCR       0xA4050184
-#define DRVCRA      0xA405018A
-#define DRVCRB      0xA405018C
-
-/* I/O Port */
-#define PADR        0xA4050120
-#define PBDR        0xA4050122
-#define PCDR        0xA4050124
-#define PDDR        0xA4050126
-#define PEDR        0xA4050128
-#define PFDR        0xA405012A
-#define PGDR        0xA405012C
-#define PHDR        0xA405012E
-#define PJDR        0xA4050130
-#define PKDR        0xA4050132
-#define PLDR        0xA4050134
-#define PMDR        0xA4050136
-#define PNDR        0xA4050138
-#define PQDR        0xA405013A
-#define PRDR        0xA405013C
-#define PSDR        0xA405013E
-#define PTDR        0xA4050160
-#define PUDR        0xA4050162
-#define PVDR        0xA4050164
-#define PWDR        0xA4050166
-#define PXDR        0xA4050168
-#define PYDR        0xA405016A
-#define PZDR        0xA405016C
-
-/* UBC */
-/* H-UDI */
-
-#endif /* _ASM_CPU_SH7724_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7785.h b/arch/sh/include/asm/cpu_sh7785.h
deleted file mode 100644
index b0388957f9..0000000000
--- a/arch/sh/include/asm/cpu_sh7785.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-#ifndef	_ASM_CPU_SH7785_H_
-#define	_ASM_CPU_SH7785_H_
-
-/*
- * Copyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
- * Copyright (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#define	CACHE_OC_NUM_WAYS	1
-#define	CCR_CACHE_INIT		0x0000090b
-
-/*	Exceptions	*/
-#define	TRA		0xFF000020
-#define	EXPEVT	0xFF000024
-#define	INTEVT	0xFF000028
-
-/* Cache Controller */
-#define	CCR	0xFF00001C
-#define	QACR0	0xFF000038
-#define	QACR1	0xFF00003C
-#define	RAMCR	0xFF000074
-
-/* Watchdog Timer and Reset */
-#define	WTCNT	WDTCNT
-#define	WDTST	0xFFCC0000
-#define	WDTCSR	0xFFCC0004
-#define	WDTBST	0xFFCC0008
-#define	WDTCNT	0xFFCC0010
-#define	WDTBCNT	0xFFCC0018
-
-/* Timer Unit */
-#define TMU_BASE	0xFFD80000
-
-/* Serial Communication	Interface with FIFO */
-#define	SCIF1_BASE	0xffeb0000
-
-/* LBSC */
-#define MMSELR		0xfc400020
-#define LBSC_BASE	0xff800000
-#define BCR		(LBSC_BASE + 0x1000)
-#define CS0BCR		(LBSC_BASE + 0x2000)
-#define CS1BCR		(LBSC_BASE + 0x2010)
-#define CS2BCR		(LBSC_BASE + 0x2020)
-#define CS3BCR		(LBSC_BASE + 0x2030)
-#define CS4BCR		(LBSC_BASE + 0x2040)
-#define CS5BCR		(LBSC_BASE + 0x2050)
-#define CS6BCR		(LBSC_BASE + 0x2060)
-#define CS0WCR		(LBSC_BASE + 0x2008)
-#define CS1WCR		(LBSC_BASE + 0x2018)
-#define CS2WCR		(LBSC_BASE + 0x2028)
-#define CS3WCR		(LBSC_BASE + 0x2038)
-#define CS4WCR		(LBSC_BASE + 0x2048)
-#define CS5WCR		(LBSC_BASE + 0x2058)
-#define CS6WCR		(LBSC_BASE + 0x2068)
-#define CS5PCR		(LBSC_BASE + 0x2070)
-#define CS6PCR		(LBSC_BASE + 0x2080)
-
-/* PCI	Controller */
-#define	SH7780_PCIECR		0xFE000008
-#define	SH7780_PCIVID		0xFE040000
-#define	SH7780_PCIDID		0xFE040002
-#define	SH7780_PCICMD		0xFE040004
-#define	SH7780_PCISTATUS	0xFE040006
-#define	SH7780_PCIRID		0xFE040008
-#define	SH7780_PCIPIF		0xFE040009
-#define	SH7780_PCISUB		0xFE04000A
-#define	SH7780_PCIBCC		0xFE04000B
-#define	SH7780_PCICLS		0xFE04000C
-#define	SH7780_PCILTM		0xFE04000D
-#define	SH7780_PCIHDR		0xFE04000E
-#define	SH7780_PCIBIST		0xFE04000F
-#define	SH7780_PCIIBAR		0xFE040010
-#define	SH7780_PCIMBAR0		0xFE040014
-#define	SH7780_PCIMBAR1		0xFE040018
-#define	SH7780_PCISVID		0xFE04002C
-#define	SH7780_PCISID		0xFE04002E
-#define	SH7780_PCICP		0xFE040034
-#define	SH7780_PCIINTLINE	0xFE04003C
-#define	SH7780_PCIINTPIN	0xFE04003D
-#define	SH7780_PCIMINGNT	0xFE04003E
-#define	SH7780_PCIMAXLAT	0xFE04003F
-#define	SH7780_PCICID		0xFE040040
-#define	SH7780_PCINIP		0xFE040041
-#define	SH7780_PCIPMC		0xFE040042
-#define	SH7780_PCIPMCSR		0xFE040044
-#define	SH7780_PCIPMCSRBSE	0xFE040046
-#define	SH7780_PCI_CDD		0xFE040047
-#define	SH7780_PCICR		0xFE040100
-#define	SH7780_PCILSR0		0xFE040104
-#define	SH7780_PCILSR1		0xFE040108
-#define	SH7780_PCILAR0		0xFE04010C
-#define	SH7780_PCILAR1		0xFE040110
-#define	SH7780_PCIIR		0xFE040114
-#define	SH7780_PCIIMR		0xFE040118
-#define	SH7780_PCIAIR		0xFE04011C
-#define	SH7780_PCICIR		0xFE040120
-#define	SH7780_PCIAINT		0xFE040130
-#define	SH7780_PCIAINTM		0xFE040134
-#define	SH7780_PCIBMIR		0xFE040138
-#define	SH7780_PCIPAR		0xFE0401C0
-#define	SH7780_PCIPINT		0xFE0401CC
-#define	SH7780_PCIPINTM		0xFE0401D0
-#define	SH7780_PCIMBR0		0xFE0401E0
-#define	SH7780_PCIMBMR0		0xFE0401E4
-#define	SH7780_PCIMBR1		0xFE0401E8
-#define	SH7780_PCIMBMR1		0xFE0401EC
-#define	SH7780_PCIMBR2		0xFE0401F0
-#define	SH7780_PCIMBMR2		0xFE0401F4
-#define	SH7780_PCIIOBR		0xFE0401F8
-#define	SH7780_PCIIOBMR		0xFE0401FC
-#define	SH7780_PCICSCR0		0xFE040210
-#define	SH7780_PCICSCR1		0xFE040214
-#define	SH7780_PCICSAR0		0xFE040218
-#define	SH7780_PCICSAR1		0xFE04021C
-#define	SH7780_PCIPDR		0xFE040220
-
-#endif	/* _ASM_CPU_SH7780_H_ */