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authorTom Rini <trini@konsulko.com>2020-01-16 09:45:40 -0500
committerTom Rini <trini@konsulko.com>2020-01-16 09:45:40 -0500
commit92329e2413f444d1edf29bab66aefccfd782e0a7 (patch)
treef8d5b354b1f228a5258ba01ca801b8e3a5d31792 /arch
parentf47704d4ae494ebc8a25c95202e548ea32f98955 (diff)
parentddb55ff8a66dabe3365735eff9f901bb259c223f (diff)
Merge tag 'xilinx-for-v2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx/FPGA changes for v2020.04 ARM64: - Add INIT_SPL_RELATIVE dependency SPL: - FIT image fix - Enable customization of bl2_plat_get_bl31_params() Pytest: - Add test for octal/hex conversions Microblaze: - Fix manual relocation for one SPI instance Nand: - Convert zynq/zynqmp drivers to DM Xilinx: - Enable boot script location via Kconfig - Support OF_SEPARATE in board FDT selection - Remove low level uart setup it is done later by code - Add support for DEVICE_TREE variable passing for SPL Zynq: - Enable jtag boot mode via distro boot - Removing unused baseaddresses from hardware.h - DT fixups ZynqMP: - Fix emmc boot sequence - Simplify spl logic around bss and board_init_r() - Support psu_post_config_data() calling - Tune mini-nand DTS - Fix psu wiring for a2197 boards - Add runtime MMC device boot order filling in spl - Clear ATF handoff handling with custom bl2_plat_get_bl31_params() - Add support u-boot.its generation - Use single image configuration for all platforms - Enable PANIC_HANG via Kconfig - DT fixups - Firmware fixes - Add support for zcu208 and zcu1285 Versal: - Fix emmc boot sequence - Enable board_late_init() by default
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/dts/Makefile2
-rw-r--r--arch/arm/dts/zynq-7000.dtsi135
-rw-r--r--arch/arm/dts/zynq-zc770-xm011.dts8
-rw-r--r--arch/arm/dts/zynqmp-clk-ccf.dtsi22
-rw-r--r--arch/arm/dts/zynqmp-clk.dtsi4
-rw-r--r--arch/arm/dts/zynqmp-mini-nand.dts49
-rw-r--r--arch/arm/dts/zynqmp-zcu100-revC.dts9
-rw-r--r--arch/arm/dts/zynqmp-zcu102-revA.dts12
-rw-r--r--arch/arm/dts/zynqmp-zcu102-revB.dts2
-rw-r--r--arch/arm/dts/zynqmp-zcu106-revA.dts5
-rw-r--r--arch/arm/dts/zynqmp-zcu111-revA.dts5
-rw-r--r--arch/arm/dts/zynqmp-zcu1275-revB.dts4
-rw-r--r--arch/arm/dts/zynqmp-zcu1285-revA.dts245
-rw-r--r--arch/arm/dts/zynqmp-zcu208-revA.dts588
-rw-r--r--arch/arm/dts/zynqmp-zcu216-revA.dts6
-rw-r--r--arch/arm/dts/zynqmp.dtsi14
-rw-r--r--arch/arm/mach-zynq/include/mach/hardware.h5
-rw-r--r--arch/arm/mach-zynqmp/Kconfig11
-rw-r--r--arch/arm/mach-zynqmp/handoff.c17
-rw-r--r--arch/arm/mach-zynqmp/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h1
-rw-r--r--arch/arm/mach-zynqmp/include/mach/sys_proto.h2
-rwxr-xr-xarch/arm/mach-zynqmp/mkimage_fit_atf.sh123
-rw-r--r--arch/arm/mach-zynqmp/psu_spl_init.c9
-rw-r--r--arch/arm/mach-zynqmp/spl.c27
26 files changed, 1182 insertions, 126 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ee3ca8d182..a623ef5743 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -12,6 +12,7 @@ config ARM64
if ARM64
config POSITION_INDEPENDENT
bool "Generate position-independent pre-relocation code"
+ select INIT_SP_RELATIVE
help
U-Boot expects to be linked to a specific hard-coded address, and to
be loaded to and run from that address. This option lifts that
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index adb843c885..04a8cccda5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -282,6 +282,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-zcu111-revA.dtb \
zynqmp-zcu1275-revA.dtb \
zynqmp-zcu1275-revB.dtb \
+ zynqmp-zcu1285-revA.dtb \
+ zynqmp-zcu208-revA.dtb \
zynqmp-zcu216-revA.dtb \
zynqmp-zc1232-revA.dtb \
zynqmp-zc1254-revA.dtb \
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 07dfa0d107..c35eb2344f 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -62,6 +62,39 @@
regulator-always-on;
};
+ replicator {
+ compatible = "arm,coresight-static-replicator";
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* replicator output ports */
+ port@0 {
+ reg = <0>;
+ replicator_out_port0: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ replicator_out_port1: endpoint {
+ remote-endpoint = <&etb_in_port>;
+ };
+ };
+ };
+ in-ports {
+ /* replicator input port */
+ port {
+ replicator_in_port0: endpoint {
+ remote-endpoint = <&funnel_out_port>;
+ };
+ };
+ };
+ };
+
amba: amba {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
@@ -415,5 +448,107 @@
reg = <0xf8005000 0x1000>;
timeout-sec = <10>;
};
+
+ etb@f8801000 {
+ compatible = "arm,coresight-etb10", "arm,primecell";
+ reg = <0xf8801000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ in-ports {
+ port {
+ etb_in_port: endpoint {
+ remote-endpoint = <&replicator_out_port1>;
+ };
+ };
+ };
+ };
+
+ tpiu@f8803000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0xf8803000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ in-ports {
+ port {
+ tpiu_in_port: endpoint {
+ remote-endpoint = <&replicator_out_port0>;
+ };
+ };
+ };
+ };
+
+ funnel@f8804000 {
+ compatible = "arm,coresight-static-funnel", "arm,primecell";
+ reg = <0xf8804000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+ /* funnel output ports */
+ out-ports {
+ port {
+ funnel_out_port: endpoint {
+ remote-endpoint =
+ <&replicator_in_port0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* funnel input ports */
+ port@0 {
+ reg = <0>;
+ funnel0_in_port0: endpoint {
+ remote-endpoint = <&ptm0_out_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel0_in_port1: endpoint {
+ remote-endpoint = <&ptm1_out_port>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel0_in_port2: endpoint {
+ };
+ };
+ /* The other input ports are not connect to anything */
+ };
+ };
+
+ ptm@f889c000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0xf889c000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ cpu = <&cpu0>;
+ out-ports {
+ port {
+ ptm0_out_port: endpoint {
+ remote-endpoint = <&funnel0_in_port0>;
+ };
+ };
+ };
+ };
+
+ ptm@f889d000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0xf889d000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ cpu = <&cpu1>;
+ out-ports {
+ port {
+ ptm1_out_port: endpoint {
+ remote-endpoint = <&funnel0_in_port1>;
+ };
+ };
+ };
+ };
};
};
diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts
index 1123bfc743..61482017d6 100644
--- a/arch/arm/dts/zynq-zc770-xm011.dts
+++ b/arch/arm/dts/zynq-zc770-xm011.dts
@@ -47,6 +47,14 @@
};
};
+&nand0 {
+ status = "okay";
+};
+
+&smcc {
+ status = "okay";
+};
+
&spi0 {
status = "okay";
num-cs = <4>;
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 998298cc9b..8eacd22d7c 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -2,7 +2,7 @@
/*
* Clock specification for Xilinx ZynqMP
*
- * (C) Copyright 2017, Xilinx, Inc.
+ * (C) Copyright 2017 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@@ -173,26 +173,30 @@
};
&gem0 {
- clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>,
- <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>;
+ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
+ <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
+ <&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gem1 {
- clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>,
- <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>;
+ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
+ <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
+ <&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gem2 {
- clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>,
- <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>;
+ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
+ <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
+ <&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gem3 {
- clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>,
- <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>;
+ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
+ <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
+ <&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi
index 9ef55ad0d1..c9464ec8eb 100644
--- a/arch/arm/dts/zynqmp-clk.dtsi
+++ b/arch/arm/dts/zynqmp-clk.dtsi
@@ -61,13 +61,13 @@
clock-accuracy = <100>;
};
- dpdma_clk: dpdma_clk {
+ dpdma_clk: dpdma-clk {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <533000000>;
};
- drm_clock: drm_clock {
+ drm_clock: drm-clock {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <262750000>;
diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts
index 93aa193f01..d376ade834 100644
--- a/arch/arm/dts/zynqmp-mini-nand.dts
+++ b/arch/arm/dts/zynqmp-mini-nand.dts
@@ -50,55 +50,6 @@
#size-cells = <1>;
arasan,has-mdma;
num-cs = <2>;
-
- partition@0 { /* for testing purpose */
- label = "nand-fsbl-uboot";
- reg = <0x0 0x0 0x400000>;
- };
- partition@1 { /* for testing purpose */
- label = "nand-linux";
- reg = <0x0 0x400000 0x1400000>;
- };
- partition@2 { /* for testing purpose */
- label = "nand-device-tree";
- reg = <0x0 0x1800000 0x400000>;
- };
- partition@3 { /* for testing purpose */
- label = "nand-rootfs";
- reg = <0x0 0x1C00000 0x1400000>;
- };
- partition@4 { /* for testing purpose */
- label = "nand-bitstream";
- reg = <0x0 0x3000000 0x400000>;
- };
- partition@5 { /* for testing purpose */
- label = "nand-misc";
- reg = <0x0 0x3400000 0xFCC00000>;
- };
- partition@6 { /* for testing purpose */
- label = "nand1-fsbl-uboot";
- reg = <0x1 0x0 0x400000>;
- };
- partition@7 { /* for testing purpose */
- label = "nand1-linux";
- reg = <0x1 0x400000 0x1400000>;
- };
- partition@8 { /* for testing purpose */
- label = "nand1-device-tree";
- reg = <0x1 0x1800000 0x400000>;
- };
- partition@9 { /* for testing purpose */
- label = "nand1-rootfs";
- reg = <0x1 0x1C00000 0x1400000>;
- };
- partition@10 { /* for testing purpose */
- label = "nand1-bitstream";
- reg = <0x1 0x3000000 0x400000>;
- };
- partition@11 { /* for testing purpose */
- label = "nand1-misc";
- reg = <0x1 0x3400000 0xFCC00000>;
- };
};
};
};
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index 14aa98de73..21118c8cc3 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -11,7 +11,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
@@ -53,7 +53,7 @@
label = "sw4";
gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
- gpio-key,wakeup;
+ wakeup-source;
autorepeat;
};
};
@@ -95,7 +95,7 @@
linux,default-trigger = "bluetooth-power";
};
- vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
+ vbus-det { /* U5 USB5744 VBUS detection via MIO25 */
label = "vbus_det";
gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -120,9 +120,10 @@
regulator-boot-on;
};
- sdio_pwrseq: sdio_pwrseq {
+ sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+ post-power-on-delay-ms = <10>;
};
ina226 {
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 78110c490e..b580f9263d 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -51,14 +51,14 @@
label = "sw19";
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_DOWN>;
- gpio-key,wakeup;
+ wakeup-source;
autorepeat;
};
};
leds {
compatible = "gpio-leds";
- heartbeat_led {
+ heartbeat-led {
label = "heartbeat";
gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
@@ -213,25 +213,25 @@
gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
"PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
"", "", "", "", "", "", "", "", "";
- gtr_sel0 {
+ gtr-sel0 {
gpio-hog;
gpios = <0 0>;
output-low; /* PCIE = 0, DP = 1 */
line-name = "sel0";
};
- gtr_sel1 {
+ gtr-sel1 {
gpio-hog;
gpios = <1 0>;
output-high; /* PCIE = 0, DP = 1 */
line-name = "sel1";
};
- gtr_sel2 {
+ gtr-sel2 {
gpio-hog;
gpios = <2 0>;
output-high; /* PCIE = 0, USB0 = 1 */
line-name = "sel2";
};
- gtr_sel3 {
+ gtr-sel3 {
gpio-hog;
gpios = <3 0>;
output-high; /* PCIE = 0, SATA = 1 */
diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts
index 2132024a25..38ec188164 100644
--- a/arch/arm/dts/zynqmp-zcu102-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revB.dts
@@ -25,7 +25,7 @@
/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
};
/* Cleanup from RevA */
- /delete-node/ phy@21;
+ /delete-node/ ethernet-phy@21;
};
/* Fix collision with u61 */
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index b4dd101330..d31982fce7 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -51,14 +51,14 @@
label = "sw19";
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_DOWN>;
- gpio-key,wakeup;
+ wakeup-source;
autorepeat;
};
};
leds {
compatible = "gpio-leds";
- heartbeat_led {
+ heartbeat-led {
label = "heartbeat";
gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
@@ -653,7 +653,6 @@
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
- no-1-8-v;
xlnx,mio_bank = <1>;
};
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index aabf73dd6d..bff224f78d 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -51,14 +51,14 @@
label = "sw19";
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_DOWN>;
- gpio-key,wakeup;
+ wakeup-source;
autorepeat;
};
};
leds {
compatible = "gpio-leds";
- heartbeat_led {
+ heartbeat-led {
label = "heartbeat";
gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
@@ -566,7 +566,6 @@
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
- no-1-8-v;
disable-wp;
xlnx,mio_bank = <1>;
};
diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts
index 34c4becd43..2ec29b0b5d 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts
@@ -75,6 +75,10 @@
&sdhci1 {
status = "okay";
+ /*
+ * 1.0 revision has level shifter and this property should be
+ * removed for supporting UHS mode
+ */
no-1-8-v;
xlnx,mio_bank = <1>;
};
diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts
new file mode 100644
index 0000000000..9c18013138
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP ZCU1285 RevA
+ *
+ * (C) Copyright 2018 - 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+ model = "ZynqMP ZCU1285 RevA";
+ compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285",
+ "xlnx,zynqmp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &dcc;
+ spi0 = &qspi;
+ mmc0 = &sdhci1;
+ i2c = &i2c0; /* EMIO */
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ ina226-u60 {
+ compatible = "iio-hwmon";
+ io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
+ };
+ ina226-u61 {
+ compatible = "iio-hwmon";
+ io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
+ };
+ ina226-u63 {
+ compatible = "iio-hwmon";
+ io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
+ };
+ ina226-u65 {
+ compatible = "iio-hwmon";
+ io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
+ };
+ ina226-u64 {
+ compatible = "iio-hwmon";
+ io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ i2c-mux@75 {
+ compatible = "nxp,pca9548"; /* u22 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PMBUS */
+ max20751@74 { /* u23 */
+ compatible = "maxim,max20751";
+ reg = <0x74>;
+ };
+ max20751@70 { /* u89 */
+ compatible = "maxim,max20751";
+ reg = <0x70>;
+ };
+ max15301@a { /* u28 */
+ compatible = "maxim,max15301";
+ reg = <0xa>;
+ };
+ max15303@b { /* u48 */
+ compatible = "maxim,max15303";
+ reg = <0xb>;
+ };
+ max15303@d { /* u27 */
+ compatible = "maxim,max15303";
+ reg = <0xd>;
+ };
+ max15303@e { /* u11 */
+ compatible = "maxim,max15303";
+ reg = <0xe>;
+ };
+ max15303@f { /* u96 */
+ compatible = "maxim,max15303";
+ reg = <0xf>;
+ };
+ max15303@11 { /* u47 */
+ compatible = "maxim,max15303";
+ reg = <0x11>;
+ };
+ max15303@12 { /* u24 */
+ compatible = "maxim,max15303";
+ reg = <0x12>;
+ };
+ max15301@13 { /* u29 */
+ compatible = "maxim,max15301";
+ reg = <0x13>;
+ };
+ max15303@14 { /* u51 */
+ compatible = "maxim,max15303";
+ reg = <0x14>;
+ };
+ max15303@15 { /* u30 */
+ compatible = "maxim,max15303";
+ reg = <0x15>;
+ };
+ max15303@16 { /* u102 */
+ compatible = "maxim,max15303";
+ reg = <0x16>;
+ };
+ max15301@17 { /* u50 */
+ compatible = "maxim,max15301";
+ reg = <0x17>;
+ };
+ max15301@18 { /* u31 */
+ compatible = "maxim,max15301";
+ reg = <0x18>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* CM_I2C */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYS_EEPROM */
+ eeprom: eeprom@54 { /* u101 */
+ compatible = "atmel,24c32"; /* 24LC32A */
+ reg = <0x54>;
+ };
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* FMC1 */
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* FMC2 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* ANALOG_PMBUS */
+ u60: ina226@40 { /* u60 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u60";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+ u61: ina226@41 { /* u61 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u61";
+ reg = <0x41>;
+ shunt-resistor = <1000>;
+ };
+ u63: ina226@42 { /* u63 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u63";
+ reg = <0x42>;
+ shunt-resistor = <1000>;
+ };
+ u65: ina226@43 { /* u65 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u65";
+ reg = <0x43>;
+ shunt-resistor = <1000>;
+ };
+ u64: ina226@44 { /* u64 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u64";
+ reg = <0x44>;
+ shunt-resistor = <1000>;
+ };
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* ANALOG_CM_I2C */
+ };
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* FMC3 */
+ };
+ };
+};
+
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&sdhci1 {
+ status = "okay";
+ xlnx,mio_bank = <1>;
+};
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
new file mode 100644
index 0000000000..9181060b89
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -0,0 +1,588 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU208
+ *
+ * (C) Copyright 2017 - 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP ZCU208 RevA";
+ compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ xlnx,eeprom = &eeprom;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ sw19 {
+ label = "sw19";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_DOWN>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat_led {
+ label = "heartbeat";
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ ina226-vccint {
+ compatible = "iio-hwmon";
+ io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
+ };
+ ina226-vccint-io-bram-ps {
+ compatible = "iio-hwmon";
+ io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
+ };
+ ina226-vcc1v8 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
+ };
+ ina226-vcc1v2 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
+ };
+ ina226-vadj-fmc {
+ compatible = "iio-hwmon";
+ io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
+ };
+ ina226-mgtavcc {
+ compatible = "iio-hwmon";
+ io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
+ };
+ ina226-mgt1v2 {
+ compatible = "iio-hwmon";
+ io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
+ };
+ ina226-mgt1v8 {
+ compatible = "iio-hwmon";
+ io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
+ };
+ ina226-vccint-ams {
+ compatible = "iio-hwmon";
+ io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
+ };
+ ina226-dac-avtt {
+ compatible = "iio-hwmon";
+ io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
+ };
+ ina226-dac-avccaux {
+ compatible = "iio-hwmon";
+ io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
+ };
+ ina226-adc-avcc {
+ compatible = "iio-hwmon";
+ io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
+ };
+ ina226-adc-avccaux {
+ compatible = "iio-hwmon";
+ io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
+ };
+ ina226-dac-avcc {
+ compatible = "iio-hwmon";
+ io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: ethernet-phy@c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ ti,dp83867-rxctrl-strap-quirk;
+ };
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
+ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */
+ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */
+ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */
+ "", "", "BUTTON", "LED", "", /* 20 - 24 */
+ "", "PMU_INPUT", "", "", "", /* 25 - 29 */
+ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */
+ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */
+ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */
+ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */
+ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */
+ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */
+ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */
+ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */
+ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */
+ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
+ "", "", /* 78 - 79 */
+ "", "", "", "", "", /* 80 - 84 */
+ "", "", "", "", "", /* 85 -89 */
+ "", "", "", "", "", /* 90 - 94 */
+ "", "", "", "", "", /* 95 - 99 */
+ "", "", "", "", "", /* 100 - 104 */
+ "", "", "", "", "", /* 105 - 109 */
+ "", "", "", "", "", /* 110 - 114 */
+ "", "", "", "", "", /* 115 - 119 */
+ "", "", "", "", "", /* 120 - 124 */
+ "", "", "", "", "", /* 125 - 129 */
+ "", "", "", "", "", /* 130 - 134 */
+ "", "", "", "", "", /* 135 - 139 */
+ "", "", "", "", "", /* 140 - 144 */
+ "", "", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 174 */
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u15: gpio@20 { /* u15 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */
+ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */
+ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */
+ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@75 { /* u17 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ /* PMBUS_ALERT done via pca9544 */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vccint";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ vccint_io_bram_ps: ina226@41 { /* u57 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vccint-io-bram-ps";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v8: ina226@42 { /* u60 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vcc1v8";
+ reg = <0x42>;
+ shunt-resistor = <2000>;
+ };
+ vcc1v2: ina226@43 { /* u58 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vcc1v2";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vadj_fmc: ina226@45 { /* u62 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vadj-fmc";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ mgtavcc: ina226@46 { /* u67 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-mgtavcc";
+ reg = <0x46>;
+ shunt-resistor = <2000>;
+ };
+ mgt1v2: ina226@47 { /* u63 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-mgt1v2";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ mgt1v8: ina226@48 { /* u64 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-mgt1v8";
+ reg = <0x48>;
+ shunt-resistor = <5000>;
+ };
+ vccint_ams: ina226@49 { /* u61 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-vccint-ams";
+ reg = <0x49>;
+ shunt-resistor = <5000>;
+ };
+ dac_avtt: ina226@4a { /* u59 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-dac-avtt";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ dac_avccaux: ina226@4b { /* u124 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-dac-avccaux";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ adc_avcc: ina226@4c { /* u75 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-adc-avcc";
+ reg = <0x4c>;
+ shunt-resistor = <5000>;
+ };
+ adc_avccaux: ina226@4d { /* u71 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-adc-avccaux";
+ reg = <0x4d>;
+ shunt-resistor = <5000>;
+ };
+ dac_avcc: ina226@4e { /* u77 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-dac-avcc";
+ reg = <0x4e>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* NC */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* u104 - ir35215 0x10/0x40 */
+ /* u127 - ir38164 0x1b/0x4b */
+ /* u112 - ir38164 0x13/0x43 */
+ /* u123 - ir38164 0x1c/0x4c */
+
+ irps5401_44: irps54012@44 { /* IRPS5401 - u53 */
+ #clock-cells = <0>;
+ compatible = "infineon,irps5401";
+ reg = <0x44>; /* i2c addr 0x14 */
+ };
+ irps5401_45: irps54012@45 { /* IRPS5401 - u55 */
+ #clock-cells = <0>;
+ compatible = "infineon,irps5401";
+ reg = <0x45>; /* i2c addr 0x15 */
+ };
+ /* J21 header too */
+
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* SYSMON */
+ };
+ };
+ /* u38 MPS430 */
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ i2c-mux@74 {
+ compatible = "nxp,pca9548"; /* u20 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ i2c_eeprom: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom@54 { /* u21 */
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+ i2c_si5341: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si5341: clock-generator@36 { /* SI5341 - u43 */
+ compatible = "si5341";
+ reg = <0x36>;
+ };
+
+ };
+ i2c_si570_user_c0: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ clock-output-names = "si570_user_c0";
+ };
+ };
+ i2c_si570_mgt: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ clock-output-names = "si570_mgt";
+ };
+ };
+ i2c_8a34001: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* U409B - 8a34001 */
+ };
+ i2c_clk104: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* CLK104_SDA */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* RFMCP connector */
+ };
+ /* 7 NC */
+ };
+
+ i2c-mux@75 {
+ compatible = "nxp,pca9548"; /* u22 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* FMCP_HSPC_IIC */
+ };
+ i2c_si570_user_c1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ clock-output-names = "si570_user_c1";
+ };
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SFP3 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SFP2 */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SFP1 */
+ };
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SFP0 */
+ };
+ };
+ /* MSP430 */
+};
+
+&qspi {
+ status = "okay";
+ is-dual = <1>;
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ disable-wp;
+ xlnx,mio_bank = <1>;
+};
+
+&serdes {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
+};
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index dd9cd7b38f..c294e1b51a 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -253,7 +253,7 @@
#io-channel-cells = <1>;
label = "ina226-vccint-io-bram-ps";
reg = <0x41>;
- shunt-resistor = <2000>;
+ shunt-resistor = <5000>;
};
vcc1v8: ina226@42 { /* u60 */
compatible = "ti,ina226";
@@ -302,7 +302,7 @@
#io-channel-cells = <1>;
label = "ina226-vccint-ams";
reg = <0x49>;
- shunt-resistor = <2000>;
+ shunt-resistor = <5000>;
};
dac_avtt: ina226@4a { /* u59 */
compatible = "ti,ina226";
@@ -401,7 +401,7 @@
* 768B - 1024B address 0x57
*/
eeprom: eeprom@54 { /* u21 */
- compatible = "atmel,24c08";
+ compatible = "atmel,24c128";
reg = <0x54>;
};
};
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index b453941baf..9e7fae83f7 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -25,7 +25,7 @@
#size-cells = <0>;
cpu0: cpu@0 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
operating-points-v2 = <&cpu_opp_table>;
@@ -34,7 +34,7 @@
};
cpu1: cpu@1 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x1>;
@@ -43,7 +43,7 @@
};
cpu2: cpu@2 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x2>;
@@ -52,7 +52,7 @@
};
cpu3: cpu@3 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x3>;
@@ -74,7 +74,7 @@
};
};
- cpu_opp_table: cpu_opp_table {
+ cpu_opp_table: cpu-opp-table {
compatible = "operating-points-v2";
opp-shared;
opp00 {
@@ -252,7 +252,7 @@
};
};
- amba_apu: amba_apu@0 {
+ amba_apu: amba-apu@0 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
@@ -626,12 +626,12 @@
compatible = "xlnx,zynqmp-gpio-1.0";
status = "disabled";
#gpio-cells = <0x2>;
+ gpio-controller;
interrupt-parent = <&gic>;
interrupts = <0 16 4>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0xff0a0000 0x0 0x1000>;
- gpio-controller;
power-domains = <&zynqmp_firmware PD_GPIO>;
};
diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h
index 5412ed6827..89eb565c94 100644
--- a/arch/arm/mach-zynq/include/mach/hardware.h
+++ b/arch/arm/mach-zynq/include/mach/hardware.h
@@ -9,13 +9,8 @@
#define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
#define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
#define ZYNQ_SCU_BASEADDR 0xF8F00000
-#define ZYNQ_QSPI_BASEADDR 0xE000D000
-#define ZYNQ_SMC_BASEADDR 0xE000E000
-#define ZYNQ_NAND_BASEADDR 0xE1000000
#define ZYNQ_DDRC_BASEADDR 0xF8006000
#define ZYNQ_EFUSE_BASEADDR 0xF800D000
-#define ZYNQ_USB_BASEADDR0 0xE0002000
-#define ZYNQ_USB_BASEADDR1 0xE0003000
#define ZYNQ_OCM_BASEADDR 0xFFFC0000
/* Bootmode setting values */
diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index 6cf17eb94e..d82a737a69 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@@ -117,17 +117,6 @@ config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
config ZYNQ_SDHCI_MAX_FREQ
default 200000000
-config SPL_ZYNQMP_TWO_SDHCI
- bool "Enable booting from both SDHCIs"
- depends on SPL
- help
- This option reflects that board has two SDHCI controllers which
- platform can use as boot device. This option ensures that SPL will
- setup BOOT_DEVICE_MMC2 for SDHCI1 controller and BOOT_DEVICE_MMC1 for
- SDHCI0 controller. Platforms which have only one SDHCI controller
- shouldn't enable this option because it for software SDHCI0 or SDHCI1
- are both covered by BOOT_DEVICE_MMC1.
-
config SPL_ZYNQMP_ALT_BOOTMODE
hex
default 0x0 if JTAG_MODE
diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c
index f71ff7b3d2..64e5320acc 100644
--- a/arch/arm/mach-zynqmp/handoff.c
+++ b/arch/arm/mach-zynqmp/handoff.c
@@ -66,7 +66,9 @@ struct xfsbl_atf_handoff_params {
};
#ifdef CONFIG_SPL_OS_BOOT
-void handoff_setup(void)
+struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry,
+ uintptr_t bl33_entry,
+ uintptr_t fdt_addr)
{
struct xfsbl_atf_handoff_params *atfhandoffparams;
@@ -76,11 +78,16 @@ void handoff_setup(void)
atfhandoffparams->magic[2] = 'N';
atfhandoffparams->magic[3] = 'X';
- atfhandoffparams->num_entries = 1;
- atfhandoffparams->partition[0].entry_point = CONFIG_SYS_TEXT_BASE;
- atfhandoffparams->partition[0].flags = FSBL_FLAGS_EL2 <<
- FSBL_FLAGS_EL_SHIFT;
+ atfhandoffparams->num_entries = 0;
+ if (bl33_entry) {
+ atfhandoffparams->partition[0].entry_point = bl33_entry;
+ atfhandoffparams->partition[0].flags = FSBL_FLAGS_EL2 <<
+ FSBL_FLAGS_EL_SHIFT;
+ atfhandoffparams->num_entries++;
+ }
writel(CONFIG_SPL_TEXT_BASE, &pmu_base->gen_storage6);
+
+ return NULL;
}
#endif
diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h
index a0d776166d..fd361c5ce8 100644
--- a/arch/arm/mach-zynqmp/include/mach/hardware.h
+++ b/arch/arm/mach-zynqmp/include/mach/hardware.h
@@ -7,8 +7,6 @@
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
-#define ARASAN_NAND_BASEADDR 0xFF100000
-
#define ZYNQMP_TCM_BASE_ADDR 0xFFE00000
#define ZYNQMP_TCM_SIZE 0x40000
diff --git a/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h b/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h
index 15e54c0493..e37acda2f8 100644
--- a/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h
+++ b/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h
@@ -21,5 +21,6 @@ void prog_reg(unsigned long addr, unsigned long mask,
unsigned long shift, unsigned long value);
int psu_init(void);
+unsigned long psu_post_config_data(void);
#endif /* _PSU_INIT_GPL_H_ */
diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
index 10b70761de..2974ffbc2f 100644
--- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
@@ -46,8 +46,6 @@ struct zynqmp_ipi_msg {
int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
unsigned int zynqmp_get_silicon_version(void);
-void handoff_setup(void);
-
int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
int zynqmp_mmio_read(const u32 address, u32 *value);
diff --git a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
new file mode 100755
index 0000000000..1e770ba111
--- /dev/null
+++ b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
@@ -0,0 +1,123 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0+
+#
+# script to generate FIT image source for Xilinx ZynqMP boards with
+# ARM Trusted Firmware and multiple device trees (given on the command line)
+#
+# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
+
+BL33="u-boot-nodtb.bin"
+[ -z "$BL31" ] && BL31="bl31.bin"
+# Can be also done as ${CROSS_COMPILE}readelf -l bl31.elf | awk '/Entry point/ { print $3 }'
+[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0xfffea000"
+
+if [ -z "$BL33_LOAD_ADDR" ];then
+ BL33_LOAD_ADDR=`awk '/CONFIG_SYS_TEXT_BASE/ { print $3 }' include/generated/autoconf.h`
+fi
+
+DTB_LOAD_ADDR=`awk '/CONFIG_XILINX_OF_BOARD_DTB_ADDR/ { print $3 }' include/generated/autoconf.h`
+if [ ! -z "$DTB_LOAD_ADDR" ]; then
+ DTB_LOAD="load = <$DTB_LOAD_ADDR>;"
+else
+ DTB_LOAD=""
+fi
+
+if [ -z "$*" ]; then
+ DT=arch/arm/dts/${DEVICE_TREE}.dtb
+else
+ DT=$*
+fi
+
+if [ ! -f $BL31 ]; then
+ echo "WARNING: BL31 file $BL31 NOT found, resulting binary is non-functional" >&2
+ BL31=/dev/null
+ # But U-Boot proper could be loaded in EL3 by specifying
+ # firmware = "uboot";
+ # instead of "atf" in config node
+fi
+
+cat << __HEADER_EOF
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+/dts-v1/;
+
+/ {
+ description = "Configuration to load ATF before U-Boot";
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ data = /incbin/("$BL33");
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm64";
+ compression = "none";
+ load = <$BL33_LOAD_ADDR>;
+ entry = <$BL33_LOAD_ADDR>;
+ hash {
+ algo = "md5";
+ };
+ };
+ atf {
+ description = "ARM Trusted Firmware";
+ data = /incbin/("$BL31");
+ type = "firmware";
+ os = "arm-trusted-firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <$ATF_LOAD_ADDR>;
+ entry = <$ATF_LOAD_ADDR>;
+ hash {
+ algo = "md5";
+ };
+ };
+__HEADER_EOF
+
+DEFAULT=1
+cnt=1
+for dtname in $DT
+do
+ cat << __FDT_IMAGE_EOF
+ fdt_$cnt {
+ description = "$(basename $dtname .dtb)";
+ data = /incbin/("$dtname");
+ type = "flat_dt";
+ arch = "arm64";
+ compression = "none";
+ $DTB_LOAD
+ hash {
+ algo = "md5";
+ };
+ };
+__FDT_IMAGE_EOF
+
+[ "x$(basename $dtname .dtb)" = "x${DEVICE_TREE}" ] && DEFAULT=$cnt
+
+cnt=$((cnt+1))
+done
+
+cat << __CONF_HEADER_EOF
+ };
+ configurations {
+ default = "config_$DEFAULT";
+
+__CONF_HEADER_EOF
+
+cnt=1
+for dtname in $DT
+do
+cat << __CONF_SECTION1_EOF
+ config_$cnt {
+ description = "$(basename $dtname .dtb)";
+ firmware = "atf";
+ loadables = "uboot";
+ fdt = "fdt_$cnt";
+ };
+__CONF_SECTION1_EOF
+cnt=$((cnt+1))
+done
+
+cat << __ITS_EOF
+ };
+};
+__ITS_EOF
diff --git a/arch/arm/mach-zynqmp/psu_spl_init.c b/arch/arm/mach-zynqmp/psu_spl_init.c
index b357de3235..b6abdfd608 100644
--- a/arch/arm/mach-zynqmp/psu_spl_init.c
+++ b/arch/arm/mach-zynqmp/psu_spl_init.c
@@ -77,3 +77,12 @@ __weak int psu_init(void)
*/
return -1;
}
+
+__weak unsigned long psu_post_config_data(void)
+{
+ /*
+ * This function is overridden by the one in
+ * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists.
+ */
+ return 0;
+}
diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
index 6ba42bb42f..896657f51c 100644
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@@ -13,6 +13,7 @@
#include <asm/io.h>
#include <asm/spl.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/psu_init_gpl.h>
#include <asm/arch/sys_proto.h>
void board_init_f(ulong dummy)
@@ -27,13 +28,6 @@ void board_init_f(ulong dummy)
#endif
/* Delay is required for clocks to be propagated */
udelay(1000000);
-
- debug("Clearing BSS 0x%p - 0x%p\n", __bss_start, __bss_end);
- /* Clear the BSS */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* No need to call timer init - it is empty for ZynqMP */
- board_init_r(NULL, 0);
}
static void ps_mode_reset(ulong mode)
@@ -60,9 +54,20 @@ void spl_board_init(void)
preloader_console_init();
ps_mode_reset(MODE_RESET);
board_init();
+ psu_post_config_data();
}
#endif
+void board_boot_order(u32 *spl_boot_list)
+{
+ spl_boot_list[0] = spl_boot_device();
+
+ if (spl_boot_list[0] == BOOT_DEVICE_MMC1)
+ spl_boot_list[1] = BOOT_DEVICE_MMC2;
+ if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
+ spl_boot_list[1] = BOOT_DEVICE_MMC1;
+}
+
u32 spl_boot_device(void)
{
u32 reg = 0;
@@ -86,11 +91,7 @@ u32 spl_boot_device(void)
#ifdef CONFIG_SPL_MMC_SUPPORT
case SD_MODE1:
case SD1_LSHFT_MODE: /* not working on silicon v1 */
-/* if both controllers enabled, then these two are the second controller */
-#ifdef CONFIG_SPL_ZYNQMP_TWO_SDHCI
return BOOT_DEVICE_MMC2;
-/* else, fall through, the one SDHCI controller that is enabled is number 1 */
-#endif
case SD_MODE:
case EMMC_MODE:
return BOOT_DEVICE_MMC1;
@@ -119,8 +120,6 @@ u32 spl_boot_device(void)
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
- handoff_setup();
-
return 0;
}
#endif
@@ -131,6 +130,6 @@ int board_fit_config_name_match(const char *name)
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
- return 0;
+ return -1;
}
#endif