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authorSimon Glass <sjg@chromium.org>2016-03-06 19:28:12 -0700
committerBin Meng <bmeng.cn@gmail.com>2016-03-17 10:27:23 +0800
commit963a811ab42aac2fac6fc063dc7cc689a3336d28 (patch)
treeba91b3be7160e8a1ae73ecbea382eb37504e9165 /arch
parenta86d45491ed6202107d31f2a715576f73bde97a9 (diff)
x86: dts: link: Add board ID GPIOs
At present the board ID GPIOs are hard-coded. Move them to the device tree so that we can use general SDRAM init code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/dts/chromebook_link.dts2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 12f315e66a..a702ea9d60 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -74,6 +74,8 @@
northbridge@0,0 {
reg = <0x00000000 0 0 0 0>;
compatible = "intel,bd82x6x-northbridge";
+ board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>,
+ <&gpio_b 11 0>, <&gpio_a 10 0>;
u-boot,dm-pre-reloc;
spd {
compatible = "memory-spd";