diff options
| author | Jagan Teki <jagannadh.teki@gmail.com> | 2018-06-28 19:40:46 +0530 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-06-29 10:52:18 +0200 |
| commit | 9c22aec4102de0f0dc35e21772d9f21d4616c3d2 (patch) | |
| tree | beaf46b1b6e74413aadd69d9e8071ec76e3773f8 /arch | |
| parent | 9763df8b8a1f7fe7b79030d19d3c326b17800f9e (diff) | |
usb: sunxi: Use proper reg_mask for clock gate, reset
Masking clock gate, reset register bits based on the
probed controller is proper only due to the assumption
that masking should start with 0 even thought the controller
has separate PHY or shared between OTG.
unfortunately these are fixed due to lack of separate
clock, reset drivers.
Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG)
so we need to start reg_mask 0 - 2.
This patch calculated the mask, based on the register base
so that we can get the proper bits to set with respect to
probed controller.
We even do this masking by using PHY index specifier from dt,
but dev_read_addr_size is failing for 64-bit boards.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index ee648366c7..02ce73954d 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -63,10 +63,11 @@ #ifdef CONFIG_SUNXI_GEN_SUN6I #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) #define SUNXI_USBPHY_BASE 0x01c19000 -#define SUNXI_USB0_BASE 0x01c1a000 -#define SUNXI_USB1_BASE 0x01c1b000 -#define SUNXI_USB2_BASE 0x01c1c000 -#define SUNXI_USB3_BASE 0x01c1d000 +#define SUNXI_USB0_BASE SUNXI_USBPHY_BASE +#define SUNXI_USB1_BASE 0x01c1a000 +#define SUNXI_USB2_BASE 0x01c1b000 +#define SUNXI_USB3_BASE 0x01c1c000 +#define SUNXI_USB4_BASE 0x01c1d000 #else #define SUNXI_USB0_BASE 0x01c19000 #define SUNXI_USB1_BASE 0x01c1a000 |