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authorBin Meng <bmeng.cn@gmail.com>2015-07-22 01:21:13 -0700
committerSimon Glass <sjg@chromium.org>2015-07-28 10:36:25 -0600
commita8ebf283e98d0eda0b7c76647cdcd3f36f34837c (patch)
treecc37e6e8fe9f5956dbce2df26ee169a3d37a46fc /arch
parentc77b8912d86a08b57bab21982a865fbf2151f0af (diff)
x86: qemu: Enable writing MP table
Enable writing MP table for QEMU boads (i440fx and q35). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/cpu/qemu/pci.c34
-rw-r--r--arch/x86/dts/qemu-x86_i440fx.dts12
-rw-r--r--arch/x86/dts/qemu-x86_q35.dts12
3 files changed, 55 insertions, 3 deletions
diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c
index ab93e76054..acbd922747 100644
--- a/arch/x86/cpu/qemu/pci.c
+++ b/arch/x86/cpu/qemu/pci.c
@@ -13,6 +13,8 @@
DECLARE_GLOBAL_DATA_PTR;
+static bool i440fx;
+
void board_pci_setup_hose(struct pci_controller *hose)
{
hose->first_busno = 0;
@@ -61,7 +63,8 @@ int board_pci_post_scan(struct pci_controller *hose)
* PCI device ID.
*/
device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
- pam = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_PAM : Q35_PAM;
+ i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
+ pam = i440fx ? I440FX_PAM : Q35_PAM;
/*
* Initialize Programmable Attribute Map (PAM) Registers
@@ -71,7 +74,7 @@ int board_pci_post_scan(struct pci_controller *hose)
for (i = 0; i < PAM_NUM; i++)
x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
- if (device == PCI_DEVICE_ID_INTEL_82441) {
+ if (i440fx) {
/*
* Enable legacy IDE I/O ports decode
*
@@ -97,10 +100,35 @@ int board_pci_post_scan(struct pci_controller *hose)
* board, it shows as device 2, while for Q35 and ICH9 chipset board,
* it shows as device 1.
*/
- vga = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_VGA : Q35_VGA;
+ vga = i440fx ? I440FX_VGA : Q35_VGA;
start = get_timer(0);
ret = pci_run_vga_bios(vga, NULL, PCI_ROM_USE_NATIVE);
debug("BIOS ran in %lums\n", get_timer(start));
return ret;
}
+
+#ifdef CONFIG_GENERATE_MP_TABLE
+int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
+{
+ u8 irq;
+
+ if (i440fx) {
+ /*
+ * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
+ * connected to I/O APIC INTPIN#16-19. Instead they are routed
+ * to an irq number controled by the PIRQ routing register.
+ */
+ irq = x86_pci_read_config8(PCI_BDF(bus, dev, func),
+ PCI_INTERRUPT_LINE);
+ } else {
+ /*
+ * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7.
+ * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11].
+ */
+ irq = pirq < 8 ? pirq + 16 : pirq + 12;
+ }
+
+ return irq;
+}
+#endif
diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts
index 0c522c860f..c26c71bcf7 100644
--- a/arch/x86/dts/qemu-x86_i440fx.dts
+++ b/arch/x86/dts/qemu-x86_i440fx.dts
@@ -24,6 +24,18 @@
stdout-path = "/serial";
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "cpu-x86";
+ reg = <0>;
+ intel,apic-id = <0>;
+ };
+ };
+
pci {
compatible = "pci-x86";
#address-cells = <3>;
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 5fbabc2f3c..2e785fa4bf 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -35,6 +35,18 @@
stdout-path = "/serial";
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "cpu-x86";
+ reg = <0>;
+ intel,apic-id = <0>;
+ };
+ };
+
pci {
compatible = "pci-x86";
#address-cells = <3>;