Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv

- Fix SiFive HiFive Unleashed board booting failure problem.
- Enable SiFive fu540 PWM driver.
- Support SiFive fu540: SPI boot.
- Update OpenSBI used for RISC-V CI testing.
- Revert "riscv: Allow use of reset drivers".
- Revert "Revert "riscv: sifive: fu540: Add gpio-restart support"".
- sysreset: syscon:
        - Don't assume default value for offset and mask property.
        - Support value property.
- qemu: Add syscon reboot and poweroff support.
- Fix SIFIVE debug serial dependency.
- Fix linking error when building u-boot-spl with no SMP support.
- AE350 use fdtdec_get_addr_size_auto_noparent to parse smc reg.
- Make memory node available to SPL in hifive-unleashed-a00-u-boot.dtsi
- SiFive fu540 avoid using hardcoded ram base and size.

6 files changed, 44 insertions, 7 deletions

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index bbd6c15352..bfa2d4a426 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -107,7 +107,7 @@ int arch_cpu_init_dm(void)
 #endif
 	}
 
-#ifdef CONFIG_SMP
+#if CONFIG_IS_ENABLED(SMP)
 	ret = riscv_init_ipi();
 	if (ret)
 		return ret;
diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
index e9302e87c0..2dcad8e27f 100644
--- a/arch/riscv/cpu/fu540/Kconfig
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -13,3 +13,16 @@ config SIFIVE_FU540
 	imply SPL_CPU_SUPPORT
 	imply SPL_OPENSBI
 	imply SPL_LOAD_FIT
+
+if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET
+	default 0x505000
+
+config ENV_SIZE
+	default 0x20000
+
+config ENV_SECT_SIZE
+	default 0x10000
+
+endif # ENV_IS_IN_SPI_FLASH
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index f408e41ab9..bf9fdf369b 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -193,6 +193,7 @@ spl_stack_gd_setup:
 	mv	sp, s0
 #endif
 
+#if CONFIG_IS_ENABLED(SMP)
 	/* set new stack and global data pointer on secondary harts */
 spl_secondary_hart_stack_gd_setup:
 	la	a0, secondary_hart_relocate
@@ -207,6 +208,7 @@ spl_secondary_hart_stack_gd_setup:
 	la	a0, secondary_harts_relocation_error
 	jal	printf
 	jal	hang
+#endif
 
 	/* set new global data pointer on main hart */
 1:	mv	gp, s0
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index e037150520..5d0c928b29 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -16,6 +16,14 @@
 		spi2 = &qspi2;
 	};
 
+	config {
+		u-boot,spl-payload-offset = <0x105000>; /* loader2 @1044KB */
+	};
+
+	memory@80000000 {
+		u-boot,dm-spl;
+	};
+
 	hfclk {
 		u-boot,dm-spl;
 	};
@@ -26,6 +34,14 @@
 
 };
 
+&qspi0 {
+	u-boot,dm-spl;
+
+	flash@0 {
+		u-boot,dm-spl;
+	};
+};
+
 &qspi2 {
 	mmc@0 {
 		u-boot,dm-spl;
diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c
index 6008bbe78e..8779c619cc 100644
--- a/arch/riscv/lib/reset.c
+++ b/arch/riscv/lib/reset.c
@@ -7,7 +7,6 @@
 #include <command.h>
 #include <hang.h>
 
-#ifndef CONFIG_SYSRESET
 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
 	printf("resetting ...\n");
@@ -17,4 +16,3 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 
 	return 0;
 }
-#endif
diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
index 78fc6c868d..b9a2c649cc 100644
--- a/arch/riscv/lib/sifive_clint.c
+++ b/arch/riscv/lib/sifive_clint.c
@@ -26,6 +26,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int riscv_get_time(u64 *time)
 {
+	/* ensure timer register base has a sane value */
+	riscv_init_ipi();
+
 	*time = readq((void __iomem *)MTIME_REG(gd->arch.clint));
 
 	return 0;
@@ -33,6 +36,9 @@ int riscv_get_time(u64 *time)
 
 int riscv_set_timecmp(int hart, u64 cmp)
 {
+	/* ensure timer register base has a sane value */
+	riscv_init_ipi();
+
 	writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart));
 
 	return 0;
@@ -40,11 +46,13 @@ int riscv_set_timecmp(int hart, u64 cmp)
 
 int riscv_init_ipi(void)
 {
-	long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT);
+	if (!gd->arch.clint) {
+		long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT);
 
-	if (IS_ERR(ret))
-		return PTR_ERR(ret);
-	gd->arch.clint = ret;
+		if (IS_ERR(ret))
+			return PTR_ERR(ret);
+		gd->arch.clint = ret;
+	}
 
 	return 0;
 }