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authorTom Rini <trini@konsulko.com>2016-06-12 12:52:19 -0400
committerTom Rini <trini@konsulko.com>2016-06-12 12:52:19 -0400
commitb10335009667fee493fbce59bbeb0504d0ca9ff0 (patch)
tree74aa9bc8d6d1f1929e24e4139d1242a30f02fabf /arch
parent3fc304b8d77ce6646d38ae506e9fae74b9975631 (diff)
parente19b9004575cacf1f64fff894621adafe0e7ea7f (diff)
Merge branch 'master' of git://git.denx.de/u-boot-mips
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/Kconfig2
-rw-r--r--arch/mips/lib/cache.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 5c30ae981d..21066f0fda 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -253,7 +253,7 @@ config SYS_DCACHE_SIZE
The total size of the L1 Dcache, if known at compile time.
config SYS_DCACHE_LINE_SIZE
- hex
+ int
default 0
help
The size of L1 Dcache lines, if known at compile time.
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 5f520c069f..db81953f86 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -91,5 +91,5 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
if (start_addr == stop)
return;
- cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_I);
+ cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
}