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authorOliver Chen <Oliver.Chen@nxp.com>2020-04-21 14:48:09 +0800
committerPeng Fan <peng.fan@nxp.com>2020-07-14 15:23:46 +0800
commitb335966958a93e49439bf248adadce89e7e2bee3 (patch)
treed4ee266783df9801705bb751710514be758da202 /arch
parent3f63d27c177a84dd97f77fb843ff4e4c6d7d45eb (diff)
drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue
Add logic to automatically update umctl2's setting based on phy training CDD value for rank to rank space issue Acked-by: Ye Li <ye.li@nxp.com> Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/arch-imx8m/ddr.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h
index 04c9c962cf..0f1e832c03 100644
--- a/arch/arm/include/asm/arch-imx8m/ddr.h
+++ b/arch/arm/include/asm/arch-imx8m/ddr.h
@@ -721,6 +721,9 @@ int wait_ddrphy_training_complete(void);
void ddrphy_init_set_dfi_clk(unsigned int drate);
void ddrphy_init_read_msg_block(enum fw_type type);
+void update_umctl2_rank_space_setting(unsigned int pstat_num);
+void get_trained_CDD(unsigned int fsp);
+
static inline void reg32_write(unsigned long addr, u32 val)
{
writel(val, addr);