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authorTroy Kisky <troy.kisky@boundarydevices.com>2012-05-18 13:21:59 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-07-07 14:07:22 +0200
commitd5b069ecb4199f1672fd98041bd0037bd33d2f0f (patch)
treee69184730c00381d3d7c0d65c5a692eca3686ec8 /arch
parente843d0f7ee1b67500d5cbbb20320df17ecbdf32c (diff)
DaVinci: fix ddr2 vtp i/o calibration
Previously, only the low 5 bits (NCH) were being transfered from DDRVTPR to DDRVTPIOCR, the bits 5-9 where zeroed. VTP_RECAL should be bit 15, not 18. The only mainline board affected by this change is davinci_sonata. The other Davinci boards define CONFIG_SKIP_LOWLEVEL_INIT. However, if the program that loads u-boot on these boards copied the code from u-boot, they will need fixed as well. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Please get tested by acks before applying, where tested by means an overnight memory test. Thanks Troy
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S7
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S
index 5b39484501..0e45426fbc 100644
--- a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S
+++ b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S
@@ -523,9 +523,8 @@ VTPLock:
ldr r6, DDRVTPR
ldr r7, [r6]
- and r7, r7, $0x1f
- and r8, r7, $0x3e0
- orr r8, r7, r8
+ mov r8, r7, LSL #32-10
+ mov r8, r8, LSR #32-10 /* grab low 10 bits */
ldr r7, VTP_RECAL
orr r8, r7, r8
ldr r7, VTP_EN
@@ -644,7 +643,7 @@ VTP_LOCK_COUNT:
VTP_MASK:
.word 0xffffdfff
VTP_RECAL:
- .word 0x40000
+ .word 0x08000
VTP_EN:
.word 0x02000
CFGTEST: