diff options
author | Simon Glass <sjg@chromium.org> | 2016-01-21 19:45:17 -0700 |
---|---|---|
committer | Simon Glass <sjg@chromium.org> | 2016-01-21 20:42:37 -0700 |
commit | dae594f2105b08ce76aa6b3b02433abb0796be51 (patch) | |
tree | b4245d9043e7cadd9df635c7807ed6dcb3df3240 /arch | |
parent | 318922b30fd0f255a72d7ccd7d7fd58dfb5feb2e (diff) |
rockchip: spl: Support full-speed CPU in SPL
Add a feature which speeds up the CPU to full speed in SPL to minimise
boot time. This is only supported for certain boards (at present only
jerry).
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/dts/rk3288-veyron.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-rockchip/clock.h | 5 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 12 | ||||
-rw-r--r-- | arch/arm/mach-rockchip/rk3288/Kconfig | 9 | ||||
-rw-r--r-- | arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 36 |
5 files changed, 64 insertions, 0 deletions
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi index c201e855de..421d21290c 100644 --- a/arch/arm/dts/rk3288-veyron.dtsi +++ b/arch/arm/dts/rk3288-veyron.dtsi @@ -332,6 +332,7 @@ clock-frequency = <400000>; i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ i2c-scl-rising-time-ns = <100>; /* 45ns measured */ + u-boot,dm-pre-reloc; rk808: pmic@1b { compatible = "rockchip,rk808"; @@ -344,6 +345,7 @@ rockchip,system-power-controller; wakeup-source; #clock-cells = <1>; + u-boot,dm-pre-reloc; vcc1-supply = <&vcc33_sys>; vcc2-supply = <&vcc33_sys>; diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index a9ea2689c7..d66b26f18e 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -74,4 +74,9 @@ void *rockchip_get_cru(void); */ int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp); +struct rk3288_cru; +struct rk3288_grf; + +void rkclk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); + #endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index b0dea7060a..d2690c7788 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -109,6 +109,18 @@ enum { SPI0_DIV_MASK = 0x7f, }; +/* CRU_CLKSEL37_CON */ +enum { + PCLK_CORE_DBG_DIV_SHIFT = 9, + PCLK_CORE_DBG_DIV_MASK = 0x1f, + + ATCLK_CORE_DIV_CON_SHIFT = 4, + ATCLK_CORE_DIV_CON_MASK = 0x1f, + + CLK_L2RAM_DIV_SHIFT = 0, + CLK_L2RAM_DIV_MASK = 7, +}; + /* CRU_CLKSEL39_CON */ enum { ACLK_HEVC_PLL_SHIFT = 0xe, diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index d0a72767c8..ed89c3e077 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -16,6 +16,15 @@ config TARGET_CHROMEBOOK_JERRY WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to the keyboard and battery functions. +config ROCKCHIP_FAST_SPL + bool "Change the CPU to full speed in SPL" + depends on TARGET_CHROMEBOOK_JERRY + help + Some boards want to boot as fast as possible. We can increase the + CPU frequency in SPL if the power supply is configured to the correct + voltage. This option is only available on boards which support it + and have the required PMIC code. + config SYS_SOC default "rockchip" diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c index 074cf51870..e9e2211c82 100644 --- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c @@ -22,6 +22,8 @@ #include <asm/arch/pmu_rk3288.h> #include <asm/arch/sdram.h> #include <linux/err.h> +#include <power/regulator.h> +#include <power/rk808_pmic.h> DECLARE_GLOBAL_DATA_PTR; @@ -748,6 +750,32 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu) } #ifdef CONFIG_SPL_BUILD +# ifdef CONFIG_ROCKCHIP_FAST_SPL +static int veyron_init(struct dram_info *priv) +{ + struct udevice *pmic; + int ret; + + ret = uclass_first_device(UCLASS_PMIC, &pmic); + if (ret) + return ret; + + /* Slowly raise to max CPU voltage to prevent overshoot */ + ret = rk808_spl_configure_buck(pmic, 1, 1200000); + if (ret) + return ret; + udelay(175);/* Must wait for voltage to stabilize, 2mV/us */ + ret = rk808_spl_configure_buck(pmic, 1, 1400000); + if (ret) + return ret; + udelay(100);/* Must wait for voltage to stabilize, 2mV/us */ + + rkclk_configure_cpu(priv->cru, priv->grf); + + return 0; +} +# endif + static int setup_sdram(struct udevice *dev) { struct dram_info *priv = dev_get_priv(dev); @@ -791,6 +819,14 @@ static int setup_sdram(struct udevice *dev) return -EINVAL; } +# ifdef CONFIG_ROCKCHIP_FAST_SPL + if (!fdt_node_check_compatible(blob, 0, "google,veyron")) { + ret = veyron_init(priv); + if (ret) + return ret; + } +# endif + return sdram_init(priv, ¶ms); } #endif |