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authorSanchayan Maity <maitysanchayan@gmail.com>2015-04-15 16:24:26 +0530
committerTom Rini <trini@konsulko.com>2015-04-23 14:56:09 -0400
commite7b860fa4dd4de736d887deca19ca540abea4239 (patch)
treee87e02cde7cef75a7b4091c2995decb61d0fc96d /arch
parent7a90a1f260908eb13b3948da0315a729795db1ab (diff)
ARM: vf610: Initial integration for Colibri VF50/VF61
This adds initial support for Colibri VF50/VF61 based on Freescale Vybrid SoC. - CPU clocked at 396/500 MHz - DDR3 at 396MHz - for VF50, use PLL2 as memory clock (synchronous mode) - for VF61, use PLL1 as memory clock (asynchronous mode) - Console on UART0 (Colibri UART_A) - Ethernet on FEC1 - PLL5 based RMII clocking (E.g. No external crystal) - UART_A and UART_C I/O muxing - Boot from NAND by default Tested on Colibri VF50/VF61 booting using serial loader over UART. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Acked-by: Stefan Agner <stefan@agner.ch>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig5
-rw-r--r--arch/arm/include/asm/arch-vf610/imx-regs.h5
2 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7abcff12e0..b39bb4f532 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -640,6 +640,10 @@ config TARGET_VF610TWR
bool "Support vf610twr"
select CPU_V7
+config TARGET_COLIBRI_VF
+ bool "Support Colibri VF50/61"
+ select CPU_V7
+
config ZYNQ
bool "Xilinx Zynq Platform"
select CPU_V7
@@ -914,6 +918,7 @@ source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
+source "board/toradex/colibri_vf/Kconfig"
source "board/tqc/tqma6/Kconfig"
source "board/trizepsiv/Kconfig"
source "board/ttcontrol/vision2/Kconfig"
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index a5908ca102..bf41971148 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -263,6 +263,11 @@
#define SRC_SRSR_WDOG_M4 (0x1 << 4)
#define SRC_SRSR_WDOG_A5 (0x1 << 3)
#define SRC_SRSR_POR_RST (0x1 << 0)
+#define SRC_SBMR2_BMOD_MASK (0x3 << 24)
+#define SRC_SBMR2_BMOD_SHIFT 24
+#define SRC_SBMR2_BMOD_FUSES 0x0
+#define SRC_SBMR2_BMOD_SERIAL 0x1
+#define SRC_SBMR2_BMOD_RCON 0x2
/* Slow Clock Source Controller Module (SCSC) */
#define SCSC_SOSC_CTR_SOSC_EN 0x1