Merge branch 'master' of git://git.denx.de/u-boot

49 files changed, 3817 insertions, 1956 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cead0401cd..714dd8b514 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -406,6 +406,7 @@ config TARGET_BCMNSP
 config ARCH_EXYNOS
 	bool "Samsung EXYNOS"
 	select DM
+	select DM_I2C
 	select DM_SPI_FLASH
 	select DM_SERIAL
 	select DM_SPI
@@ -418,6 +419,7 @@ config ARCH_S5PC1XX
 	select DM
 	select DM_SERIAL
 	select DM_GPIO
+	select DM_I2C
 
 config ARCH_HIGHBANK
 	bool "Calxeda Highbank"
@@ -540,6 +542,7 @@ config ARCH_SOCFPGA
 	select DM
 	select DM_SPI_FLASH
 	select DM_SPI
+	select ENABLE_ARM_SOC_BOOT0_HOOK
 
 config TARGET_CM_T43
 	bool "Support cm_t43"
@@ -826,7 +829,6 @@ config TARGET_COLIBRI_PXA270
 
 config ARCH_UNIPHIER
 	bool "Socionext UniPhier SoCs"
-	select BLK
 	select CLK_UNIPHIER
 	select DM
 	select DM_GPIO
diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c
index 0588e2baef..30915d28aa 100644
--- a/arch/arm/cpu/armv7/arch_timer.c
+++ b/arch/arm/cpu/armv7/arch_timer.c
@@ -8,6 +8,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <div64.h>
+#include <bootstage.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -17,7 +18,6 @@ int timer_init(void)
 	gd->arch.tbu = 0;
 
 	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
-
 	return 0;
 }
 
@@ -39,6 +39,11 @@ ulong get_timer(ulong base)
 	return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base;
 }
 
+ulong timer_get_boot_us(void)
+{
+	return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000));
+}
+
 void __udelay(unsigned long usec)
 {
 	unsigned long long endtime;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index ed1c4eeb03..6772584a60 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -76,6 +76,13 @@ config SECURE_BOOT
 	help
 		Enable Freescale Secure Boot feature
 
+config QSPI_AHB_INIT
+	bool "Init the QSPI AHB bus"
+	help
+	  The default setting for QSPI AHB bus just support 3bytes addressing.
+	  But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
+	  bus for those flashes to support the full QSPI flash size.
+
 config SYS_FSL_IFC_BANK_COUNT
 	int "Maximum banks of Integrated flash controller"
 	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d6ee54642d..ffbbd729d4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -26,6 +26,9 @@
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include <asm/armv8/sec_firmware.h>
 #endif
+#ifdef CONFIG_SYS_FSL_DDR
+#include <fsl_ddr.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -403,7 +406,9 @@ int arch_early_init_r(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 	erratum_a009635();
 #endif
-
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
+	erratum_a009942_check_cpo();
+#endif
 #ifdef CONFIG_MP
 #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
 	/* Check the psci version to determine if the psci is supported */
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
index 67d605e38b..ab83e85adc 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
@@ -36,6 +36,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 	{0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
 	{0x39, {SGMII8, SGMII7, SGMII6, PCIE2, SGMII4, SGMII3, SGMII2,
 		PCIE1 } },
+	{0x3B, {XFI8, XFI7, XFI6, PCIE2, XFI4, XFI3, XFI2, PCIE1 } },
 	{0x4B, {PCIE2, PCIE2, PCIE2, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
 	{0x4C, {XFI8, XFI7, XFI6, XFI5, PCIE1, PCIE1, PCIE1, PCIE1 } },
 	{0x4D, {SGMII8, SGMII7, PCIE2, PCIE2, SGMII4, SGMII3, PCIE1, PCIE1 } },
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6c4238707d..2f54625d42 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -373,6 +373,45 @@ void fsl_lsch2_early_init_f(void)
 }
 #endif
 
+#ifdef CONFIG_QSPI_AHB_INIT
+/* Enable 4bytes address support and fast read */
+int qspi_ahb_init(void)
+{
+	u32 *qspi_lut, lut_key, *qspi_key;
+
+	qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
+	qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
+
+	lut_key = in_be32(qspi_key);
+
+	if (lut_key == 0x5af05af0) {
+		/* That means the register is BE */
+		out_be32(qspi_key, 0x5af05af0);
+		/* Unlock the lut table */
+		out_be32(qspi_key + 1, 0x00000002);
+		out_be32(qspi_lut, 0x0820040c);
+		out_be32(qspi_lut + 1, 0x1c080c08);
+		out_be32(qspi_lut + 2, 0x00002400);
+		/* Lock the lut table */
+		out_be32(qspi_key, 0x5af05af0);
+		out_be32(qspi_key + 1, 0x00000001);
+	} else {
+		/* That means the register is LE */
+		out_le32(qspi_key, 0x5af05af0);
+		/* Unlock the lut table */
+		out_le32(qspi_key + 1, 0x00000002);
+		out_le32(qspi_lut, 0x0820040c);
+		out_le32(qspi_lut + 1, 0x1c080c08);
+		out_le32(qspi_lut + 2, 0x00002400);
+		/* Lock the lut table */
+		out_le32(qspi_key, 0x5af05af0);
+		out_le32(qspi_key + 1, 0x00000001);
+	}
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
@@ -382,6 +421,9 @@ int board_late_init(void)
 #ifdef CONFIG_CHAIN_OF_TRUST
 	fsl_setenv_chain_of_trust();
 #endif
+#ifdef CONFIG_QSPI_AHB_INIT
+	qspi_ahb_init();
+#endif
 
 	return 0;
 }
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1964d3d9d1..f43746966c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -75,6 +75,7 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	armada-388-gp.dtb			\
 	armada-385-amc.dtb			\
 	armada-7040-db.dtb			\
+	armada-8040-db.dtb			\
 	armada-xp-gp.dtb			\
 	armada-xp-maxbcm.dtb			\
 	armada-xp-synology-ds414.dtb		\
@@ -132,6 +133,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_mcvevk.dtb			\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_de0_nano_soc.dtb			\
+	socfpga_cyclone5_de1_soc.dtb			\
 	socfpga_cyclone5_sockit.dtb			\
 	socfpga_cyclone5_socrates.dtb			\
 	socfpga_cyclone5_sr1500.dtb			\
diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index 7d0059afe5..466c6dcc3f 100644
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -66,36 +66,14 @@
 	};
 };
 
-&i2c0 {
-	status = "okay";
-	clock-frequency = <100000>;
-};
-
-&spi0 {
-	status = "okay";
-
-	spi-flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "U-Boot";
-				reg = <0 0x200000>;
-			};
-			partition@400000 {
-				label = "Filesystem";
-				reg = <0x200000 0xce0000>;
-			};
-		};
-	};
+&ap_pinctl {
+	   /* MPP Bus:
+	    * SDIO  [0-5]
+	    * UART0 [11,19]
+	    */
+		  /* 0 1 2 3 4 5 6 7 8 9 */
+	pin-func = < 1 1 1 1 1 1 0 0 0 0
+		     0 3 0 0 0 0 0 0 0 3 >;
 };
 
 &uart0 {
@@ -108,11 +86,37 @@
 };
 
 &cpm_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cpm_i2c0_pins>;
 	status = "okay";
 	clock-frequency = <100000>;
 };
 
+&cpm_pinctl {
+		/* MPP Bus:
+		 * TDM	 [0-11]
+		 * SPI   [13-16]
+		 * SATA1 [28]
+		 * UART0 [29-30]
+		 * SMI	 [32,34]
+		 * XSMI  [35-36]
+		 * I2C	 [37-38]
+		 * RGMII1[44-55]
+		 * SD	 [56-62]
+		 */
+		/*   0   1   2   3   4   5   6   7   8   9 */
+	pin-func = < 4   4   4   4   4   4   4   4   4   4
+		     4   4   0   3   3   3   3   0   0   0
+		     0   0   0   0   0   0   0   0   9   0xA
+		     0xA 0   7   0   7   7   7   2   2   0
+		     0   0   0   0   1   1   1   1   1   1
+		     1   1   1   1   1   1   0xE 0xE 0xE 0xE
+		     0xE 0xE 0xE >;
+};
+
 &cpm_spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cpm_spi0_pins>;
 	status = "okay";
 
 	spi-flash@0 {
@@ -152,7 +156,7 @@
 	status = "okay";
 };
 
-&comphy_cp110 {
+&cpm_comphy {
 	phy0 {
 		phy-type = <PHY_TYPE_SGMII2>;
 		phy-speed = <PHY_SPEED_3_125G>;
@@ -184,10 +188,10 @@
 	};
 };
 
-&utmi0 {
+&cpm_utmi0 {
 	status = "okay";
 };
 
-&utmi1 {
+&cpm_utmi1 {
 	status = "okay";
 };
diff --git a/arch/arm/dts/armada-8020.dtsi b/arch/arm/dts/armada-8020.dtsi
new file mode 100644
index 0000000000..048e5cf516
--- /dev/null
+++ b/arch/arm/dts/armada-8020.dtsi
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
+ * two CP110.
+ */
+
+#include "armada-ap806-dual.dtsi"
+#include "armada-cp110-master.dtsi"
+#include "armada-cp110-slave.dtsi"
+
+/ {
+	model = "Marvell Armada 8020";
+	compatible = "marvell,armada8020", "marvell,armada-ap806-dual",
+		     "marvell,armada-ap806";
+};
diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts
new file mode 100644
index 0000000000..40def9d6cd
--- /dev/null
+++ b/arch/arm/dts/armada-8040-db.dts
@@ -0,0 +1,285 @@
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada 8040 Development board platform
+ */
+
+#include "armada-8040.dtsi"
+
+/ {
+	model = "Marvell Armada 8040 DB board";
+	compatible = "marvell,armada8040-db", "marvell,armada8040",
+		     "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		i2c0 = &cpm_i2c0;
+		spi0 = &cps_spi1;
+	};
+
+	memory@00000000 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+};
+
+/* Accessible over the mini-USB CON9 connector on the main board */
+&uart0 {
+	status = "okay";
+};
+
+&ap_pinctl {
+	/* MPP Bus:
+	 * SDIO  [0-10]
+	 * UART0 [11,19]
+	 */
+		  /* 0 1 2 3 4 5 6 7 8 9 */
+	pin-func = < 1 1 1 1 1 1 1 1 1 1
+		     1 3 0 0 0 0 0 0 0 3 >;
+};
+
+&cpm_pinctl {
+	/* MPP Bus:
+	 * [0-31] = 0xff: Keep default CP0_shared_pins:
+	 * [11] CLKOUT_MPP_11 (out)
+	 * [23] LINK_RD_IN_CP2CP (in)
+	 * [25] CLKOUT_MPP_25 (out)
+	 * [29] AVS_FB_IN_CP2CP (in)
+	 * [32,34] SMI
+	 * [31]    GPIO: push button/Wake
+	 * [35-36] GPIO
+	 * [37-38] I2C
+	 * [40-41] SATA[0/1]_PRESENT_ACTIVEn
+	 * [42-43] XSMI
+	 * [44-55] RGMII1
+	 * [56-62] SD
+	 */
+		/*   0    1    2    3    4    5    6    7    8    9 */
+	pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0    7    0    7    0    0    2    2    0
+		     0    0    8    8    1    1    1    1    1    1
+		     1    1    1    1    1    1    0xe  0xe  0xe  0xe
+		     0xe  0xe  0xe >;
+};
+
+/* CON5 on CP0 expansion */
+&cpm_pcie2 {
+	status = "okay";
+};
+
+&cpm_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cpm_i2c0_pins>;
+	status = "okay";
+	clock-frequency = <100000>;
+};
+
+/* CON4 on CP0 expansion */
+&cpm_sata0 {
+	status = "okay";
+};
+
+/* CON9 on CP0 expansion */
+&cpm_usb3_0 {
+	status = "okay";
+};
+
+/* CON10 on CP0 expansion */
+&cpm_usb3_1 {
+	status = "okay";
+};
+
+&cps_pinctl {
+	/* MPP Bus:
+	 * [0-11]  RGMII0
+	 * [13-16] SPI1
+	 * [27,31] GE_MDIO/MDC
+	 * [32-62] = 0xff: Keep default CP1_shared_pins:
+	 */
+		/*   0    1    2    3    4    5    6    7    8    9 */
+	pin-func = < 0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3
+		     0x3  0x3  0xff 0x3  0x3  0x3  0x3  0xff 0xff 0xff
+		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8  0xff 0xff
+		     0xff 0x8  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0xff 0xff 0xff >;
+};
+
+/* CON5 on CP1 expansion */
+&cps_pcie2 {
+	status = "okay";
+};
+
+&cps_spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cps_spi1_pins>;
+	status = "okay";
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "U-Boot";
+				reg = <0 0x200000>;
+			};
+			partition@400000 {
+				label = "Filesystem";
+				reg = <0x200000 0xce0000>;
+			};
+		};
+	};
+};
+
+/* CON4 on CP1 expansion */
+&cps_sata0 {
+	status = "okay";
+};
+
+/* CON9 on CP1 expansion */
+&cps_usb3_0 {
+	status = "okay";
+};
+
+/* CON10 on CP1 expansion */
+&cps_usb3_1 {
+	status = "okay";
+};
+
+&cpm_comphy {
+	/*
+	 * Serdes Configuration:
+	 * Lane 0: SGMII2
+	 * Lane 1: USB3_HOST0
+	 * Lane 2: KR (10G)
+	 * Lane 3: SATA1
+	 * Lane 4: USB3_HOST1
+	 * Lane 5: PEX2x1
+	 */
+	phy0 {
+		phy-type = <PHY_TYPE_SGMII2>;
+		phy-speed = <PHY_SPEED_3_125G>;
+	};
+
+	phy1 {
+		phy-type = <PHY_TYPE_USB3_HOST0>;
+	};
+
+	phy2 {
+		phy-type = <PHY_TYPE_KR>;
+	};
+
+	phy3 {
+		phy-type = <PHY_TYPE_SATA1>;
+	};
+
+	phy4 {
+		phy-type = <PHY_TYPE_USB3_HOST1>;
+	};
+
+	phy5 {
+		phy-type = <PHY_TYPE_PEX2>;
+	};
+};
+
+&cps_comphy {
+	/*
+	 * Serdes Configuration:
+	 * Lane 0: SGMII2
+	 * Lane 1: USB3_HOST0
+	 * Lane 2: KR (10G)
+	 * Lane 3: SATA1
+	 * Lane 4: Unconnected
+	 * Lane 5: PEX2x1
+	 */
+	phy0 {
+		phy-type = <PHY_TYPE_SGMII2>;
+		phy-speed = <PHY_SPEED_3_125G>;
+	};
+
+	phy1 {
+		phy-type = <PHY_TYPE_USB3_HOST0>;
+	};
+
+	phy2 {
+		phy-type = <PHY_TYPE_KR>;
+	};
+
+	phy3 {
+		phy-type = <PHY_TYPE_SATA1>;
+	};
+
+	phy4 {
+		phy-type = <PHY_TYPE_UNCONNECTED>;
+	};
+
+	phy5 {
+		phy-type = <PHY_TYPE_PEX2>;
+	};
+};
+
+&cpm_utmi0 {
+	status = "okay";
+};
+
+&cpm_utmi1 {
+	status = "okay";
+};
+
+&cps_utmi0 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/armada-8040.dtsi b/arch/arm/dts/armada-8040.dtsi
new file mode 100644
index 0000000000..9c1b28c476
--- /dev/null
+++ b/arch/arm/dts/armada-8040.dtsi
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and
+ * two CP110.
+ */
+
+#include "armada-ap806-quad.dtsi"
+#include "armada-cp110-master.dtsi"
+#include "armada-cp110-slave.dtsi"
+
+/ {
+	model = "Marvell Armada 8040";
+	compatible = "marvell,armada8040", "marvell,armada-ap806-quad",
+		     "marvell,armada-ap806";
+};
diff --git a/arch/arm/dts/armada-ap806.dtsi b/arch/arm/dts/armada-ap806.dtsi
index d315b29cd0..efb383b9f3 100644
--- a/arch/arm/dts/armada-ap806.dtsi
+++ b/arch/arm/dts/armada-ap806.dtsi
@@ -140,6 +140,24 @@
 				marvell,spi-base = <128>, <136>, <144>, <152>;
 			};
 
+			ap_pinctl: ap-pinctl@6F4000 {
+				compatible = "marvell,armada-ap806-pinctrl";
+				bank-name ="apn-806";
+				reg = <0x6F4000 0x10>;
+				pin-count = <20>;
+				max-func = <3>;
+
+				ap_i2c0_pins: i2c-pins-0 {
+					marvell,pins = < 4 5 >;
+					marvell,function = <3>;
+				};
+				ap_emmc_pins: emmc-pins-0 {
+					marvell,pins = < 0 1 2 3 4 5 6 7
+							 8 9 10 >;
+					marvell,function = <1>;
+				};
+			};
+
 			xor@400000 {
 				compatible = "marvell,mv-xor-v2";
 				reg = <0x400000 0x1000>,
diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi
index 7da98bf5cb..d637867615 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -81,6 +81,38 @@
 					"cpm-usb3dev", "cpm-eip150", "cpm-eip197";
 			};
 
+			cpm_pinctl: cpm-pinctl@440000 {
+				compatible = "marvell,mvebu-pinctrl",
+					     "marvell,a70x0-pinctrl",
+					     "marvell,a80x0-cp0-pinctrl";
+				bank-name ="cp0-110";
+				reg = <0x440000 0x20>;
+				pin-count = <63>;
+				max-func = <0xf>;
+
+				cpm_i2c0_pins: cpm-i2c-pins-0 {
+					marvell,pins = < 37 38 >;
+					marvell,function = <2>;
+				};
+				cpm_ge2_rgmii_pins: cpm-ge-rgmii-pins-0 {
+					marvell,pins = < 44 45 46 47 48 49 50 51
+							 52 53 54 55 >;
+					marvell,function = <1>;
+				};
+				pca0_pins: cpm-pca0_pins {
+					marvell,pins = <62>;
+					marvell,function = <0>;
+				};
+				cpm_sdhci_pins: cpm-sdhi-pins-0 {
+					marvell,pins = < 56 57 58 59 60 61 >;
+					marvell,function = <14>;
+				};
+				cpm_spi0_pins: cpm-spi-pins-0 {
+					marvell,pins = < 13 14 15 16 >;
+					marvell,function = <3>;
+				};
+			};
+
 			cpm_sata0: sata@540000 {
 				compatible = "marvell,armada-8k-ahci";
 				reg = <0x540000 0x30000>;
@@ -149,7 +181,7 @@
 				status = "disabled";
 			};
 
-			comphy_cp110: comphy@441000 {
+			cpm_comphy: comphy@441000 {
 				compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
 				reg = <0x441000 0x8>,
 				      <0x120000 0x8>;
@@ -157,7 +189,7 @@
 				max-lanes = <6>;
 			};
 
-			utmi0: utmi@580000 {
+			cpm_utmi0: utmi@580000 {
 				compatible = "marvell,mvebu-utmi-2.6.0";
 				reg = <0x580000 0x1000>,	/* utmi-unit */
 				      <0x440420 0x4>,		/* usb-cfg */
@@ -166,7 +198,7 @@
 				status = "disabled";
 			};
 
-			utmi1: utmi@581000 {
+			cpm_utmi1: utmi@581000 {
 				compatible = "marvell,mvebu-utmi-2.6.0";
 				reg = <0x581000 0x1000>,	/* utmi-unit */
 				      <0x440420 0x4>,		/* usb-cfg */
diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi
new file mode 100644
index 0000000000..92ef55cf26
--- /dev/null
+++ b/arch/arm/dts/armada-cp110-slave.dtsi
@@ -0,0 +1,287 @@
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada CP110 Slave.
+ */
+
+#include <dt-bindings/comphy/comphy_data.h>
+
+/ {
+	cp110-slave {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		config-space {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			interrupt-parent = <&gic>;
+			ranges = <0x0 0x0 0xf4000000 0x2000000>;
+
+			cps_syscon0: system-controller@440000 {
+				compatible = "marvell,cp110-system-controller0",
+					     "syscon";
+				reg = <0x440000 0x1000>;
+				#clock-cells = <2>;
+				core-clock-output-names =
+					"cps-apll", "cps-ppv2-core", "cps-eip",
+					"cps-core", "cps-nand-core";
+				gate-clock-output-names =
+					"cps-audio", "cps-communit", "cps-nand",
+					"cps-ppv2", "cps-sdio", "cps-mg-domain",
+					"cps-mg-core", "cps-xor1", "cps-xor0",
+					"cps-gop-dp", "none", "cps-pcie_x10",
+					"cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
+					"cps-sata", "cps-sata-usb", "cps-main",
+					"cps-sd-mmc", "none", "none",
+					"cps-slow-io", "cps-usb3h0", "cps-usb3h1",
+					"cps-usb3dev", "cps-eip150", "cps-eip197";
+			};
+
+			cps_pinctl: cps-pinctl@440000 {
+				compatible = "marvell,mvebu-pinctrl",
+					     "marvell,a80x0-cp1-pinctrl";
+				bank-name ="cp1-110";
+				reg = <0x440000 0x20>;
+				pin-count = <63>;
+				max-func = <0xf>;
+
+				cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 {
+					marvell,pins = < 0  1  2  3  4  5  6  7
+							 8  9  10 11 >;
+					marvell,function = <3>;
+				};
+				cps_spi1_pins: cps-spi-pins-1 {
+					marvell,pins = < 13 14 15 16 >;
+					marvell,function = <3>;
+				};
+			};
+
+			cps_sata0: sata@540000 {
+				compatible = "marvell,armada-8k-ahci";
+				reg = <0x540000 0x30000>;
+				interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cps_syscon0 1 15>;
+				status = "disabled";
+			};
+
+			cps_usb3_0: usb3@500000 {
+				compatible = "marvell,armada-8k-xhci",
+					     "generic-xhci";
+				reg = <0x500000 0x4000>;
+				dma-coherent;
+				interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cps_syscon0 1 22>;
+				status = "disabled";
+			};
+
+			cps_usb3_1: usb3@510000 {
+				compatible = "marvell,armada-8k-xhci",
+					     "generic-xhci";
+				reg = <0x510000 0x4000>;
+				dma-coherent;
+				interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cps_syscon0 1 23>;
+				status = "disabled";
+			};
+
+			cps_xor0: xor@6a0000 {
+				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+				reg = <0x6a0000 0x1000>,
+				      <0x6b0000 0x1000>;
+				dma-coherent;
+				msi-parent = <&gic_v2m0>;
+				clocks = <&cps_syscon0 1 8>;
+			};
+
+			cps_xor1: xor@6c0000 {
+				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+				reg = <0x6c0000 0x1000>,
+				      <0x6d0000 0x1000>;
+				dma-coherent;
+				msi-parent = <&gic_v2m0>;
+				clocks = <&cps_syscon0 1 7>;
+			};
+
+			cps_spi0: spi@700600 {
+				compatible = "marvell,armada-380-spi";
+				reg = <0x700600 0x50>;
+				#address-cells = <0x1>;
+				#size-cells = <0x0>;
+				cell-index = <1>;
+				clocks = <&cps_syscon0 0 3>;
+				status = "disabled";
+			};
+
+			cps_spi1: spi@700680 {
+				compatible = "marvell,armada-380-spi";
+				reg = <0x700680 0x50>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				cell-index = <2>;
+				clocks = <&cps_syscon0 1 21>;
+				status = "disabled";
+			};
+
+			cps_i2c0: i2c@701000 {
+				compatible = "marvell,mv78230-i2c";
+				reg = <0x701000 0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cps_syscon0 1 21>;
+				status = "disabled";
+			};
+
+			cps_i2c1: i2c@701100 {
+				compatible = "marvell,mv78230-i2c";
+				reg = <0x701100 0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cps_syscon0 1 21>;
+				status = "disabled";
+			};
+
+			cps_comphy: comphy@441000 {
+				compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
+				reg = <0x441000 0x8>,
+				      <0x120000 0x8>;
+				mux-bitcount = <4>;
+				max-lanes = <6>;
+			};
+
+			cps_utmi0: utmi@580000 {
+				compatible = "marvell,mvebu-utmi-2.6.0";
+				reg = <0x580000 0x1000>,	/* utmi-unit */
+				      <0x440420 0x4>,		/* usb-cfg */
+				      <0x440440 0x4>;		/* utmi-cfg */
+				utmi-port = <UTMI_PHY_TO_USB_HOST0>;
+				status = "disabled";
+			};
+		};
+
+		cps_pcie0: pcie@f4600000 {
+			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+			reg = <0 0xf4600000 0 0x10000>,
+			      <0 0xfaf00000 0 0x80000>;
+			reg-names = "ctrl", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			device_type = "pci";
+			dma-coherent;
+			msi-parent = <&gic_v2m0>;
+
+			bus-range = <0 0xff>;
+			ranges =
+				/* downstream I/O */
+				<0x81000000 0 0xfd000000 0  0xfd000000 0 0x10000
+				/* non-prefetchable memory */
+				0x82000000 0 0xfa000000 0  0xfa000000 0 0xf00000>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+			num-lanes = <1>;
+			clocks = <&cps_syscon0 1 13>;
+			status = "disabled";
+		};
+
+		cps_pcie1: pcie@f4620000 {
+			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+			reg = <0 0xf4620000 0 0x10000>,
+			      <0 0xfbf00000 0 0x80000>;
+			reg-names = "ctrl", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			device_type = "pci";
+			dma-coherent;
+			msi-parent = <&gic_v2m0>;
+
+			bus-range = <0 0xff>;
+			ranges =
+				/* downstream I/O */
+				<0x81000000 0 0xfd010000 0  0xfd010000 0 0x10000
+				/* non-prefetchable memory */
+				0x82000000 0 0xfb000000 0  0xfb000000 0 0xf00000>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
+
+			num-lanes = <1>;
+			clocks = <&cps_syscon0 1 11>;
+			status = "disabled";
+		};
+
+		cps_pcie2: pcie@f4640000 {
+			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+			reg = <0 0xf4640000 0 0x10000>,
+			      <0 0xfcf00000 0 0x80000>;
+			reg-names = "ctrl", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			device_type = "pci";
+			dma-coherent;
+			msi-parent = <&gic_v2m0>;
+
+			bus-range = <0 0xff>;
+			ranges =
+				/* downstream I/O */
+				<0x81000000 0 0xfd020000 0  0xfd020000 0 0x10000
+				/* non-prefetchable memory */
+				0x82000000 0 0xfc000000 0  0xfc000000 0 0xf00000>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
+
+			num-lanes = <1>;
+			clocks = <&cps_syscon0 1 12>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 119b1afeb7..37be16905b 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -176,6 +176,7 @@
 			#size-cells = <0>;
 			reg = <0x1550000 0x10000>,
 				<0x40000000 0x4000000>;
+			reg-names = "QuadSPI", "QuadSPI-memory";
 			num-cs = <2>;
 			big-endian;
 			status = "disabled";
diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
new file mode 100644
index 0000000000..a583990aec
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
@@ -0,0 +1,66 @@
+/*
+ * Copyright Altera Corporation (C) 2015
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+	model = "Terasic DE1-SoC";
+	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	aliases {
+		ethernet0 = &gmac1;
+		udc0 = &usb1;
+	};
+
+	memory {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>; /* 1GB */
+	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&gmac1 {
+	status = "okay";
+	phy-mode = "rgmii";
+
+	rxd0-skew-ps = <420>;
+	rxd1-skew-ps = <420>;
+	rxd2-skew-ps = <420>;
+	rxd3-skew-ps = <420>;
+	txen-skew-ps = <0>;
+	txc-skew-ps = <1860>;
+	rxdv-skew-ps = <420>;
+	rxc-skew-ps = <1680>;
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&mmc0 {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&usb1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi
deleted file mode 100644
index f87e320830..0000000000
--- a/arch/arm/dts/uniphier-common32.dtsi
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Device Tree Source commonly used by UniPhier ARM SoCs
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+	X11
- */
-
-/include/ "skeleton.dtsi"
-
-/ {
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	clocks {
-		refclk: ref {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-		};
-	};
-
-	soc: soc {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-		interrupt-parent = <&intc>;
-		u-boot,dm-pre-reloc;
-
-		serial0: serial@54006800 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006800 0x40>;
-			interrupts = <0 33 4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart0>;
-			clocks = <&peri_clk 0>;
-		};
-
-		serial1: serial@54006900 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006900 0x40>;
-			interrupts = <0 35 4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart1>;
-			clocks = <&peri_clk 1>;
-		};
-
-		serial2: serial@54006a00 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006a00 0x40>;
-			interrupts = <0 37 4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart2>;
-			clocks = <&peri_clk 2>;
-		};
-
-		serial3: serial@54006b00 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006b00 0x40>;
-			interrupts = <0 177 4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart3>;
-			clocks = <&peri_clk 3>;
-		};
-
-		system_bus: system-bus@58c00000 {
-			compatible = "socionext,uniphier-system-bus";
-			status = "disabled";
-			reg = <0x58c00000 0x400>;
-			#address-cells = <2>;
-			#size-cells = <1>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_system_bus>;
-		};
-
-		smpctrl@59800000 {
-			compatible = "socionext,uniphier-smpctrl";
-			reg = <0x59801000 0x400>;
-		};
-
-		mioctrl@59810000 {
-			compatible = "socionext,uniphier-mioctrl",
-				     "simple-mfd", "syscon";
-			reg = <0x59810000 0x800>;
-			u-boot,dm-pre-reloc;
-
-			mio_clk: clock {
-				#clock-cells = <1>;
-			};
-
-			mio_rst: reset {
-				#reset-cells = <1>;
-			};
-		};
-
-		perictrl@59820000 {
-			compatible = "socionext,uniphier-perictrl",
-				     "simple-mfd", "syscon";
-			reg = <0x59820000 0x200>;
-
-			peri_clk: clock {
-				#clock-cells = <1>;
-			};
-
-			peri_rst: reset {
-				#reset-cells = <1>;
-			};
-		};
-
-		timer@60000200 {
-			compatible = "arm,cortex-a9-global-timer";
-			reg = <0x60000200 0x20>;
-			interrupts = <1 11 0x104>;
-			clocks = <&arm_timer_clk>;
-		};
-
-		timer@60000600 {
-			compatible = "arm,cortex-a9-twd-timer";
-			reg = <0x60000600 0x20>;
-			interrupts = <1 13 0x104>;
-			clocks = <&arm_timer_clk>;
-		};
-
-		intc: interrupt-controller@60001000 {
-			compatible = "arm,cortex-a9-gic";
-			reg = <0x60001000 0x1000>,
-			      <0x60000100 0x100>;
-			#interrupt-cells = <3>;
-			interrupt-controller;
-		};
-
-		soc-glue@5f800000 {
-			compatible = "socionext,uniphier-soc-glue",
-				     "simple-mfd", "syscon";
-			reg = <0x5f800000 0x2000>;
-			u-boot,dm-pre-reloc;
-
-			pinctrl: pinctrl {
-				/* specify compatible in each SoC DTSI */
-				u-boot,dm-pre-reloc;
-			};
-		};
-
-		sysctrl@61840000 {
-			compatible = "socionext,uniphier-sysctrl",
-				     "simple-mfd", "syscon";
-			reg = <0x61840000 0x4000>;
-
-			sys_clk: clock {
-				#clock-cells = <1>;
-			};
-
-			sys_rst: reset {
-				#reset-cells = <1>;
-			};
-		};
-
-		nand: nand@68000000 {
-			compatible = "denali,denali-nand-dt";
-			status = "disabled";
-			reg-names = "nand_data", "denali_reg";
-			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
-			interrupts = <0 65 4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_nand>;
-		};
-	};
-};
-
-/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi
index a95cb6e97b..eef4dcefbc 100644
--- a/arch/arm/dts/uniphier-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -7,7 +7,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/memreserve/ 0x80000000 0x00000008;	/* cpu-release-addr */
+/memreserve/ 0x80000000 0x00080000;
 
 / {
 	compatible = "socionext,uniphier-ld11";
@@ -34,31 +34,66 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x000>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000000>;
+			clocks = <&sys_clk 33>;
+			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu1: cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x001>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000000>;
+			clocks = <&sys_clk 33>;
+			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 	};
 
+	cluster0_opp: opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@245000000 {
+			opp-hz = /bits/ 64 <245000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@250000000 {
+			opp-hz = /bits/ 64 <250000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@490000000 {
+			opp-hz = /bits/ 64 <490000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@653334000 {
+			opp-hz = /bits/ 64 <653334000>;
+			clock-latency-ns = <300>;
+		};
+		opp@666667000 {
+			opp-hz = /bits/ 64 <666667000>;
+			clock-latency-ns = <300>;
+		};
+		opp@980000000 {
+			opp-hz = /bits/ 64 <980000000>;
+			clock-latency-ns = <300>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
 	clocks {
 		refclk: ref {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <25000000>;
 		};
-
-		i2c_clk: i2c_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <50000000>;
-		};
 	};
 
 	timer {
@@ -129,7 +164,7 @@
 			interrupts = <0 41 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_i2c0>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 4>;
 			clock-frequency = <100000>;
 		};
 
@@ -142,7 +177,7 @@
 			interrupts = <0 42 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_i2c1>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 5>;
 			clock-frequency = <100000>;
 		};
 
@@ -152,7 +187,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 43 4>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 6>;
 			clock-frequency = <400000>;
 		};
 
@@ -165,7 +200,7 @@
 			interrupts = <0 44 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_i2c3>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 7>;
 			clock-frequency = <100000>;
 		};
 
@@ -178,7 +213,7 @@
 			interrupts = <0 45 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_i2c4>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 8>;
 			clock-frequency = <100000>;
 		};
 
@@ -188,7 +223,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 25 4>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 9>;
 			clock-frequency = <400000>;
 		};
 
@@ -207,8 +242,19 @@
 			reg = <0x59801000 0x400>;
 		};
 
+		sdctrl@59810000 {
+			compatible = "socionext,uniphier-ld11-sdctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59810000 0x400>;
+
+			sd_rst: reset {
+				compatible = "socionext,uniphier-ld11-sd-reset";
+				#reset-cells = <1>;
+			};
+		};
+
 		perictrl@59820000 {
-			compatible = "socionext,uniphier-perictrl",
+			compatible = "socionext,uniphier-ld11-perictrl",
 				     "simple-mfd", "syscon";
 			reg = <0x59820000 0x200>;
 
@@ -223,6 +269,19 @@
 			};
 		};
 
+		emmc: sdhc@5a000000 {
+			compatible = "cdns,sd4hc";
+			reg = <0x5a000000 0x400>;
+			interrupts = <0 78 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_emmc_1v8>;
+			clocks = <&sys_clk 4>;
+			bus-width = <8>;
+			mmc-ddr-1_8v;
+			mmc-hs200-1_8v;
+			/* mmc-hs400-1_8v; support depends on board design */
+		};
+
 		usb0: usb@5a800100 {
 			compatible = "socionext,uniphier-ehci", "generic-ehci";
 			status = "disabled";
@@ -277,7 +336,7 @@
 		};
 
 		soc-glue@5f800000 {
-			compatible = "socionext,uniphier-soc-glue",
+			compatible = "socionext,uniphier-ld11-soc-glue",
 				     "simple-mfd", "syscon";
 			reg = <0x5f800000 0x2000>;
 			u-boot,dm-pre-reloc;
@@ -305,7 +364,7 @@
 		sysctrl@61840000 {
 			compatible = "socionext,uniphier-ld11-sysctrl",
 				     "simple-mfd", "syscon";
-			reg = <0x61840000 0x4000>;
+			reg = <0x61840000 0x10000>;
 
 			sys_clk: clock {
 				compatible = "socionext,uniphier-ld11-clock";
@@ -317,6 +376,18 @@
 				#reset-cells = <1>;
 			};
 		};
+
+		nand: nand@68000000 {
+			compatible = "socionext,denali-nand-v5b";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+			clocks = <&sys_clk 2>;
+			nand-ecc-strength = <8>;
+		};
 	};
 };
 
diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi
index 29a84aeccd..1b41945ead 100644
--- a/arch/arm/dts/uniphier-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -7,7 +7,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/memreserve/ 0x80000000 0x00000008;	/* cpu-release-addr */
+/memreserve/ 0x80000000 0x00080000;
 
 / {
 	compatible = "socionext,uniphier-ld20";
@@ -43,47 +43,126 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a72", "arm,armv8";
 			reg = <0 0x000>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000000>;
+			clocks = <&sys_clk 32>;
+			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu1: cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a72", "arm,armv8";
 			reg = <0 0x001>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000000>;
+			clocks = <&sys_clk 32>;
+			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu2: cpu@100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x100>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000000>;
+			clocks = <&sys_clk 33>;
+			enable-method = "psci";
+			operating-points-v2 = <&cluster1_opp>;
 		};
 
 		cpu3: cpu@101 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x101>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000000>;
+			clocks = <&sys_clk 33>;
+			enable-method = "psci";
+			operating-points-v2 = <&cluster1_opp>;
 		};
 	};
 
+	cluster0_opp: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@250000000 {
+			opp-hz = /bits/ 64 <250000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@275000000 {
+			opp-hz = /bits/ 64 <275000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@550000000 {
+			opp-hz = /bits/ 64 <550000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@666667000 {
+			opp-hz = /bits/ 64 <666667000>;
+			clock-latency-ns = <300>;
+		};
+		opp@733334000 {
+			opp-hz = /bits/ 64 <733334000>;
+			clock-latency-ns = <300>;
+		};
+		opp@1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@1100000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			clock-latency-ns = <300>;
+		};
+	};
+
+	cluster1_opp: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@250000000 {
+			opp-hz = /bits/ 64 <250000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@275000000 {
+			opp-hz = /bits/ 64 <275000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@550000000 {
+			opp-hz = /bits/ 64 <550000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@666667000 {
+			opp-hz = /bits/ 64 <666667000>;
+			clock-latency-ns = <300>;
+		};
+		opp@733334000 {
+			opp-hz = /bits/ 64 <733334000>;
+			clock-latency-ns = <300>;
+		};
+		opp@1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@1100000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			clock-latency-ns = <300>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
 	clocks {
 		refclk: ref {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <25000000>;
 		};
-
-		i2c_clk: i2c_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <50000000>;
-		};
 	};
 
 	timer {
@@ -154,7 +233,7 @@
 			interrupts = <0 41 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_i2c0>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 4>;
 			clock-frequency = <100000>;
 		};
 
@@ -167,7 +246,7 @@
 			interrupts = <0 42 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_i2c1>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 5>;
 			clock-frequency = <100000>;
 		};
 
@@ -177,7 +256,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 43 4>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 6>;
 			clock-frequency = <400000>;
 		};
 
@@ -190,7 +269,7 @@
 			interrupts = <0 44 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_i2c3>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 7>;
 			clock-frequency = <100000>;
 		};
 
@@ -203,7 +282,7 @@
 			interrupts = <0 45 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_i2c4>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 8>;
 			clock-frequency = <100000>;
 		};
 
@@ -213,7 +292,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 25 4>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 9>;
 			clock-frequency = <400000>;
 		};
 
@@ -232,24 +311,24 @@
 			reg = <0x59801000 0x400>;
 		};
 
-		mioctrl@59810000 {
-			compatible = "socionext,uniphier-mioctrl",
+		sdctrl@59810000 {
+			compatible = "socionext,uniphier-ld20-sdctrl",
 				     "simple-mfd", "syscon";
 			reg = <0x59810000 0x800>;
 
-			mio_clk: clock {
-				compatible = "socionext,uniphier-ld20-mio-clock";
+			sd_clk: clock {
+				compatible = "socionext,uniphier-ld20-sd-clock";
 				#clock-cells = <1>;
 			};
 
-			mio_rst: reset {
-				compatible = "socionext,uniphier-ld20-mio-reset";
+			sd_rst: reset {
+				compatible = "socionext,uniphier-ld20-sd-reset";
 				#reset-cells = <1>;
 			};
 		};
 
 		perictrl@59820000 {
-			compatible = "socionext,uniphier-perictrl",
+			compatible = "socionext,uniphier-ld20-perictrl",
 				     "simple-mfd", "syscon";
 			reg = <0x59820000 0x200>;
 
@@ -264,6 +343,19 @@
 			};
 		};
 
+		emmc: sdhc@5a000000 {
+			compatible = "cdns,sd4hc";
+			reg = <0x5a000000 0x400>;
+			interrupts = <0 78 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_emmc_1v8>;
+			clocks = <&sys_clk 4>;
+			bus-width = <8>;
+			mmc-ddr-1_8v;
+			mmc-hs200-1_8v;
+			/* mmc-hs400-1_8v; support depends on board design */
+		};
+
 		sd: sdhc@5a400000 {
 			compatible = "socionext,uniphier-sdhc";
 			status = "disabled";
@@ -271,14 +363,15 @@
 			interrupts = <0 76 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_sd>;
-			clocks = <&mio_clk 0>;
+			clocks = <&sd_clk 0>;
 			reset-names = "host";
-			resets = <&mio_rst 0>;
+			resets = <&sd_rst 0>;
 			bus-width = <4>;
+			cap-sd-highspeed;
 		};
 
 		soc-glue@5f800000 {
-			compatible = "socionext,uniphier-soc-glue",
+			compatible = "socionext,uniphier-ld20-soc-glue",
 				     "simple-mfd", "syscon";
 			reg = <0x5f800000 0x2000>;
 			u-boot,dm-pre-reloc;
@@ -304,9 +397,9 @@
 		};
 
 		sysctrl@61840000 {
-			compatible = "socionext,uniphier-sysctrl",
+			compatible = "socionext,uniphier-ld20-sysctrl",
 				     "simple-mfd", "syscon";
-			reg = <0x61840000 0x4000>;
+			reg = <0x61840000 0x10000>;
 
 			sys_clk: clock {
 				compatible = "socionext,uniphier-ld20-clock";
@@ -318,6 +411,35 @@
 				#reset-cells = <1>;
 			};
 		};
+
+		usb: usb@65b00000 {
+			compatible = "socionext,uniphier-ld20-dwc3";
+			reg = <0x65b00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
+				    <&pinctrl_usb2>, <&pinctrl_usb3>;
+			dwc3@65a00000 {
+				compatible = "snps,dwc3";
+				reg = <0x65a00000 0x10000>;
+				interrupts = <0 134 4>;
+				tx-fifo-resize;
+			};
+		};
+
+		nand: nand@68000000 {
+			compatible = "socionext,denali-nand-v5b";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+			clocks = <&sys_clk 2>;
+			nand-ecc-strength = <8>;
+		};
 	};
 };
 
diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi
index 9f555df652..bbfa164c92 100644
--- a/arch/arm/dts/uniphier-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ld4.dtsi
@@ -7,7 +7,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/include/ "uniphier-common32.dtsi"
+/include/ "skeleton.dtsi"
 
 / {
 	compatible = "socionext,uniphier-ld4";
@@ -25,313 +25,438 @@
 		};
 	};
 
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
 	clocks {
-		arm_timer_clk: arm_timer_clk {
-			#clock-cells = <0>;
+		refclk: ref {
 			compatible = "fixed-clock";
-			clock-frequency = <50000000>;
+			#clock-cells = <0>;
+			clock-frequency = <24576000>;
 		};
 
-		iobus_clk: iobus_clk {
+		arm_timer_clk: arm_timer_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
-			clock-frequency = <100000000>;
+			clock-frequency = <50000000>;
 		};
 	};
-};
 
-&soc {
-	l2: l2-cache@500c0000 {
-		compatible = "socionext,uniphier-system-cache";
-		reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
-		interrupts = <0 174 4>, <0 175 4>;
-		cache-unified;
-		cache-size = <(512 * 1024)>;
-		cache-sets = <256>;
-		cache-line-size = <128>;
-		cache-level = <2>;
-	};
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		interrupt-parent = <&intc>;
+		u-boot,dm-pre-reloc;
+
+		l2: l2-cache@500c0000 {
+			compatible = "socionext,uniphier-system-cache";
+			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+			      <0x506c0000 0x400>;
+			interrupts = <0 174 4>, <0 175 4>;
+			cache-unified;
+			cache-size = <(512 * 1024)>;
+			cache-sets = <256>;
+			cache-line-size = <128>;
+			cache-level = <2>;
+		};
 
-	port0x: gpio@55000008 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000008 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial0: serial@54006800 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006800 0x40>;
+			interrupts = <0 33 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart0>;
+			clocks = <&peri_clk 0>;
+			clock-frequency = <36864000>;
+		};
 
-	port1x: gpio@55000010 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000010 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial1: serial@54006900 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006900 0x40>;
+			interrupts = <0 35 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart1>;
+			clocks = <&peri_clk 1>;
+			clock-frequency = <36864000>;
+		};
 
-	port2x: gpio@55000018 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000018 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial2: serial@54006a00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006a00 0x40>;
+			interrupts = <0 37 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart2>;
+			clocks = <&peri_clk 2>;
+			clock-frequency = <36864000>;
+		};
 
-	port3x: gpio@55000020 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000020 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial3: serial@54006b00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006b00 0x40>;
+			interrupts = <0 29 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart3>;
+			clocks = <&peri_clk 3>;
+			clock-frequency = <36864000>;
+		};
 
-	port4: gpio@55000028 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000028 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port0x: gpio@55000008 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000008 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port5x: gpio@55000030 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000030 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port1x: gpio@55000010 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000010 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port6x: gpio@55000038 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000038 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port2x: gpio@55000018 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000018 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port7x: gpio@55000040 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000040 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port3x: gpio@55000020 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000020 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port8x: gpio@55000048 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000048 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port4: gpio@55000028 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000028 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port9x: gpio@55000050 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000050 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port5x: gpio@55000030 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000030 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port10x: gpio@55000058 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000058 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port6x: gpio@55000038 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000038 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port11x: gpio@55000060 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000060 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port7x: gpio@55000040 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000040 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port12x: gpio@55000068 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000068 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port8x: gpio@55000048 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000048 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port13x: gpio@55000070 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000070 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port9x: gpio@55000050 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000050 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port14x: gpio@55000078 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000078 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port10x: gpio@55000058 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000058 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port16x: gpio@55000088 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000088 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port11x: gpio@55000060 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000060 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c0: i2c@58400000 {
-		compatible = "socionext,uniphier-i2c";
-		status = "disabled";
-		reg = <0x58400000 0x40>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 41 1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c0>;
-		clocks = <&iobus_clk>;
-		clock-frequency = <100000>;
-	};
+		port12x: gpio@55000068 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000068 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c1: i2c@58480000 {
-		compatible = "socionext,uniphier-i2c";
-		status = "disabled";
-		reg = <0x58480000 0x40>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 42 1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c1>;
-		clocks = <&iobus_clk>;
-		clock-frequency = <100000>;
-	};
+		port13x: gpio@55000070 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000070 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	/* chip-internal connection for DMD */
-	i2c2: i2c@58500000 {
-		compatible = "socionext,uniphier-i2c";
-		reg = <0x58500000 0x40>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 43 1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c2>;
-		clocks = <&iobus_clk>;
-		clock-frequency = <400000>;
-	};
+		port14x: gpio@55000078 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000078 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c3: i2c@58580000 {
-		compatible = "socionext,uniphier-i2c";
-		status = "disabled";
-		reg = <0x58580000 0x40>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 44 1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c3>;
-		clocks = <&iobus_clk>;
-		clock-frequency = <100000>;
-	};
+		port16x: gpio@55000088 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000088 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	sd: sdhc@5a400000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x5a400000 0x200>;
-		interrupts = <0 76 4>;
-		pinctrl-names = "default", "1.8v";
-		pinctrl-0 = <&pinctrl_sd>;
-		pinctrl-1 = <&pinctrl_sd_1v8>;
-		clocks = <&mio_clk 0>;
-		reset-names = "host", "bridge";
-		resets = <&mio_rst 0>, <&mio_rst 3>;
-		bus-width = <4>;
-	};
+		i2c0: i2c@58400000 {
+			compatible = "socionext,uniphier-i2c";
+			status = "disabled";
+			reg = <0x58400000 0x40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 41 1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c0>;
+			clocks = <&peri_clk 4>;
+			clock-frequency = <100000>;
+		};
 
-	emmc: sdhc@5a500000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x5a500000 0x200>;
-		interrupts = <0 78 4>;
-		pinctrl-names = "default", "1.8v";
-		pinctrl-0 = <&pinctrl_emmc>;
-		pinctrl-1 = <&pinctrl_emmc_1v8>;
-		clocks = <&mio_clk 1>;
-		reset-names = "host", "bridge", "hw-reset";
-		resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
-		bus-width = <8>;
-		non-removable;
-	};
+		i2c1: i2c@58480000 {
+			compatible = "socionext,uniphier-i2c";
+			status = "disabled";
+			reg = <0x58480000 0x40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 42 1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c1>;
+			clocks = <&peri_clk 5>;
+			clock-frequency = <100000>;
+		};
 
-	usb0: usb@5a800100 {
-		compatible = "socionext,uniphier-ehci", "generic-ehci";
-		status = "disabled";
-		reg = <0x5a800100 0x100>;
-		interrupts = <0 80 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb0>;
-		clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
-		resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
-			 <&mio_rst 12>;
-	};
+		/* chip-internal connection for DMD */
+		i2c2: i2c@58500000 {
+			compatible = "socionext,uniphier-i2c";
+			reg = <0x58500000 0x40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 43 1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c2>;
+			clocks = <&peri_clk 6>;
+			clock-frequency = <400000>;
+		};
 
-	usb1: usb@5a810100 {
-		compatible = "socionext,uniphier-ehci", "generic-ehci";
-		status = "disabled";
-		reg = <0x5a810100 0x100>;
-		interrupts = <0 81 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb1>;
-		clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
-		resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
-			 <&mio_rst 13>;
-	};
+		i2c3: i2c@58580000 {
+			compatible = "socionext,uniphier-i2c";
+			status = "disabled";
+			reg = <0x58580000 0x40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 44 1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c3>;
+			clocks = <&peri_clk 7>;
+			clock-frequency = <100000>;
+		};
 
-	usb2: usb@5a820100 {
-		compatible = "socionext,uniphier-ehci", "generic-ehci";
-		status = "disabled";
-		reg = <0x5a820100 0x100>;
-		interrupts = <0 82 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb2>;
-		clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
-		resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
-			 <&mio_rst 14>;
-	};
+		system_bus: system-bus@58c00000 {
+			compatible = "socionext,uniphier-system-bus";
+			status = "disabled";
+			reg = <0x58c00000 0x400>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_system_bus>;
+		};
 
-	aidet@61830000 {
-		compatible = "simple-mfd", "syscon";
-		reg = <0x61830000 0x200>;
-	};
-};
+		smpctrl@59800000 {
+			compatible = "socionext,uniphier-smpctrl";
+			reg = <0x59801000 0x400>;
+		};
 
-&refclk {
-	clock-frequency = <24576000>;
-};
+		mioctrl@59810000 {
+			compatible = "socionext,uniphier-ld4-mioctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59810000 0x800>;
 
-&serial0 {
-	clock-frequency = <36864000>;
-};
+			mio_clk: clock {
+				compatible = "socionext,uniphier-ld4-mio-clock";
+				#clock-cells = <1>;
+			};
 
-&serial1 {
-	clock-frequency = <36864000>;
-};
+			mio_rst: reset {
+				compatible = "socionext,uniphier-ld4-mio-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-&serial2 {
-	clock-frequency = <36864000>;
-};
+		perictrl@59820000 {
+			compatible = "socionext,uniphier-ld4-perictrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59820000 0x200>;
 
-&serial3 {
-	interrupts = <0 29 4>;
-	clock-frequency = <36864000>;
-};
+			peri_clk: clock {
+				compatible = "socionext,uniphier-ld4-peri-clock";
+				#clock-cells = <1>;
+			};
 
-&mio_clk {
-	compatible = "socionext,uniphier-ld4-mio-clock";
-};
+			peri_rst: reset {
+				compatible = "socionext,uniphier-ld4-peri-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-&mio_rst {
-	compatible = "socionext,uniphier-ld4-mio-reset";
-};
+		sd: sdhc@5a400000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a400000 0x200>;
+			interrupts = <0 76 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_sd>;
+			pinctrl-1 = <&pinctrl_sd_1v8>;
+			clocks = <&mio_clk 0>;
+			reset-names = "host", "bridge";
+			resets = <&mio_rst 0>, <&mio_rst 3>;
+			bus-width = <4>;
+			cap-sd-highspeed;
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+		};
 
-&peri_clk {
-	compatible = "socionext,uniphier-ld4-peri-clock";
-};
+		emmc: sdhc@5a500000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a500000 0x200>;
+			interrupts = <0 78 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_emmc>;
+			pinctrl-1 = <&pinctrl_emmc_1v8>;
+			clocks = <&mio_clk 1>;
+			reset-names = "host", "bridge";
+			resets = <&mio_rst 1>, <&mio_rst 4>;
+			bus-width = <8>;
+			non-removable;
+			cap-mmc-highspeed;
+			cap-mmc-hw-reset;
+		};
 
-&peri_rst {
-	compatible = "socionext,uniphier-ld4-peri-reset";
-};
+		usb0: usb@5a800100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a800100 0x100>;
+			interrupts = <0 80 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>;
+			clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+				 <&mio_rst 12>;
+		};
 
-&pinctrl {
-	compatible = "socionext,uniphier-ld4-pinctrl";
-};
+		usb1: usb@5a810100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a810100 0x100>;
+			interrupts = <0 81 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>;
+			clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+				 <&mio_rst 13>;
+		};
 
-&sys_clk {
-	compatible = "socionext,uniphier-ld4-clock";
-};
+		usb2: usb@5a820100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a820100 0x100>;
+			interrupts = <0 82 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb2>;
+			clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+				 <&mio_rst 14>;
+		};
+
+		soc-glue@5f800000 {
+			compatible = "socionext,uniphier-ld4-soc-glue",
+				     "simple-mfd", "syscon";
+			reg = <0x5f800000 0x2000>;
+			u-boot,dm-pre-reloc;
+
+			pinctrl: pinctrl {
+				compatible = "socionext,uniphier-ld4-pinctrl";
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		timer@60000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x60000200 0x20>;
+			interrupts = <1 11 0x104>;
+			clocks = <&arm_timer_clk>;
+		};
 
-&sys_rst {
-	compatible = "socionext,uniphier-ld4-reset";
+		timer@60000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x60000600 0x20>;
+			interrupts = <1 13 0x104>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		intc: interrupt-controller@60001000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0x60001000 0x1000>,
+			      <0x60000100 0x100>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+		};
+
+		aidet@61830000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x61830000 0x200>;
+		};
+
+		sysctrl@61840000 {
+			compatible = "socionext,uniphier-ld4-sysctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x61840000 0x10000>;
+
+			sys_clk: clock {
+				compatible = "socionext,uniphier-ld4-clock";
+				#clock-cells = <1>;
+			};
+
+			sys_rst: reset {
+				compatible = "socionext,uniphier-ld4-reset";
+				#reset-cells = <1>;
+			};
+		};
+
+		nand: nand@68000000 {
+			compatible = "socionext,denali-nand-v5a";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+			clocks = <&sys_clk 2>;
+			nand-ecc-strength = <8>;
+		};
+	};
 };
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-pro4-ref.dts b/arch/arm/dts/uniphier-pro4-ref.dts
index 2d49b3e831..9714fb0c30 100644
--- a/arch/arm/dts/uniphier-pro4-ref.dts
+++ b/arch/arm/dts/uniphier-pro4-ref.dts
@@ -68,15 +68,19 @@
 	status = "okay";
 };
 
-&usb0 {
+&usb2 {
 	status = "okay";
 };
 
-&usb2 {
+&usb3 {
 	status = "okay";
 };
 
-&usb3 {
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi
index aa80ea4801..9b881f6905 100644
--- a/arch/arm/dts/uniphier-pro4.dtsi
+++ b/arch/arm/dts/uniphier-pro4.dtsi
@@ -7,7 +7,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/include/ "uniphier-common32.dtsi"
+/include/ "skeleton.dtsi"
 
 / {
 	compatible = "socionext,uniphier-pro4";
@@ -33,452 +33,593 @@
 		};
 	};
 
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
 	clocks {
+		refclk: ref {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+
 		arm_timer_clk: arm_timer_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <50000000>;
 		};
+	};
 
-		uart_clk: uart_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		interrupt-parent = <&intc>;
+		u-boot,dm-pre-reloc;
+
+		l2: l2-cache@500c0000 {
+			compatible = "socionext,uniphier-system-cache";
+			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+			      <0x506c0000 0x400>;
+			interrupts = <0 174 4>, <0 175 4>;
+			cache-unified;
+			cache-size = <(768 * 1024)>;
+			cache-sets = <256>;
+			cache-line-size = <128>;
+			cache-level = <2>;
+		};
+
+		serial0: serial@54006800 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006800 0x40>;
+			interrupts = <0 33 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart0>;
+			clocks = <&peri_clk 0>;
 			clock-frequency = <73728000>;
 		};
 
-		i2c_clk: i2c_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <50000000>;
+		serial1: serial@54006900 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006900 0x40>;
+			interrupts = <0 35 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart1>;
+			clocks = <&peri_clk 1>;
+			clock-frequency = <73728000>;
 		};
-	};
-};
 
-&soc {
-	l2: l2-cache@500c0000 {
-		compatible = "socionext,uniphier-system-cache";
-		reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
-		interrupts = <0 174 4>, <0 175 4>;
-		cache-unified;
-		cache-size = <(768 * 1024)>;
-		cache-sets = <256>;
-		cache-line-size = <128>;
-		cache-level = <2>;
-	};
+		serial2: serial@54006a00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006a00 0x40>;
+			interrupts = <0 37 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart2>;
+			clocks = <&peri_clk 2>;
+			clock-frequency = <73728000>;
+		};
 
-	port0x: gpio@55000008 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000008 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial3: serial@54006b00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006b00 0x40>;
+			interrupts = <0 177 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart3>;
+			clocks = <&peri_clk 3>;
+			clock-frequency = <73728000>;
+		};
 
-	port1x: gpio@55000010 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000010 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port0x: gpio@55000008 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000008 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port2x: gpio@55000018 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000018 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port1x: gpio@55000010 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000010 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port3x: gpio@55000020 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000020 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port2x: gpio@55000018 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000018 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port4: gpio@55000028 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000028 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port3x: gpio@55000020 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000020 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port5x: gpio@55000030 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000030 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port4: gpio@55000028 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000028 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port6x: gpio@55000038 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000038 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port5x: gpio@55000030 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000030 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port7x: gpio@55000040 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000040 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port6x: gpio@55000038 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000038 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port8x: gpio@55000048 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000048 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port7x: gpio@55000040 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000040 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port9x: gpio@55000050 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000050 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port8x: gpio@55000048 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000048 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port10x: gpio@55000058 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000058 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port9x: gpio@55000050 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000050 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port11x: gpio@55000060 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000060 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port10x: gpio@55000058 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000058 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port12x: gpio@55000068 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000068 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port11x: gpio@55000060 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000060 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port13x: gpio@55000070 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000070 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port12x: gpio@55000068 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000068 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port14x: gpio@55000078 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000078 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port13x: gpio@55000070 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000070 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port17x: gpio@550000a0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000a0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port14x: gpio@55000078 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000078 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port18x: gpio@550000a8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000a8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port17x: gpio@550000a0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000a0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port19x: gpio@550000b0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000b0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port18x: gpio@550000a8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000a8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port20x: gpio@550000b8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000b8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port19x: gpio@550000b0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000b0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port21x: gpio@550000c0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000c0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port20x: gpio@550000b8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000b8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port22x: gpio@550000c8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000c8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port21x: gpio@550000c0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000c0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port23x: gpio@550000d0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000d0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port22x: gpio@550000c8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000c8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port24x: gpio@550000d8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000d8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port23x: gpio@550000d0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000d0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port25x: gpio@550000e0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000e0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port24x: gpio@550000d8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000d8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port26x: gpio@550000e8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000e8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port25x: gpio@550000e0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000e0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port27x: gpio@550000f0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000f0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port26x: gpio@550000e8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000e8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port28x: gpio@550000f8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000f8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port27x: gpio@550000f0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000f0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port29x: gpio@55000100 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000100 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port28x: gpio@550000f8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000f8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port30x: gpio@55000108 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000108 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port29x: gpio@55000100 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000100 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c0: i2c@58780000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58780000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 41 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c0>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		port30x: gpio@55000108 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000108 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c1: i2c@58781000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58781000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 42 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c1>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		i2c0: i2c@58780000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58780000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 41 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c0>;
+			clocks = <&peri_clk 4>;
+			clock-frequency = <100000>;
+		};
 
-	i2c2: i2c@58782000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58782000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 43 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c2>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		i2c1: i2c@58781000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58781000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 42 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c1>;
+			clocks = <&peri_clk 5>;
+			clock-frequency = <100000>;
+		};
 
-	i2c3: i2c@58783000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58783000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 44 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c3>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		i2c2: i2c@58782000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58782000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 43 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c2>;
+			clocks = <&peri_clk 6>;
+			clock-frequency = <100000>;
+		};
 
-	/* i2c4 does not exist */
+		i2c3: i2c@58783000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58783000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 44 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c3>;
+			clocks = <&peri_clk 7>;
+			clock-frequency = <100000>;
+		};
 
-	/* chip-internal connection for DMD */
-	i2c5: i2c@58785000 {
-		compatible = "socionext,uniphier-fi2c";
-		reg = <0x58785000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 25 4>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <400000>;
-	};
+		/* i2c4 does not exist */
+
+		/* chip-internal connection for DMD */
+		i2c5: i2c@58785000 {
+			compatible = "socionext,uniphier-fi2c";
+			reg = <0x58785000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 25 4>;
+			clocks = <&peri_clk 9>;
+			clock-frequency = <400000>;
+		};
 
-	/* chip-internal connection for HDMI */
-	i2c6: i2c@58786000 {
-		compatible = "socionext,uniphier-fi2c";
-		reg = <0x58786000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 26 4>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <400000>;
-	};
+		/* chip-internal connection for HDMI */
+		i2c6: i2c@58786000 {
+			compatible = "socionext,uniphier-fi2c";
+			reg = <0x58786000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 26 4>;
+			clocks = <&peri_clk 10>;
+			clock-frequency = <400000>;
+		};
 
-	sd: sdhc@5a400000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x5a400000 0x200>;
-		interrupts = <0 76 4>;
-		pinctrl-names = "default", "1.8v";
-		pinctrl-0 = <&pinctrl_sd>;
-		pinctrl-1 = <&pinctrl_sd_1v8>;
-		clocks = <&mio_clk 0>;
-		reset-names = "host", "bridge";
-		resets = <&mio_rst 0>, <&mio_rst 3>;
-		bus-width = <4>;
-	};
+		system_bus: system-bus@58c00000 {
+			compatible = "socionext,uniphier-system-bus";
+			status = "disabled";
+			reg = <0x58c00000 0x400>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_system_bus>;
+		};
 
-	emmc: sdhc@5a500000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x5a500000 0x200>;
-		interrupts = <0 78 4>;
-		pinctrl-names = "default", "1.8v";
-		pinctrl-0 = <&pinctrl_emmc>;
-		pinctrl-1 = <&pinctrl_emmc_1v8>;
-		clocks = <&mio_clk 1>;
-		reset-names = "host", "bridge", "hw-reset";
-		resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
-		bus-width = <8>;
-		non-removable;
-	};
+		smpctrl@59800000 {
+			compatible = "socionext,uniphier-smpctrl";
+			reg = <0x59801000 0x400>;
+		};
 
-	sd1: sdhc@5a600000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x5a600000 0x200>;
-		interrupts = <0 85 4>;
-		pinctrl-names = "default", "1.8v";
-		pinctrl-0 = <&pinctrl_sd1>;
-		pinctrl-1 = <&pinctrl_sd1_1v8>;
-		clocks = <&mio_clk 2>;
-		resets = <&mio_rst 2>, <&mio_rst 5>;
-		bus-width = <4>;
-	};
+		mioctrl@59810000 {
+			compatible = "socionext,uniphier-pro4-mioctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59810000 0x800>;
+			u-boot,dm-pre-reloc;
+
+			mio_clk: clock {
+				compatible = "socionext,uniphier-pro4-mio-clock";
+				#clock-cells = <1>;
+			};
+
+			mio_rst: reset {
+				compatible = "socionext,uniphier-pro4-mio-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-	usb2: usb@5a800100 {
-		compatible = "socionext,uniphier-ehci", "generic-ehci";
-		status = "disabled";
-		reg = <0x5a800100 0x100>;
-		interrupts = <0 80 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb2>;
-		clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
-		resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
-			 <&mio_rst 12>;
-	};
+		perictrl@59820000 {
+			compatible = "socionext,uniphier-pro4-perictrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59820000 0x200>;
 
-	usb3: usb@5a810100 {
-		compatible = "socionext,uniphier-ehci", "generic-ehci";
-		status = "disabled";
-		reg = <0x5a810100 0x100>;
-		interrupts = <0 81 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb3>;
-		clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
-		resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
-			 <&mio_rst 13>;
-	};
+			peri_clk: clock {
+				compatible = "socionext,uniphier-pro4-peri-clock";
+				#clock-cells = <1>;
+			};
 
-	aidet@5fc20000 {
-		compatible = "simple-mfd", "syscon";
-		reg = <0x5fc20000 0x200>;
-	};
+			peri_rst: reset {
+				compatible = "socionext,uniphier-pro4-peri-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-	usb0: usb@65a00000 {
-		compatible = "socionext,uniphier-xhci", "generic-xhci";
-		status = "disabled";
-		reg = <0x65a00000 0x100>;
-		interrupts = <0 134 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb0>;
-	};
+		sd: sdhc@5a400000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a400000 0x200>;
+			interrupts = <0 76 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_sd>;
+			pinctrl-1 = <&pinctrl_sd_1v8>;
+			clocks = <&mio_clk 0>;
+			reset-names = "host", "bridge";
+			resets = <&mio_rst 0>, <&mio_rst 3>;
+			bus-width = <4>;
+			cap-sd-highspeed;
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+		};
 
-	usb1: usb@65c00000 {
-		compatible = "socionext,uniphier-xhci", "generic-xhci";
-		status = "disabled";
-		reg = <0x65c00000 0x100>;
-		interrupts = <0 137 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb1>;
-	};
-};
+		emmc: sdhc@5a500000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a500000 0x200>;
+			interrupts = <0 78 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_emmc>;
+			pinctrl-1 = <&pinctrl_emmc_1v8>;
+			clocks = <&mio_clk 1>;
+			reset-names = "host", "bridge";
+			resets = <&mio_rst 1>, <&mio_rst 4>;
+			bus-width = <8>;
+			non-removable;
+			cap-mmc-highspeed;
+			cap-mmc-hw-reset;
+		};
 
-&refclk {
-	clock-frequency = <25000000>;
-};
+		sd1: sdhc@5a600000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a600000 0x200>;
+			interrupts = <0 85 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_sd1>;
+			pinctrl-1 = <&pinctrl_sd1_1v8>;
+			clocks = <&mio_clk 2>;
+			resets = <&mio_rst 2>, <&mio_rst 5>;
+			bus-width = <4>;
+			cap-sd-highspeed;
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+		};
 
-&serial0 {
-	clock-frequency = <73728000>;
-};
+		usb2: usb@5a800100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a800100 0x100>;
+			interrupts = <0 80 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb2>;
+			clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+				 <&mio_rst 12>;
+		};
 
-&serial1 {
-	clock-frequency = <73728000>;
-};
+		usb3: usb@5a810100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a810100 0x100>;
+			interrupts = <0 81 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb3>;
+			clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+				 <&mio_rst 13>;
+		};
 
-&serial2 {
-	clock-frequency = <73728000>;
-};
+		soc-glue@5f800000 {
+			compatible = "socionext,uniphier-pro4-soc-glue",
+				     "simple-mfd", "syscon";
+			reg = <0x5f800000 0x2000>;
+			u-boot,dm-pre-reloc;
 
-&serial3 {
-	clock-frequency = <73728000>;
-};
+			pinctrl: pinctrl {
+				compatible = "socionext,uniphier-pro4-pinctrl";
+				u-boot,dm-pre-reloc;
+			};
+		};
 
-&mio_clk {
-	compatible = "socionext,uniphier-pro4-mio-clock";
-};
+		aidet@5fc20000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x5fc20000 0x200>;
+		};
 
-&mio_rst {
-	compatible = "socionext,uniphier-pro4-mio-reset";
-};
+		timer@60000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x60000200 0x20>;
+			interrupts = <1 11 0x304>;
+			clocks = <&arm_timer_clk>;
+		};
 
-&peri_clk {
-	compatible = "socionext,uniphier-pro4-peri-clock";
-};
+		timer@60000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x60000600 0x20>;
+			interrupts = <1 13 0x304>;
+			clocks = <&arm_timer_clk>;
+		};
 
-&peri_rst {
-	compatible = "socionext,uniphier-pro4-peri-reset";
-};
+		intc: interrupt-controller@60001000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0x60001000 0x1000>,
+			      <0x60000100 0x100>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+		};
 
-&pinctrl {
-	compatible = "socionext,uniphier-pro4-pinctrl";
-};
+		sysctrl@61840000 {
+			compatible = "socionext,uniphier-pro4-sysctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x61840000 0x10000>;
 
-&sys_clk {
-	compatible = "socionext,uniphier-pro4-clock";
-};
+			sys_clk: clock {
+				compatible = "socionext,uniphier-pro4-clock";
+				#clock-cells = <1>;
+			};
 
-&sys_rst {
-	compatible = "socionext,uniphier-pro4-reset";
+			sys_rst: reset {
+				compatible = "socionext,uniphier-pro4-reset";
+				#reset-cells = <1>;
+			};
+		};
+
+		usb0: usb@65b00000 {
+			compatible = "socionext,uniphier-pro4-dwc3";
+			status = "disabled";
+			reg = <0x65b00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>;
+			dwc3@65a00000 {
+				compatible = "snps,dwc3";
+				reg = <0x65a00000 0x10000>;
+				interrupts = <0 134 4>;
+				tx-fifo-resize;
+			};
+		};
+
+		usb1: usb@65d00000 {
+			compatible = "socionext,uniphier-pro4-dwc3";
+			status = "disabled";
+			reg = <0x65d00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>;
+			dwc3@65c00000 {
+				compatible = "snps,dwc3";
+				reg = <0x65c00000 0x10000>;
+				interrupts = <0 137 4>;
+				tx-fifo-resize;
+			};
+		};
+
+		nand: nand@68000000 {
+			compatible = "socionext,denali-nand-v5a";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+			clocks = <&sys_clk 2>;
+			nand-ecc-strength = <8>;
+		};
+	};
 };
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi
index 97edc89a9c..68866e16df 100644
--- a/arch/arm/dts/uniphier-pro5.dtsi
+++ b/arch/arm/dts/uniphier-pro5.dtsi
@@ -7,7 +7,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/include/ "uniphier-common32.dtsi"
+/include/ "skeleton.dtsi"
 
 / {
 	compatible = "socionext,uniphier-pro5";
@@ -20,433 +20,652 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0>;
+			clocks = <&sys_clk 32>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			operating-points-v2 = <&cpu_opp>;
 		};
 
 		cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <1>;
+			clocks = <&sys_clk 32>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			operating-points-v2 = <&cpu_opp>;
 		};
 	};
 
+	cpu_opp: opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@116667000 {
+			opp-hz = /bits/ 64 <116667000>;
+			clock-latency-ns = <300>;
+		};
+		opp@150000000 {
+			opp-hz = /bits/ 64 <150000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@175000000 {
+			opp-hz = /bits/ 64 <175000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@233334000 {
+			opp-hz = /bits/ 64 <233334000>;
+			clock-latency-ns = <300>;
+		};
+		opp@300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@350000000 {
+			opp-hz = /bits/ 64 <350000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@466667000 {
+			opp-hz = /bits/ 64 <466667000>;
+			clock-latency-ns = <300>;
+		};
+		opp@600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@700000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@933334000 {
+			opp-hz = /bits/ 64 <933334000>;
+			clock-latency-ns = <300>;
+		};
+		opp@1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@1400000000 {
+			opp-hz = /bits/ 64 <1400000000>;
+			clock-latency-ns = <300>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
 	clocks {
-		arm_timer_clk: arm_timer_clk {
-			#clock-cells = <0>;
+		refclk: ref {
 			compatible = "fixed-clock";
-			clock-frequency = <50000000>;
+			#clock-cells = <0>;
+			clock-frequency = <20000000>;
 		};
 
-		i2c_clk: i2c_clk {
+		arm_timer_clk: arm_timer_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <50000000>;
 		};
 	};
-};
 
-&soc {
-	l2: l2-cache@500c0000 {
-		compatible = "socionext,uniphier-system-cache";
-		reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
-		interrupts = <0 190 4>, <0 191 4>;
-		cache-unified;
-		cache-size = <(2 * 1024 * 1024)>;
-		cache-sets = <512>;
-		cache-line-size = <128>;
-		cache-level = <2>;
-		next-level-cache = <&l3>;
-	};
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		interrupt-parent = <&intc>;
+		u-boot,dm-pre-reloc;
+
+		l2: l2-cache@500c0000 {
+			compatible = "socionext,uniphier-system-cache";
+			reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
+			      <0x506c0000 0x400>;
+			interrupts = <0 190 4>, <0 191 4>;
+			cache-unified;
+			cache-size = <(2 * 1024 * 1024)>;
+			cache-sets = <512>;
+			cache-line-size = <128>;
+			cache-level = <2>;
+			next-level-cache = <&l3>;
+		};
 
-	l3: l3-cache@500c8000 {
-		compatible = "socionext,uniphier-system-cache";
-		reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
-		interrupts = <0 174 4>, <0 175 4>;
-		cache-unified;
-		cache-size = <(2 * 1024 * 1024)>;
-		cache-sets = <512>;
-		cache-line-size = <256>;
-		cache-level = <3>;
-	};
+		l3: l3-cache@500c8000 {
+			compatible = "socionext,uniphier-system-cache";
+			reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
+			      <0x506c8000 0x400>;
+			interrupts = <0 174 4>, <0 175 4>;
+			cache-unified;
+			cache-size = <(2 * 1024 * 1024)>;
+			cache-sets = <512>;
+			cache-line-size = <256>;
+			cache-level = <3>;
+		};
 
-	port0x: gpio@55000008 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000008 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial0: serial@54006800 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006800 0x40>;
+			interrupts = <0 33 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart0>;
+			clocks = <&peri_clk 0>;
+			clock-frequency = <73728000>;
+		};
 
-	port1x: gpio@55000010 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000010 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial1: serial@54006900 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006900 0x40>;
+			interrupts = <0 35 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart1>;
+			clocks = <&peri_clk 1>;
+			clock-frequency = <73728000>;
+		};
 
-	port2x: gpio@55000018 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000018 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial2: serial@54006a00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006a00 0x40>;
+			interrupts = <0 37 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart2>;
+			clocks = <&peri_clk 2>;
+			clock-frequency = <73728000>;
+		};
 
-	port3x: gpio@55000020 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000020 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial3: serial@54006b00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006b00 0x40>;
+			interrupts = <0 177 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart3>;
+			clocks = <&peri_clk 3>;
+			clock-frequency = <73728000>;
+		};
 
-	port4: gpio@55000028 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000028 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port0x: gpio@55000008 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000008 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port5x: gpio@55000030 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000030 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port1x: gpio@55000010 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000010 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port6x: gpio@55000038 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000038 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port2x: gpio@55000018 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000018 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port7x: gpio@55000040 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000040 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port3x: gpio@55000020 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000020 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port8x: gpio@55000048 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000048 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port4: gpio@55000028 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000028 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port9x: gpio@55000050 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000050 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port5x: gpio@55000030 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000030 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port10x: gpio@55000058 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000058 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port6x: gpio@55000038 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000038 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port11x: gpio@55000060 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000060 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port7x: gpio@55000040 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000040 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port12x: gpio@55000068 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000068 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port8x: gpio@55000048 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000048 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port13x: gpio@55000070 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000070 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port9x: gpio@55000050 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000050 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port14x: gpio@55000078 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000078 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port10x: gpio@55000058 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000058 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port17x: gpio@550000a0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000a0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port11x: gpio@55000060 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000060 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port18x: gpio@550000a8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000a8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port12x: gpio@55000068 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000068 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port19x: gpio@550000b0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000b0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port13x: gpio@55000070 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000070 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port20x: gpio@550000b8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000b8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port14x: gpio@55000078 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000078 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port21x: gpio@550000c0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000c0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port17x: gpio@550000a0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000a0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port22x: gpio@550000c8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000c8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port18x: gpio@550000a8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000a8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port23x: gpio@550000d0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000d0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port19x: gpio@550000b0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000b0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port24x: gpio@550000d8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000d8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port20x: gpio@550000b8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000b8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port25x: gpio@550000e0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000e0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port21x: gpio@550000c0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000c0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port26x: gpio@550000e8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000e8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port22x: gpio@550000c8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000c8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port27x: gpio@550000f0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000f0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port23x: gpio@550000d0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000d0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port28x: gpio@550000f8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000f8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port24x: gpio@550000d8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000d8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port29x: gpio@55000100 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000100 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port25x: gpio@550000e0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000e0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port30x: gpio@55000108 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000108 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port26x: gpio@550000e8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000e8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c0: i2c@58780000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58780000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 41 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c0>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		port27x: gpio@550000f0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000f0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c1: i2c@58781000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58781000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 42 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c1>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		port28x: gpio@550000f8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000f8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c2: i2c@58782000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58782000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 43 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c2>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		port29x: gpio@55000100 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000100 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c3: i2c@58783000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58783000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 44 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c3>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		port30x: gpio@55000108 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000108 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	/* i2c4 does not exist */
+		i2c0: i2c@58780000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58780000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 41 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c0>;
+			clocks = <&peri_clk 4>;
+			clock-frequency = <100000>;
+		};
 
-	/* chip-internal connection for DMD */
-	i2c5: i2c@58785000 {
-		compatible = "socionext,uniphier-fi2c";
-		reg = <0x58785000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 25 4>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <400000>;
-	};
+		i2c1: i2c@58781000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58781000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 42 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c1>;
+			clocks = <&peri_clk 5>;
+			clock-frequency = <100000>;
+		};
 
-	/* chip-internal connection for HDMI */
-	i2c6: i2c@58786000 {
-		compatible = "socionext,uniphier-fi2c";
-		reg = <0x58786000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 26 4>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <400000>;
-	};
+		i2c2: i2c@58782000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58782000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 43 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c2>;
+			clocks = <&peri_clk 6>;
+			clock-frequency = <100000>;
+		};
 
-	aidet@5fc20000 {
-		compatible = "simple-mfd", "syscon";
-		reg = <0x5fc20000 0x200>;
-	};
+		i2c3: i2c@58783000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58783000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 44 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c3>;
+			clocks = <&peri_clk 7>;
+			clock-frequency = <100000>;
+		};
 
-	emmc: sdhc@68400000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x68400000 0x800>;
-		interrupts = <0 78 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_emmc>;
-		clocks = <&mio_clk 1>;
-		reset-names = "host", "hw-reset";
-		resets = <&mio_rst 1>, <&mio_rst 6>;
-		bus-width = <8>;
-		non-removable;
-	};
+		/* i2c4 does not exist */
+
+		/* chip-internal connection for DMD */
+		i2c5: i2c@58785000 {
+			compatible = "socionext,uniphier-fi2c";
+			reg = <0x58785000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 25 4>;
+			clocks = <&peri_clk 9>;
+			clock-frequency = <400000>;
+		};
 
-	sd: sdhc@68800000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x68800000 0x800>;
-		interrupts = <0 76 4>;
-		pinctrl-names = "default", "1.8v";
-		pinctrl-0 = <&pinctrl_sd>;
-		pinctrl-1 = <&pinctrl_sd_1v8>;
-		clocks = <&mio_clk 0>;
-		reset-names = "host";
-		resets = <&mio_rst 0>;
-		bus-width = <4>;
-	};
+		/* chip-internal connection for HDMI */
+		i2c6: i2c@58786000 {
+			compatible = "socionext,uniphier-fi2c";
+			reg = <0x58786000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 26 4>;
+			clocks = <&peri_clk 10>;
+			clock-frequency = <400000>;
+		};
 
-	usb0: usb@65a00000 {
-		compatible = "socionext,uniphier-xhci", "generic-xhci";
-		status = "disabled";
-		reg = <0x65a00000 0x100>;
-		interrupts = <0 134 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb0>;
-	};
+		system_bus: system-bus@58c00000 {
+			compatible = "socionext,uniphier-system-bus";
+			status = "disabled";
+			reg = <0x58c00000 0x400>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_system_bus>;
+		};
 
-	usb1: usb@65c00000 {
-		compatible = "socionext,uniphier-xhci", "generic-xhci";
-		status = "disabled";
-		reg = <0x65c00000 0x100>;
-		interrupts = <0 137 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
-	};
-};
+		smpctrl@59800000 {
+			compatible = "socionext,uniphier-smpctrl";
+			reg = <0x59801000 0x400>;
+		};
 
-&refclk {
-	clock-frequency = <20000000>;
-};
+		sdctrl@59810000 {
+			compatible = "socionext,uniphier-pro5-sdctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59810000 0x800>;
+			u-boot,dm-pre-reloc;
+
+			sd_clk: clock {
+				compatible = "socionext,uniphier-pro5-sd-clock";
+				#clock-cells = <1>;
+			};
+
+			sd_rst: reset {
+				compatible = "socionext,uniphier-pro5-sd-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-&serial0 {
-	clock-frequency = <73728000>;
-};
+		perictrl@59820000 {
+			compatible = "socionext,uniphier-pro5-perictrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59820000 0x200>;
 
-&serial1 {
-	clock-frequency = <73728000>;
-};
+			peri_clk: clock {
+				compatible = "socionext,uniphier-pro5-peri-clock";
+				#clock-cells = <1>;
+			};
 
-&serial2 {
-	clock-frequency = <73728000>;
-};
+			peri_rst: reset {
+				compatible = "socionext,uniphier-pro5-peri-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-&serial3 {
-	clock-frequency = <73728000>;
-};
+		soc-glue@5f800000 {
+			compatible = "socionext,uniphier-pro5-soc-glue",
+				     "simple-mfd", "syscon";
+			reg = <0x5f800000 0x2000>;
+			u-boot,dm-pre-reloc;
 
-&mio_clk {
-	compatible = "socionext,uniphier-pro5-mio-clock";
-};
+			pinctrl: pinctrl {
+				compatible = "socionext,uniphier-pro5-pinctrl";
+				u-boot,dm-pre-reloc;
+			};
+		};
 
-&mio_rst {
-	compatible = "socionext,uniphier-pro5-mio-reset";
-};
+		aidet@5fc20000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x5fc20000 0x200>;
+		};
 
-&peri_clk {
-	compatible = "socionext,uniphier-pro5-peri-clock";
-};
+		timer@60000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x60000200 0x20>;
+			interrupts = <1 11 0x304>;
+			clocks = <&arm_timer_clk>;
+		};
 
-&peri_rst {
-	compatible = "socionext,uniphier-pro5-peri-reset";
-};
+		timer@60000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x60000600 0x20>;
+			interrupts = <1 13 0x304>;
+			clocks = <&arm_timer_clk>;
+		};
 
-&pinctrl {
-	compatible = "socionext,uniphier-pro5-pinctrl";
-};
+		intc: interrupt-controller@60001000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0x60001000 0x1000>,
+			      <0x60000100 0x100>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+		};
 
-&sys_clk {
-	compatible = "socionext,uniphier-pro5-clock";
-};
+		sysctrl@61840000 {
+			compatible = "socionext,uniphier-pro5-sysctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x61840000 0x10000>;
+
+			sys_clk: clock {
+				compatible = "socionext,uniphier-pro5-clock";
+				#clock-cells = <1>;
+			};
+
+			sys_rst: reset {
+				compatible = "socionext,uniphier-pro5-reset";
+				#reset-cells = <1>;
+			};
+		};
+
+		usb0: usb@65b00000 {
+			compatible = "socionext,uniphier-pro5-dwc3";
+			status = "disabled";
+			reg = <0x65b00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>;
+			dwc3@65a00000 {
+				compatible = "snps,dwc3";
+				reg = <0x65a00000 0x10000>;
+				interrupts = <0 134 4>;
+				tx-fifo-resize;
+			};
+		};
 
-&sys_rst {
-	compatible = "socionext,uniphier-pro5-reset";
+		usb1: usb@65d00000 {
+			compatible = "socionext,uniphier-pro5-dwc3";
+			status = "disabled";
+			reg = <0x65d00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
+			dwc3@65c00000 {
+				compatible = "snps,dwc3";
+				reg = <0x65c00000 0x10000>;
+				interrupts = <0 137 4>;
+				tx-fifo-resize;
+			};
+		};
+
+		nand: nand@68000000 {
+			compatible = "socionext,denali-nand-v5b";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+			clocks = <&sys_clk 2>;
+			nand-ecc-strength = <8>;
+		};
+
+		emmc: sdhc@68400000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x68400000 0x800>;
+			interrupts = <0 78 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_emmc>;
+			clocks = <&sd_clk 1>;
+			reset-names = "host";
+			resets = <&sd_rst 1>;
+			bus-width = <8>;
+			non-removable;
+			cap-mmc-highspeed;
+			cap-mmc-hw-reset;
+			no-3-3-v;
+		};
+
+		sd: sdhc@68800000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x68800000 0x800>;
+			interrupts = <0 76 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_sd>;
+			pinctrl-1 = <&pinctrl_sd_1v8>;
+			clocks = <&sd_clk 0>;
+			reset-names = "host";
+			resets = <&sd_rst 0>;
+			bus-width = <4>;
+			cap-sd-highspeed;
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+		};
+	};
 };
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-pxs2-gentil.dts b/arch/arm/dts/uniphier-pxs2-gentil.dts
index a98e758f03..0a6d46cb14 100644
--- a/arch/arm/dts/uniphier-pxs2-gentil.dts
+++ b/arch/arm/dts/uniphier-pxs2-gentil.dts
@@ -71,7 +71,7 @@
 	u-boot,dm-pre-reloc;
 };
 
-&mio_clk {
+&sd_clk {
 	u-boot,dm-pre-reloc;
 };
 
diff --git a/arch/arm/dts/uniphier-pxs2-vodka.dts b/arch/arm/dts/uniphier-pxs2-vodka.dts
index 78a52a8f18..770edca6ce 100644
--- a/arch/arm/dts/uniphier-pxs2-vodka.dts
+++ b/arch/arm/dts/uniphier-pxs2-vodka.dts
@@ -55,7 +55,7 @@
 	u-boot,dm-pre-reloc;
 };
 
-&mio_clk {
+&sd_clk {
 	u-boot,dm-pre-reloc;
 };
 
diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi
index b64107b3dd..da62070b74 100644
--- a/arch/arm/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/dts/uniphier-pxs2.dtsi
@@ -7,7 +7,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/include/ "uniphier-common32.dtsi"
+/include/ "skeleton.dtsi"
 
 / {
 	compatible = "socionext,uniphier-pxs2";
@@ -20,36 +20,93 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0>;
+			clocks = <&sys_clk 32>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			operating-points-v2 = <&cpu_opp>;
 		};
 
 		cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <1>;
+			clocks = <&sys_clk 32>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			operating-points-v2 = <&cpu_opp>;
 		};
 
 		cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <2>;
+			clocks = <&sys_clk 32>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			operating-points-v2 = <&cpu_opp>;
 		};
 
 		cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <3>;
+			clocks = <&sys_clk 32>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			operating-points-v2 = <&cpu_opp>;
 		};
 	};
 
+	cpu_opp: opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@150000000 {
+			opp-hz = /bits/ 64 <150000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			clock-latency-ns = <300>;
+		};
+		opp@1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			clock-latency-ns = <300>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
 	clocks {
+		refclk: ref {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+
 		arm_timer_clk: arm_timer_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -62,397 +119,536 @@
 			clock-frequency = <50000000>;
 		};
 	};
-};
 
-&soc {
-	l2: l2-cache@500c0000 {
-		compatible = "socionext,uniphier-system-cache";
-		reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
-		interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
-		cache-unified;
-		cache-size = <(1280 * 1024)>;
-		cache-sets = <512>;
-		cache-line-size = <128>;
-		cache-level = <2>;
-	};
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		interrupt-parent = <&intc>;
+		u-boot,dm-pre-reloc;
+
+		l2: l2-cache@500c0000 {
+			compatible = "socionext,uniphier-system-cache";
+			reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
+			      <0x506c0000 0x400>;
+			interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
+			cache-unified;
+			cache-size = <(1280 * 1024)>;
+			cache-sets = <512>;
+			cache-line-size = <128>;
+			cache-level = <2>;
+		};
 
-	port0x: gpio@55000008 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000008 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial0: serial@54006800 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006800 0x40>;
+			interrupts = <0 33 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart0>;
+			clocks = <&peri_clk 0>;
+			clock-frequency = <88900000>;
+		};
 
-	port1x: gpio@55000010 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000010 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial1: serial@54006900 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006900 0x40>;
+			interrupts = <0 35 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart1>;
+			clocks = <&peri_clk 1>;
+			clock-frequency = <88900000>;
+		};
 
-	port2x: gpio@55000018 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000018 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial2: serial@54006a00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006a00 0x40>;
+			interrupts = <0 37 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart2>;
+			clocks = <&peri_clk 2>;
+			clock-frequency = <88900000>;
+		};
 
-	port3x: gpio@55000020 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000020 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial3: serial@54006b00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006b00 0x40>;
+			interrupts = <0 177 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart3>;
+			clocks = <&peri_clk 3>;
+			clock-frequency = <88900000>;
+		};
 
-	port4: gpio@55000028 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000028 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port0x: gpio@55000008 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000008 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port5x: gpio@55000030 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000030 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port1x: gpio@55000010 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000010 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port6x: gpio@55000038 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000038 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port2x: gpio@55000018 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000018 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port7x: gpio@55000040 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000040 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port3x: gpio@55000020 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000020 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port8x: gpio@55000048 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000048 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port4: gpio@55000028 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000028 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port9x: gpio@55000050 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000050 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port5x: gpio@55000030 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000030 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port10x: gpio@55000058 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000058 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port6x: gpio@55000038 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000038 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port12x: gpio@55000068 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000068 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port7x: gpio@55000040 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000040 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port13x: gpio@55000070 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000070 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port8x: gpio@55000048 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000048 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port14x: gpio@55000078 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000078 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port9x: gpio@55000050 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000050 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port15x: gpio@55000080 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000080 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port10x: gpio@55000058 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000058 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port16x: gpio@55000088 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000088 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port12x: gpio@55000068 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000068 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port17x: gpio@550000a0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000a0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port13x: gpio@55000070 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000070 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port18x: gpio@550000a8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000a8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port14x: gpio@55000078 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000078 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port19x: gpio@550000b0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000b0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port15x: gpio@55000080 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000080 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port20x: gpio@550000b8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000b8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port16x: gpio@55000088 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000088 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port21x: gpio@550000c0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000c0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port17x: gpio@550000a0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000a0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port22x: gpio@550000c8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000c8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port18x: gpio@550000a8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000a8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port23x: gpio@550000d0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000d0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port19x: gpio@550000b0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000b0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port24x: gpio@550000d8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000d8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port20x: gpio@550000b8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000b8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port25x: gpio@550000e0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000e0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port21x: gpio@550000c0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000c0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port26x: gpio@550000e8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000e8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port22x: gpio@550000c8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000c8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port27x: gpio@550000f0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000f0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port23x: gpio@550000d0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000d0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port28x: gpio@550000f8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000f8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port24x: gpio@550000d8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000d8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c0: i2c@58780000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58780000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 41 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c0>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		port25x: gpio@550000e0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000e0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c1: i2c@58781000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58781000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 42 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c1>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		port26x: gpio@550000e8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000e8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c2: i2c@58782000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58782000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c2>;
-		interrupts = <0 43 4>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		port27x: gpio@550000f0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000f0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c3: i2c@58783000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58783000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 44 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c3>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		port28x: gpio@550000f8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000f8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	/* chip-internal connection for DMD */
-	i2c4: i2c@58784000 {
-		compatible = "socionext,uniphier-fi2c";
-		reg = <0x58784000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 45 4>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <400000>;
-	};
+		i2c0: i2c@58780000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58780000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 41 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c0>;
+			clocks = <&i2c_clk>;
+			clock-frequency = <100000>;
+		};
 
-	/* chip-internal connection for STM */
-	i2c5: i2c@58785000 {
-		compatible = "socionext,uniphier-fi2c";
-		reg = <0x58785000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 25 4>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <400000>;
-	};
+		i2c1: i2c@58781000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58781000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 42 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c1>;
+			clocks = <&i2c_clk>;
+			clock-frequency = <100000>;
+		};
 
-	/* chip-internal connection for HDMI */
-	i2c6: i2c@58786000 {
-		compatible = "socionext,uniphier-fi2c";
-		reg = <0x58786000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 26 4>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <400000>;
-	};
+		i2c2: i2c@58782000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58782000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 43 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c2>;
+			clocks = <&i2c_clk>;
+			clock-frequency = <100000>;
+		};
 
-	emmc: sdhc@5a000000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x5a000000 0x800>;
-		interrupts = <0 78 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_emmc>;
-		clocks = <&mio_clk 1>;
-		reset-names = "host", "hw-reset";
-		resets = <&mio_rst 1>, <&mio_rst 6>;
-		bus-width = <8>;
-		non-removable;
-	};
+		i2c3: i2c@58783000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58783000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 44 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c3>;
+			clocks = <&i2c_clk>;
+			clock-frequency = <100000>;
+		};
 
-	sd: sdhc@5a400000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x5a400000 0x800>;
-		interrupts = <0 76 4>;
-		pinctrl-names = "default", "1.8v";
-		pinctrl-0 = <&pinctrl_sd>;
-		pinctrl-1 = <&pinctrl_sd_1v8>;
-		clocks = <&mio_clk 0>;
-		reset-names = "host";
-		resets = <&mio_rst 0>;
-		bus-width = <4>;
-	};
+		/* chip-internal connection for DMD */
+		i2c4: i2c@58784000 {
+			compatible = "socionext,uniphier-fi2c";
+			reg = <0x58784000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 45 4>;
+			clocks = <&i2c_clk>;
+			clock-frequency = <400000>;
+		};
 
-	aidet@5fc20000 {
-		compatible = "simple-mfd", "syscon";
-		reg = <0x5fc20000 0x200>;
-	};
+		/* chip-internal connection for STM */
+		i2c5: i2c@58785000 {
+			compatible = "socionext,uniphier-fi2c";
+			reg = <0x58785000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 25 4>;
+			clocks = <&i2c_clk>;
+			clock-frequency = <400000>;
+		};
 
-	usb0: usb@65a00000 {
-		compatible = "socionext,uniphier-xhci", "generic-xhci";
-		status = "disabled";
-		reg = <0x65a00000 0x100>;
-		interrupts = <0 134 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
-	};
+		/* chip-internal connection for HDMI */
+		i2c6: i2c@58786000 {
+			compatible = "socionext,uniphier-fi2c";
+			reg = <0x58786000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 26 4>;
+			clocks = <&i2c_clk>;
+			clock-frequency = <400000>;
+		};
 
-	usb1: usb@65c00000 {
-		compatible = "socionext,uniphier-xhci", "generic-xhci";
-		status = "disabled";
-		reg = <0x65c00000 0x100>;
-		interrupts = <0 137 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
-	};
-};
+		system_bus: system-bus@58c00000 {
+			compatible = "socionext,uniphier-system-bus";
+			status = "disabled";
+			reg = <0x58c00000 0x400>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_system_bus>;
+		};
 
-&refclk {
-	clock-frequency = <25000000>;
-};
+		smpctrl@59800000 {
+			compatible = "socionext,uniphier-smpctrl";
+			reg = <0x59801000 0x400>;
+		};
 
-&serial0 {
-	clock-frequency = <88900000>;
-};
+		sdctrl@59810000 {
+			compatible = "socionext,uniphier-pxs2-sdctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59810000 0x800>;
+			u-boot,dm-pre-reloc;
+
+			sd_clk: clock {
+				compatible = "socionext,uniphier-pxs2-sd-clock";
+				#clock-cells = <1>;
+			};
+
+			sd_rst: reset {
+				compatible = "socionext,uniphier-pxs2-sd-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-&serial1 {
-	clock-frequency = <88900000>;
-};
+		perictrl@59820000 {
+			compatible = "socionext,uniphier-pxs2-perictrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59820000 0x200>;
 
-&serial2 {
-	clock-frequency = <88900000>;
-};
+			peri_clk: clock {
+				compatible = "socionext,uniphier-pxs2-peri-clock";
+				#clock-cells = <1>;
+			};
 
-&serial3 {
-	clock-frequency = <88900000>;
-};
+			peri_rst: reset {
+				compatible = "socionext,uniphier-pxs2-peri-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-&mio_clk {
-	compatible = "socionext,uniphier-pxs2-mio-clock";
-};
+		emmc: sdhc@5a000000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a000000 0x800>;
+			interrupts = <0 78 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_emmc>;
+			clocks = <&sd_clk 1>;
+			reset-names = "host";
+			resets = <&sd_rst 1>;
+			bus-width = <8>;
+			non-removable;
+			cap-mmc-highspeed;
+			cap-mmc-hw-reset;
+			no-3-3-v;
+		};
 
-&mio_rst {
-	compatible = "socionext,uniphier-pxs2-mio-reset";
-};
+		sd: sdhc@5a400000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a400000 0x800>;
+			interrupts = <0 76 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_sd>;
+			pinctrl-1 = <&pinctrl_sd_1v8>;
+			clocks = <&sd_clk 0>;
+			reset-names = "host";
+			resets = <&sd_rst 0>;
+			bus-width = <4>;
+			cap-sd-highspeed;
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+		};
 
-&peri_clk {
-	compatible = "socionext,uniphier-pxs2-peri-clock";
-};
+		soc-glue@5f800000 {
+			compatible = "socionext,uniphier-pxs2-soc-glue",
+				     "simple-mfd", "syscon";
+			reg = <0x5f800000 0x2000>;
+			u-boot,dm-pre-reloc;
 
-&peri_rst {
-	compatible = "socionext,uniphier-pxs2-peri-reset";
-};
+			pinctrl: pinctrl {
+				compatible = "socionext,uniphier-pxs2-pinctrl";
+				u-boot,dm-pre-reloc;
+			};
+		};
 
-&pinctrl {
-	compatible = "socionext,uniphier-pxs2-pinctrl";
-};
+		aidet@5fc20000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x5fc20000 0x200>;
+		};
 
-&sys_clk {
-	compatible = "socionext,uniphier-pxs2-clock";
-};
+		timer@60000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x60000200 0x20>;
+			interrupts = <1 11 0xf04>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		timer@60000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x60000600 0x20>;
+			interrupts = <1 13 0xf04>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		intc: interrupt-controller@60001000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0x60001000 0x1000>,
+			      <0x60000100 0x100>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+		};
+
+		sysctrl@61840000 {
+			compatible = "socionext,uniphier-pxs2-sysctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x61840000 0x4000>;
+
+			sys_clk: clock {
+				compatible = "socionext,uniphier-pxs2-clock";
+				#clock-cells = <1>;
+			};
 
-&sys_rst {
-	compatible = "socionext,uniphier-pxs2-reset";
+			sys_rst: reset {
+				compatible = "socionext,uniphier-pxs2-reset";
+				#reset-cells = <1>;
+			};
+		};
+
+		usb0: usb@65b00000 {
+			compatible = "socionext,uniphier-pxs2-dwc3";
+			status = "disabled";
+			reg = <0x65b00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
+			dwc3@65a00000 {
+				compatible = "snps,dwc3";
+				reg = <0x65a00000 0x10000>;
+				interrupts = <0 134 4>;
+				tx-fifo-resize;
+			};
+		};
+
+		usb1: usb@65d00000 {
+			compatible = "socionext,uniphier-pxs2-dwc3";
+			status = "disabled";
+			reg = <0x65d00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
+			dwc3@65c00000 {
+				compatible = "snps,dwc3";
+				reg = <0x65c00000 0x10000>;
+				interrupts = <0 137 4>;
+				tx-fifo-resize;
+			};
+		};
+
+		nand: nand@68000000 {
+			compatible = "socionext,denali-nand-v5b";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+			clocks = <&sys_clk 2>;
+			nand-ecc-strength = <8>;
+		};
+	};
 };
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-sld3.dtsi b/arch/arm/dts/uniphier-sld3.dtsi
index f5c5487534..919cbff9de 100644
--- a/arch/arm/dts/uniphier-sld3.dtsi
+++ b/arch/arm/dts/uniphier-sld3.dtsi
@@ -50,12 +50,6 @@
 			compatible = "fixed-clock";
 			clock-frequency = <50000000>;
 		};
-
-		iobus_clk: iobus_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <100000000>;
-		};
 	};
 
 	soc {
@@ -251,7 +245,7 @@
 			interrupts = <0 41 1>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_i2c0>;
-			clocks = <&iobus_clk>;
+			clocks = <&sys_clk 1>;
 			clock-frequency = <100000>;
 		};
 
@@ -262,7 +256,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 42 1>;
-			clocks = <&iobus_clk>;
+			clocks = <&sys_clk 1>;
 			clock-frequency = <100000>;
 		};
 
@@ -273,7 +267,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 43 1>;
-			clocks = <&iobus_clk>;
+			clocks = <&sys_clk 1>;
 			clock-frequency = <100000>;
 		};
 
@@ -284,7 +278,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 44 1>;
-			clocks = <&iobus_clk>;
+			clocks = <&sys_clk 1>;
 			clock-frequency = <100000>;
 		};
 
@@ -295,7 +289,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 45 1>;
-			clocks = <&iobus_clk>;
+			clocks = <&sys_clk 1>;
 			clock-frequency = <400000>;
 		};
 
@@ -339,9 +333,12 @@
 			pinctrl-0 = <&pinctrl_emmc>;
 			pinctrl-1 = <&pinctrl_emmc_1v8>;
 			clocks = <&mio_clk 1>;
+			reset-names = "host", "bridge";
 			resets = <&mio_rst 1>, <&mio_rst 4>;
 			bus-width = <8>;
 			non-removable;
+			cap-mmc-highspeed;
+			cap-mmc-hw-reset;
 		};
 
 		sd: sdhc@5a500000 {
@@ -353,8 +350,13 @@
 			pinctrl-0 = <&pinctrl_sd>;
 			pinctrl-1 = <&pinctrl_sd_1v8>;
 			clocks = <&mio_clk 0>;
+			reset-names = "host", "bridge";
 			resets = <&mio_rst 0>, <&mio_rst 3>;
 			bus-width = <4>;
+			cap-sd-highspeed;
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
 		};
 
 		usb0: usb@5a800100 {
@@ -406,7 +408,8 @@
 		};
 
 		soc-glue@5f800000 {
-			compatible = "simple-mfd", "syscon";
+			compatible = "socionext,uniphier-sld3-soc-glue",
+				     "simple-mfd", "syscon";
 			reg = <0x5f800000 0x2000>;
 			u-boot,dm-pre-reloc;
 
@@ -422,7 +425,7 @@
 		};
 
 		sysctrl@f1840000 {
-			compatible = "socionext,uniphier-sysctrl",
+			compatible = "socionext,uniphier-sld3-sysctrl",
 				     "simple-mfd", "syscon";
 			reg = <0xf1840000 0x4000>;
 
@@ -438,9 +441,13 @@
 		};
 
 		nand: nand@f8000000 {
-			compatible = "denali,denali-nand-dt";
-			reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
+			compatible = "socionext,denali-nand-v5a";
+			status = "disabled";
 			reg-names = "nand_data", "denali_reg";
+			reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
+			interrupts = <0 65 4>;
+			clocks = <&sys_clk 2>;
+			nand-ecc-strength = <8>;
 		};
 	};
 };
diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi
index b8f6d67409..5550bb8257 100644
--- a/arch/arm/dts/uniphier-sld8.dtsi
+++ b/arch/arm/dts/uniphier-sld8.dtsi
@@ -7,7 +7,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/include/ "uniphier-common32.dtsi"
+/include/ "skeleton.dtsi"
 
 / {
 	compatible = "socionext,uniphier-sld8";
@@ -25,313 +25,438 @@
 		};
 	};
 
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
 	clocks {
-		arm_timer_clk: arm_timer_clk {
-			#clock-cells = <0>;
+		refclk: ref {
 			compatible = "fixed-clock";
-			clock-frequency = <50000000>;
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
 		};
 
-		iobus_clk: iobus_clk {
+		arm_timer_clk: arm_timer_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
-			clock-frequency = <100000000>;
+			clock-frequency = <50000000>;
 		};
 	};
-};
 
-&soc {
-	l2: l2-cache@500c0000 {
-		compatible = "socionext,uniphier-system-cache";
-		reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
-		interrupts = <0 174 4>, <0 175 4>;
-		cache-unified;
-		cache-size = <(256 * 1024)>;
-		cache-sets = <256>;
-		cache-line-size = <128>;
-		cache-level = <2>;
-	};
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		interrupt-parent = <&intc>;
+		u-boot,dm-pre-reloc;
+
+		l2: l2-cache@500c0000 {
+			compatible = "socionext,uniphier-system-cache";
+			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+			      <0x506c0000 0x400>;
+			interrupts = <0 174 4>, <0 175 4>;
+			cache-unified;
+			cache-size = <(256 * 1024)>;
+			cache-sets = <256>;
+			cache-line-size = <128>;
+			cache-level = <2>;
+		};
 
-	port0x: gpio@55000008 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000008 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial0: serial@54006800 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006800 0x40>;
+			interrupts = <0 33 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart0>;
+			clocks = <&peri_clk 0>;
+			clock-frequency = <80000000>;
+		};
 
-	port1x: gpio@55000010 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000010 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial1: serial@54006900 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006900 0x40>;
+			interrupts = <0 35 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart1>;
+			clocks = <&peri_clk 1>;
+			clock-frequency = <80000000>;
+		};
 
-	port2x: gpio@55000018 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000018 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial2: serial@54006a00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006a00 0x40>;
+			interrupts = <0 37 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart2>;
+			clocks = <&peri_clk 2>;
+			clock-frequency = <80000000>;
+		};
 
-	port3x: gpio@55000020 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000020 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial3: serial@54006b00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006b00 0x40>;
+			interrupts = <0 29 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart3>;
+			clocks = <&peri_clk 3>;
+			clock-frequency = <80000000>;
+		};
 
-	port4: gpio@55000028 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000028 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port0x: gpio@55000008 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000008 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port5x: gpio@55000030 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000030 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port1x: gpio@55000010 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000010 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port6x: gpio@55000038 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000038 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port2x: gpio@55000018 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000018 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port7x: gpio@55000040 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000040 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port3x: gpio@55000020 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000020 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port8x: gpio@55000048 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000048 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port4: gpio@55000028 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000028 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port9x: gpio@55000050 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000050 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port5x: gpio@55000030 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000030 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port10x: gpio@55000058 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000058 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port6x: gpio@55000038 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000038 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port11x: gpio@55000060 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000060 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port7x: gpio@55000040 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000040 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port12x: gpio@55000068 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000068 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port8x: gpio@55000048 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000048 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port13x: gpio@55000070 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000070 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port9x: gpio@55000050 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000050 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port14x: gpio@55000078 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000078 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port10x: gpio@55000058 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000058 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port16x: gpio@55000088 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000088 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port11x: gpio@55000060 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000060 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c0: i2c@58400000 {
-		compatible = "socionext,uniphier-i2c";
-		status = "disabled";
-		reg = <0x58400000 0x40>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 41 1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c0>;
-		clocks = <&iobus_clk>;
-		clock-frequency = <100000>;
-	};
+		port12x: gpio@55000068 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000068 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c1: i2c@58480000 {
-		compatible = "socionext,uniphier-i2c";
-		status = "disabled";
-		reg = <0x58480000 0x40>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 42 1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c1>;
-		clocks = <&iobus_clk>;
-		clock-frequency = <100000>;
-	};
+		port13x: gpio@55000070 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000070 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	/* chip-internal connection for DMD */
-	i2c2: i2c@58500000 {
-		compatible = "socionext,uniphier-i2c";
-		reg = <0x58500000 0x40>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 43 1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c2>;
-		clocks = <&iobus_clk>;
-		clock-frequency = <400000>;
-	};
+		port14x: gpio@55000078 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000078 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c3: i2c@58580000 {
-		compatible = "socionext,uniphier-i2c";
-		status = "disabled";
-		reg = <0x58580000 0x40>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 44 1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c3>;
-		clocks = <&iobus_clk>;
-		clock-frequency = <100000>;
-	};
+		port16x: gpio@55000088 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000088 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	sd: sdhc@5a400000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x5a400000 0x200>;
-		interrupts = <0 76 4>;
-		pinctrl-names = "default", "1.8v";
-		pinctrl-0 = <&pinctrl_sd>;
-		pinctrl-1 = <&pinctrl_sd_1v8>;
-		clocks = <&mio_clk 0>;
-		reset-names = "host", "bridge";
-		resets = <&mio_rst 0>, <&mio_rst 3>;
-		bus-width = <4>;
-	};
+		i2c0: i2c@58400000 {
+			compatible = "socionext,uniphier-i2c";
+			status = "disabled";
+			reg = <0x58400000 0x40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 41 1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c0>;
+			clocks = <&peri_clk 4>;
+			clock-frequency = <100000>;
+		};
 
-	emmc: sdhc@5a500000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		interrupts = <0 78 4>;
-		reg = <0x5a500000 0x200>;
-		pinctrl-names = "default", "1.8v";
-		pinctrl-0 = <&pinctrl_emmc>;
-		pinctrl-1 = <&pinctrl_emmc_1v8>;
-		clocks = <&mio_clk 1>;
-		reset-names = "host", "bridge", "hw-reset";
-		resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
-		bus-width = <8>;
-		non-removable;
-	};
+		i2c1: i2c@58480000 {
+			compatible = "socionext,uniphier-i2c";
+			status = "disabled";
+			reg = <0x58480000 0x40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 42 1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c1>;
+			clocks = <&peri_clk 5>;
+			clock-frequency = <100000>;
+		};
 
-	usb0: usb@5a800100 {
-		compatible = "socionext,uniphier-ehci", "generic-ehci";
-		status = "disabled";
-		reg = <0x5a800100 0x100>;
-		interrupts = <0 80 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb0>;
-		clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
-		resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
-			 <&mio_rst 12>;
-	};
+		/* chip-internal connection for DMD */
+		i2c2: i2c@58500000 {
+			compatible = "socionext,uniphier-i2c";
+			reg = <0x58500000 0x40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 43 1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c2>;
+			clocks = <&peri_clk 6>;
+			clock-frequency = <400000>;
+		};
 
-	usb1: usb@5a810100 {
-		compatible = "socionext,uniphier-ehci", "generic-ehci";
-		status = "disabled";
-		reg = <0x5a810100 0x100>;
-		interrupts = <0 81 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb1>;
-		clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
-		resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
-			 <&mio_rst 13>;
-	};
+		i2c3: i2c@58580000 {
+			compatible = "socionext,uniphier-i2c";
+			status = "disabled";
+			reg = <0x58580000 0x40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 44 1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c3>;
+			clocks = <&peri_clk 7>;
+			clock-frequency = <100000>;
+		};
 
-	usb2: usb@5a820100 {
-		compatible = "socionext,uniphier-ehci", "generic-ehci";
-		status = "disabled";
-		reg = <0x5a820100 0x100>;
-		interrupts = <0 82 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb2>;
-		clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
-		resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
-			 <&mio_rst 14>;
-	};
+		system_bus: system-bus@58c00000 {
+			compatible = "socionext,uniphier-system-bus";
+			status = "disabled";
+			reg = <0x58c00000 0x400>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_system_bus>;
+		};
 
-	aidet@61830000 {
-		compatible = "simple-mfd", "syscon";
-		reg = <0x61830000 0x200>;
-	};
-};
+		smpctrl@59800000 {
+			compatible = "socionext,uniphier-smpctrl";
+			reg = <0x59801000 0x400>;
+		};
 
-&refclk {
-	clock-frequency = <25000000>;
-};
+		mioctrl@59810000 {
+			compatible = "socionext,uniphier-sld8-mioctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59810000 0x800>;
 
-&serial0 {
-	clock-frequency = <80000000>;
-};
+			mio_clk: clock {
+				compatible = "socionext,uniphier-sld8-mio-clock";
+				#clock-cells = <1>;
+			};
 
-&serial1 {
-	clock-frequency = <80000000>;
-};
+			mio_rst: reset {
+				compatible = "socionext,uniphier-sld8-mio-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-&serial2 {
-	clock-frequency = <80000000>;
-};
+		perictrl@59820000 {
+			compatible = "socionext,uniphier-sld8-perictrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59820000 0x200>;
 
-&serial3 {
-	interrupts = <0 29 4>;
-	clock-frequency = <80000000>;
-};
+			peri_clk: clock {
+				compatible = "socionext,uniphier-sld8-peri-clock";
+				#clock-cells = <1>;
+			};
 
-&mio_clk {
-	compatible = "socionext,uniphier-sld8-mio-clock";
-};
+			peri_rst: reset {
+				compatible = "socionext,uniphier-sld8-peri-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-&mio_rst {
-	compatible = "socionext,uniphier-sld8-mio-reset";
-};
+		sd: sdhc@5a400000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a400000 0x200>;
+			interrupts = <0 76 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_sd>;
+			pinctrl-1 = <&pinctrl_sd_1v8>;
+			clocks = <&mio_clk 0>;
+			reset-names = "host", "bridge";
+			resets = <&mio_rst 0>, <&mio_rst 3>;
+			bus-width = <4>;
+			cap-sd-highspeed;
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+		};
 
-&peri_clk {
-	compatible = "socionext,uniphier-sld8-peri-clock";
-};
+		emmc: sdhc@5a500000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a500000 0x200>;
+			interrupts = <0 78 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_emmc>;
+			pinctrl-1 = <&pinctrl_emmc_1v8>;
+			clocks = <&mio_clk 1>;
+			reset-names = "host", "bridge";
+			resets = <&mio_rst 1>, <&mio_rst 4>;
+			bus-width = <8>;
+			non-removable;
+			cap-mmc-highspeed;
+			cap-mmc-hw-reset;
+		};
 
-&peri_rst {
-	compatible = "socionext,uniphier-sld8-peri-reset";
-};
+		usb0: usb@5a800100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a800100 0x100>;
+			interrupts = <0 80 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>;
+			clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+				 <&mio_rst 12>;
+		};
 
-&pinctrl {
-	compatible = "socionext,uniphier-sld8-pinctrl";
-};
+		usb1: usb@5a810100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a810100 0x100>;
+			interrupts = <0 81 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>;
+			clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+				 <&mio_rst 13>;
+		};
 
-&sys_clk {
-	compatible = "socionext,uniphier-sld8-clock";
-};
+		usb2: usb@5a820100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a820100 0x100>;
+			interrupts = <0 82 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb2>;
+			clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+				 <&mio_rst 14>;
+		};
+
+		soc-glue@5f800000 {
+			compatible = "socionext,uniphier-sld8-soc-glue",
+				     "simple-mfd", "syscon";
+			reg = <0x5f800000 0x2000>;
+			u-boot,dm-pre-reloc;
+
+			pinctrl: pinctrl {
+				compatible = "socionext,uniphier-sld8-pinctrl";
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		timer@60000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x60000200 0x20>;
+			interrupts = <1 11 0x104>;
+			clocks = <&arm_timer_clk>;
+		};
 
-&sys_rst {
-	compatible = "socionext,uniphier-sld8-reset";
+		timer@60000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x60000600 0x20>;
+			interrupts = <1 13 0x104>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		intc: interrupt-controller@60001000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0x60001000 0x1000>,
+			      <0x60000100 0x100>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+		};
+
+		aidet@61830000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x61830000 0x200>;
+		};
+
+		sysctrl@61840000 {
+			compatible = "socionext,uniphier-sld8-sysctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x61840000 0x10000>;
+
+			sys_clk: clock {
+				compatible = "socionext,uniphier-sld8-clock";
+				#clock-cells = <1>;
+			};
+
+			sys_rst: reset {
+				compatible = "socionext,uniphier-sld8-reset";
+				#reset-cells = <1>;
+			};
+		};
+
+		nand: nand@68000000 {
+			compatible = "socionext,denali-nand-v5a";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+			clocks = <&sys_clk 2>;
+			nand-ecc-strength = <8>;
+		};
+	};
 };
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/include/asm/arch-armada8k/cache_llc.h b/arch/arm/include/asm/arch-armada8k/cache_llc.h
new file mode 100644
index 0000000000..8f97e6d776
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada8k/cache_llc.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#ifndef _CACHE_LLC_H_
+#define _CACHE_LLC_H_
+
+/* Armada-7K/8K last level cache */
+
+#define MVEBU_A8K_REGS_BASE_MSB		0xf000
+#define LLC_BASE_ADDR			0x8000
+#define LLC_CACHE_SYNC			0x700
+#define LLC_CACHE_SYNC_COMPLETE		0x730
+#define LLC_FLUSH_BY_WAY		0x7fc
+#define LLC_WAY_MASK			0xffffffff
+#define LLC_CACHE_SYNC_MASK		0x1
+
+#endif	/* _CACHE_LLC_H_ */
diff --git a/arch/arm/include/asm/arch-armada8k/soc-info.h b/arch/arm/include/asm/arch-armada8k/soc-info.h
new file mode 100644
index 0000000000..bae39951ee
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada8k/soc-info.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#ifndef _SOC_INFO_H_
+#define _SOC_INFO_H_
+
+/* Pin Ctrl driver definitions */
+#define BITS_PER_PIN		4
+#define PIN_FUNC_MASK		((1 << BITS_PER_PIN) - 1)
+#define PIN_REG_SHIFT		3
+#define PIN_FIELD_MASK		((1 << PIN_REG_SHIFT) - 1)
+
+#endif	/* _SOC_INFO_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d684a07730..b3cfd89a4b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -18,6 +18,7 @@
 #define CONFIG_SYS_CCI400_ADDR			(CONFIG_SYS_IMMR + 0x00180000)
 #define CONFIG_SYS_GIC400_ADDR			(CONFIG_SYS_IMMR + 0x00400000)
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
+#define SYS_FSL_QSPI_ADDR			(CONFIG_SYS_IMMR + 0x00550000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
 #define CONFIG_SYS_FSL_CSU_ADDR			(CONFIG_SYS_IMMR + 0x00510000)
 #define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 2df56f7a5b..e18dcbdd09 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -19,6 +19,7 @@
 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR	(CONFIG_SYS_IMMR + 0x00300000)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR	(CONFIG_SYS_IMMR + 0x00310000)
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR + 0x00370000)
+#define SYS_FSL_QSPI_ADDR			(CONFIG_SYS_IMMR + 0x010c0000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x01140000)
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011C0500)
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index b00decec6d..9a46340deb 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -1171,6 +1171,7 @@ struct emif_regs {
 	u32 sdram_tim1;
 	u32 sdram_tim2;
 	u32 sdram_tim3;
+	u32 ocp_config;
 	u32 read_idle_ctrl;
 	u32 zq_config;
 	u32 temp_alert_config;
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 7733936be5..40476dc421 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -83,8 +83,8 @@ config TARGET_DB_88F6820_AMC
 	bool "Support DB-88F6820-AMC"
 	select 88F6820
 
-config TARGET_MVEBU_DB_88F7040
-	bool "Support DB-88F7040 Armada 7040"
+config TARGET_MVEBU_ARMADA_8K
+	bool "Support Armada 7k/8k platforms"
 	select ARMADA_8K
 
 config TARGET_DB_MV784MP_GP
@@ -111,7 +111,7 @@ config SYS_BOARD
 	default "db-88f6720" if TARGET_DB_88F6720
 	default "db-88f6820-gp" if TARGET_DB_88F6820_GP
 	default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
-	default "mvebu_db-88f7040" if TARGET_MVEBU_DB_88F7040
+	default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
 	default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
 	default "ds414" if TARGET_DS414
 	default "maxbcm" if TARGET_MAXBCM
@@ -123,7 +123,7 @@ config SYS_CONFIG_NAME
 	default "db-88f6720" if TARGET_DB_88F6720
 	default "db-88f6820-gp" if TARGET_DB_88F6820_GP
 	default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
-	default "mvebu_db-88f7040" if TARGET_MVEBU_DB_88F7040
+	default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
 	default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
 	default "ds414" if TARGET_DS414
 	default "maxbcm" if TARGET_MAXBCM
@@ -135,7 +135,7 @@ config SYS_VENDOR
 	default "Marvell" if TARGET_DB_88F6720
 	default "Marvell" if TARGET_DB_88F6820_GP
 	default "Marvell" if TARGET_DB_88F6820_AMC
-	default "Marvell" if TARGET_MVEBU_DB_88F7040
+	default "Marvell" if TARGET_MVEBU_ARMADA_8K
 	default "solidrun" if TARGET_CLEARFOG
 	default "Synology" if TARGET_DS414
 
diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c
index 7055a81de3..8f026559c2 100644
--- a/arch/arm/mach-mvebu/arm64-common.c
+++ b/arch/arm/mach-mvebu/arm64-common.c
@@ -17,6 +17,23 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
+ * Not all memory is mapped in the MMU. So we need to restrict the
+ * memory size so that U-Boot does not try to access it. Also, the
+ * internal registers are located at 0xf000.0000 - 0xffff.ffff.
+ * Currently only 2GiB are mapped for system memory. This is what
+ * we pass to the U-Boot subsystem here.
+ */
+#define USABLE_RAM_SIZE		0x80000000
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+	if (gd->ram_size > USABLE_RAM_SIZE)
+		return USABLE_RAM_SIZE;
+
+	return gd->ram_size;
+}
+
+/*
  * On ARMv8, MBus is not configured in U-Boot. To enable compilation
  * of the already implemented drivers, lets add a dummy version of
  * this function so that linking does not fail.
@@ -109,12 +126,20 @@ int arch_early_init_r(void)
 {
 	struct udevice *dev;
 	int ret;
-
-	/* Call the comphy code via the MISC uclass driver */
-	ret = uclass_get_device(UCLASS_MISC, 0, &dev);
-	if (ret) {
-		debug("COMPHY init failed: %d\n", ret);
-		return -ENODEV;
+	int i;
+
+	/*
+	 * Loop over all MISC uclass drivers to call the comphy code
+	 * and init all CP110 devices enabled in the DT
+	 */
+	i = 0;
+	while (1) {
+		/* Call the comphy code via the MISC uclass driver */
+		ret = uclass_get_device(UCLASS_MISC, i++, &dev);
+
+		/* We're done, once no further CP110 device is found */
+		if (ret)
+			break;
 	}
 
 	/* Cause the SATA device to do its early init */
diff --git a/arch/arm/mach-mvebu/armada8k/Makefile b/arch/arm/mach-mvebu/armada8k/Makefile
index 84c69d90e7..0facf14942 100644
--- a/arch/arm/mach-mvebu/armada8k/Makefile
+++ b/arch/arm/mach-mvebu/armada8k/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y = cpu.o
+obj-y += cache_llc.o
diff --git a/arch/arm/mach-mvebu/armada8k/cache_llc.S b/arch/arm/mach-mvebu/armada8k/cache_llc.S
new file mode 100644
index 0000000000..71aecb2dde
--- /dev/null
+++ b/arch/arm/mach-mvebu/armada8k/cache_llc.S
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#include <asm/arch-armada8k/cache_llc.h>
+#include <linux/linkage.h>
+
+/*
+ * int __asm_flush_l3_dcache
+ *
+ * flush Armada-8K last level cache.
+ *
+ */
+ENTRY(__asm_flush_l3_dcache)
+	/* flush cache */
+	mov     x0, #LLC_BASE_ADDR
+	add	x0, x0, #LLC_FLUSH_BY_WAY
+	movk    x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16
+	mov     w1, #LLC_WAY_MASK
+	str     w1, [x0]
+	/* sync cache */
+	mov     x0, #LLC_BASE_ADDR
+	add	x0, x0, #LLC_CACHE_SYNC
+	movk    x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16
+	str     wzr, [x0]
+	/* check that cache sync completed */
+	mov     x0, #LLC_BASE_ADDR
+	add	x0, x0, #LLC_CACHE_SYNC_COMPLETE
+	movk    x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16
+1:	ldr	w1, [x0]
+	and	w1, w1, #LLC_CACHE_SYNC_MASK
+	cbnz	w1, 1b
+	/* return success */
+	mov	x0, #0
+	ret
+ENDPROC(__asm_flush_l3_dcache)
diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c
index 036430c46c..2719d68e07 100644
--- a/arch/arm/mach-mvebu/armada8k/cpu.c
+++ b/arch/arm/mach-mvebu/armada8k/cpu.c
@@ -39,7 +39,7 @@ static struct mm_region mvebu_mem_map[] = {
 			 PTE_BLOCK_NON_SHARE
 	},
 	{
-		/* SRAM, MMIO regions - CP110 region */
+		/* SRAM, MMIO regions - CP110 master region */
 		.phys = 0xf2000000UL,
 		.virt = 0xf2000000UL,
 		.size = 0x02000000UL,	/* 32MiB internal registers */
@@ -47,6 +47,22 @@ static struct mm_region mvebu_mem_map[] = {
 			 PTE_BLOCK_NON_SHARE
 	},
 	{
+		/* SRAM, MMIO regions - CP110 slave region */
+		.phys = 0xf4000000UL,
+		.virt = 0xf4000000UL,
+		.size = 0x02000000UL,	/* 32MiB internal registers */
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE
+	},
+	{
+		/* PCI regions */
+		.phys = 0xf8000000UL,
+		.virt = 0xf8000000UL,
+		.size = 0x08000000UL,	/* 128MiB PCI space (master & slave) */
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE
+	},
+	{
 		/* List terminator */
 		0,
 	}
diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c
index 6acf30c5db..690487e7c3 100644
--- a/arch/arm/mach-omap2/am33xx/ddr.c
+++ b/arch/arm/mach-omap2/am33xx/ddr.c
@@ -180,6 +180,10 @@ void config_sdram(const struct emif_regs *regs, int nr)
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+
+	/* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
+	if (regs->ocp_config)
+		writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
 }
 
 /**
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index d91b8bbceb..6991af8775 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -74,6 +74,10 @@ config TARGET_SOCFPGA_TERASIC_DE0_NANO
 	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_TERASIC_DE1_SOC
+	bool "Terasic DE1-SoC (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_SOCKIT
 	bool "Terasic SoCkit (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
@@ -84,6 +88,7 @@ config SYS_BOARD
 	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 	default "is1" if TARGET_SOCFPGA_IS1
 	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
@@ -98,6 +103,7 @@ config SYS_VENDOR
 	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+	default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 
 config SYS_SOC
@@ -107,6 +113,7 @@ config SYS_CONFIG_NAME
 	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 	default "socfpga_is1" if TARGET_SOCFPGA_IS1
 	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h
new file mode 100644
index 0000000000..aaada31286
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/boot0.h
@@ -0,0 +1,28 @@
+/*
+ * Specialty padding for the Altera SoCFPGA preloader image
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+#ifdef CONFIG_SPL_BUILD
+#define ARM_SOC_BOOT0_HOOK						\
+	.balignl 64,0xf33db33f;						\
+									\
+	.word	0x1337c0d3;	/* SoCFPGA preloader validation word */	\
+	.word	0xc01df00d;	/* Version, flags, length */		\
+	.word	0xcafec0d3;	/* Checksum, zero-pad */		\
+	nop;								\
+									\
+	b reset;		/* SoCFPGA jumps here */		\
+	nop;								\
+	nop;								\
+	nop;
+#else
+#define ARM_SOC_BOOT0_HOOK
+#endif
+
+
+#endif /* __BOOT0_H */
diff --git a/arch/arm/mach-socfpga/qts-filter.sh b/arch/arm/mach-socfpga/qts-filter.sh
index 1148a71311..785a0d5ea2 100755
--- a/arch/arm/mach-socfpga/qts-filter.sh
+++ b/arch/arm/mach-socfpga/qts-filter.sh
@@ -1,6 +1,14 @@
 #!/bin/sh
 
 #
+# helper function to convert from DOS to Unix, if necessary, and handle
+# lines ending in '\'.
+#
+fix_newlines_in_macros() {
+	sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
+}
+
+#
 # Process iocsr_config_*.[ch]
 # $1:	SoC type
 # $2:	Input handoff directory
@@ -27,14 +35,16 @@ process_iocsr_config() {
 EOF
 
 	# Retrieve the scan chain lengths
-	grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH'			\
-		${in_bsp_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
+	fix_newlines_in_macros \
+		${in_bsp_dir}/generated/iocsr_config_${soc}.h |
+	grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH'	| tr -d "()"
 
 	echo ""
 
 	# Retrieve the scan chain config and zap the ad-hoc length encoding
-	sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}'	\
-		${in_bsp_dir}/generated/iocsr_config_${soc}.c
+	fix_newlines_in_macros \
+		${in_bsp_dir}/generated/iocsr_config_${soc}.c |
+	sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}'
 
 	cat << EOF
 
@@ -69,8 +79,9 @@ process_pinmux_config() {
 EOF
 
 	# Retrieve the pinmux config and zap the ad-hoc length encoding
-	sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}' \
-		${in_bsp_dir}/generated/pinmux_config_${soc}.c
+	fix_newlines_in_macros \
+		${in_bsp_dir}/generated/pinmux_config_${soc}.c |
+	sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}'
 
 	cat << EOF
 
@@ -105,8 +116,9 @@ process_pll_config() {
 EOF
 
 	# Retrieve the pll config and zap parenthesis
-	sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' \
-		${in_bsp_dir}/generated/pll_config.h
+	fix_newlines_in_macros \
+		${in_bsp_dir}/generated/pll_config.h |
+	sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}'
 
 	cat << EOF
 
@@ -149,32 +161,37 @@ EOF
 
 	echo "/* SDRAM configuration */"
 	# Retrieve the sdram config, zap broken lines and zap parenthesis
-	sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p"		\
+	fix_newlines_in_macros \
 		${in_bsp_dir}/generated/sdram/sdram_config.h |
+	sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" |
 	sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
 		sort -u | grep_sdram_config
 
 	echo ""
 	echo "/* Sequencer auto configuration */"
-	sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}"		\
+	fix_newlines_in_macros \
 		${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h |
+	sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" |
 		sort -u | grep_sdram_config
 
 	echo ""
 	echo "/* Sequencer defines configuration */"
-	sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}"	\
+	fix_newlines_in_macros \
 		${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h |
+	sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" |
 		sort -u | grep_sdram_config
 
 	echo ""
 	echo "/* Sequencer ac_rom_init configuration */"
-	sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
-		${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
+	fix_newlines_in_macros \
+		${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c |
+	sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'
 
 	echo ""
 	echo "/* Sequencer inst_rom_init configuration */"
-	sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
-		${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
+	fix_newlines_in_macros \
+		${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c |
+	sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'
 
 	cat << EOF
 
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 0f8ead980c..aa11493748 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -142,7 +142,7 @@ static int spl_board_load_image(struct spl_image_info *spl_image,
 
 	return 0;
 }
-SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_BOARD, spl_board_load_image);
+SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
 #endif
 
 void s_init(void)
@@ -247,15 +247,6 @@ u32 spl_boot_device(void)
 	return -1;		/* Never reached */
 }
 
-/*
- * Properly announce BOOT_DEVICE_BOARD as "FEL".
- * Overrides weak function from common/spl/spl.c
- */
-void spl_board_announce_boot_device(void)
-{
-	printf("FEL");
-}
-
 /* No confirmation data available in SPL yet. Hardcode bootmode */
 u32 spl_boot_mode(const u32 boot_device)
 {
diff --git a/arch/arm/mach-uniphier/boot-mode/spl_board.c b/arch/arm/mach-uniphier/boot-mode/spl_board.c
index 854ab056da..a6b668656b 100644
--- a/arch/arm/mach-uniphier/boot-mode/spl_board.c
+++ b/arch/arm/mach-uniphier/boot-mode/spl_board.c
@@ -12,11 +12,6 @@
 
 #include "../soc-info.h"
 
-void spl_board_announce_boot_device(void)
-{
-	printf("eMMC");
-}
-
 struct uniphier_romfunc_table {
 	void *mmc_send_cmd;
 	void *mmc_card_blockaddr;
@@ -127,4 +122,4 @@ static int spl_board_load_image(struct spl_image_info *spl_image,
 
 	return 0;
 }
-SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_BOARD, spl_board_load_image);
+SPL_LOAD_IMAGE_METHOD("eMMC", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
diff --git a/arch/arm/mach-uniphier/dram/umc-ld20.c b/arch/arm/mach-uniphier/dram/umc-ld20.c
index b8c0f59e17..ecbe101617 100644
--- a/arch/arm/mach-uniphier/dram/umc-ld20.c
+++ b/arch/arm/mach-uniphier/dram/umc-ld20.c
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2016 Socionext Inc.
  *
- * based on commit a7a36122aa072fe1bb06e02b73b3634b7a6c555a of Diag
+ * based on commit 5e1cb0f1caeabc6c99469dd997cb6b4f46834443 of Diag
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -264,8 +264,8 @@ static int ddrphy_ip_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
 static void ddrphy_select_lane(void __iomem *phy_base, unsigned int lane,
 			       unsigned int bit)
 {
-	WARN_ON(lane >= (1 << PHY_LANE_SEL_LANE_WIDTH));
-	WARN_ON(bit >= (1 << PHY_LANE_SEL_BIT_WIDTH));
+	WARN_ON(lane >= 1 << PHY_LANE_SEL_LANE_WIDTH);
+	WARN_ON(bit >= 1 << PHY_LANE_SEL_BIT_WIDTH);
 
 	writel((bit << PHY_LANE_SEL_BIT_SHIFT) |
 	       (lane << PHY_LANE_SEL_LANE_SHIFT),
diff --git a/arch/arm/mach-uniphier/memconf/memconf.c b/arch/arm/mach-uniphier/memconf/memconf.c
index 3d4b50456b..e607ac9c3b 100644
--- a/arch/arm/mach-uniphier/memconf/memconf.c
+++ b/arch/arm/mach-uniphier/memconf/memconf.c
@@ -1,5 +1,7 @@
 /*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2016      Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -14,7 +16,7 @@
 
 int memconf_init(const struct uniphier_board_data *bd)
 {
-	u32 tmp = 0;
+	u32 tmp;
 	unsigned long size_per_word;
 
 	tmp = readl(SG_MEMCONF);
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index c2402a8bda..d1b6699a6a 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -45,7 +45,9 @@
 #include <nand.h>
 #include <errno.h>
 #endif
-
+#ifndef CONFIG_ARCH_QEMU_E500
+#include <fsl_ddr.h>
+#endif
 #include "../../../../drivers/block/fsl_sata.h"
 #ifdef CONFIG_U_QE
 #include <fsl_qe.h>
@@ -947,6 +949,10 @@ int cpu_init_r(void)
 
 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+	erratum_a009942_check_cpo();
+#endif
+
 #ifdef CONFIG_FMAN_ENET
 	fman_enet_init();
 #endif
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 4877b75981..603d6aeadc 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -512,7 +512,6 @@
 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_A004468
-#define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A007186
@@ -549,7 +548,6 @@
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A007186
diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c
index 1ad7fb6c60..7cc76d4cf1 100644
--- a/arch/sandbox/cpu/spl.c
+++ b/arch/sandbox/cpu/spl.c
@@ -25,19 +25,6 @@ u32 spl_boot_device(void)
 	return BOOT_DEVICE_BOARD;
 }
 
-void spl_board_announce_boot_device(void)
-{
-	char fname[256];
-	int ret;
-
-	ret = os_find_u_boot(fname, sizeof(fname));
-	if (ret) {
-		printf("(%s not found, error %d)\n", fname, ret);
-		return;
-	}
-	printf("%s\n", fname);
-}
-
 static int spl_board_load_image(struct spl_image_info *spl_image,
 				struct spl_boot_device *bootdev)
 {
@@ -45,13 +32,15 @@ static int spl_board_load_image(struct spl_image_info *spl_image,
 	int ret;
 
 	ret = os_find_u_boot(fname, sizeof(fname));
-	if (ret)
+	if (ret) {
+		printf("(%s not found, error %d)\n", fname, ret);
 		return ret;
+	}
 
 	/* Hopefully this will not return */
 	return os_spl_to_uboot(fname);
 }
-SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_BOARD, spl_board_load_image);
+SPL_LOAD_IMAGE_METHOD("sandbox", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
 
 void spl_board_init(void)
 {