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authorLokesh Vutla <lokeshvutla@ti.com>2018-04-26 18:21:28 +0530
committerTom Rini <trini@konsulko.com>2018-05-07 15:53:28 -0400
commitf4bcd767bdc0925528e66974af7575a5796aaab7 (patch)
treeb436d3fd8ee25efa3c9b704076c141d7b8899927 /arch
parent7240b80ee03ef712070d985cc9ed7b6c54e5764f (diff)
arm: v7: Kconfig: Introduce SYS_ARM_CACHE_CP15
Certain ARM architectures like ARMv7-A, ARMv7-R has support for enabling caches using CP15 registers. To have a common support for all these architectures, introduce a Kconfig symbol SYS_ARM_CACHE_CP15 that selects cache-cp15.c Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig7
-rw-r--r--arch/arm/lib/Makefile6
2 files changed, 8 insertions, 5 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5ff6809e94..fd6d2011af 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -74,8 +74,15 @@ config ARM_ASM_UNIFIED
config THUMB2_KERNEL
bool
+config SYS_ARM_CACHE_CP15
+ bool "CP15 based cache enabling support"
+ help
+ Select this if your processor suports enabling caches by using
+ CP15 registers.
+
config SYS_ARM_MMU
bool "MMU-based Paged Memory Management Support"
+ select SYS_ARM_CACHE_CP15
help
Select if you want MMU-based virtualised addressing space
support by paged memory management.
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 77a3be4266..655727f431 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -61,11 +61,7 @@ obj-y += reset.o
endif
obj-y += cache.o
-ifndef CONFIG_ARM64
-ifndef CONFIG_CPU_V7M
-obj-y += cache-cp15.o
-endif
-endif
+obj-$(CONFIG_SYS_ARM_CACHE_CP15) += cache-cp15.o
obj-y += psci-dt.o