Merge tag 'u-boot-imx-20200115' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

-----------------------------------
- imx8:
	add capricorn giedi deneb boards
- imx6:
	fixed fow wandboard
- imx7: DM_ETHER for pico-imx7d
- fsl_esdhc_imx: add broken-cd property
- New SOC: IMXRT10xx

Travis:
	https://travis-ci.org/sbabic/u-boot-imx/builds/637126531

23 files changed, 1009 insertions, 8 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8f950778bd..ee3ca8d182 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -807,6 +807,14 @@ config ARCH_IMX8M
 	select SUPPORT_SPL
 	imply CMD_DM
 
+config ARCH_IMXRT
+	bool "NXP i.MXRT platform"
+	select CPU_V7M
+	select DM
+	select DM_SERIAL
+	select SUPPORT_SPL
+	imply CMD_DM
+
 config ARCH_MX23
 	bool "NXP i.MX23 family"
 	select CPU_ARM926EJS
@@ -1732,6 +1740,8 @@ source "arch/arm/mach-imx/imx8/Kconfig"
 
 source "arch/arm/mach-imx/imx8m/Kconfig"
 
+source "arch/arm/mach-imx/imxrt/Kconfig"
+
 source "arch/arm/mach-imx/mxs/Kconfig"
 
 source "arch/arm/mach-omap2/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 856f2d8608..1e60a9fdd4 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -104,11 +104,11 @@ libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/
 
 ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imxrt))
 libs-y += arch/arm/mach-imx/
 endif
 else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imxrt vf610))
 libs-y += arch/arm/mach-imx/
 endif
 endif
diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
index f4ba3ad50e..7353698557 100644
--- a/arch/arm/cpu/armv7m/cache.c
+++ b/arch/arm/cpu/armv7m/cache.c
@@ -291,6 +291,12 @@ void flush_dcache_all(void)
 void invalidate_dcache_all(void)
 {
 }
+
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+				     enum dcache_option option)
+{
+}
+
 #endif
 
 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 983e235f44..d7e625ef1d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -699,7 +699,9 @@ dtb-$(CONFIG_ARCH_IMX8) += \
 	imx8qm-rom7720-a1.dtb \
 	fsl-imx8qxp-ai_ml.dtb \
 	fsl-imx8qxp-colibri.dtb \
-	fsl-imx8qxp-mek.dtb
+	fsl-imx8qxp-mek.dtb \
+	imx8-deneb.dtb \
+	imx8-giedi.dtb
 
 dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mm-evk.dtb \
@@ -707,6 +709,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mq-evk.dtb \
 	imx8mp-evk.dtb
 
+dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb
+
 dtb-$(CONFIG_RCAR_GEN2) += \
 	r8a7790-lager-u-boot.dtb \
 	r8a7790-stout-u-boot.dtb \
diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi
index 0c33eee6d2..ae1d1f460b 100644
--- a/arch/arm/dts/fsl-imx8dx.dtsi
+++ b/arch/arm/dts/fsl-imx8dx.dtsi
@@ -268,8 +268,9 @@
 		reg = <0x0 0x5a800000 0x0 0x4000>;
 		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-parent = <&gic>;
-		clocks = <&clk IMX8QXP_I2C0_CLK>;
-		clock-names = "per";
+		clocks = <&clk IMX8QXP_I2C0_CLK>,
+			<&clk IMX8QXP_I2C0_IPG_CLK>;
+		clock-names = "per", "ipg";
 		assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
 		assigned-clock-rates = <24000000>;
 		power-domains = <&pd_dma_lpi2c0>;
@@ -299,8 +300,9 @@
 		reg = <0x0 0x5a820000 0x0 0x4000>;
 		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-parent = <&gic>;
-		clocks = <&clk IMX8QXP_I2C2_CLK>;
-		clock-names = "per";
+		clocks = <&clk IMX8QXP_I2C2_CLK>,
+			<&clk IMX8QXP_I2C2_IPG_CLK>;
+		clock-names = "per", "ipg";
 		assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
 		assigned-clock-rates = <24000000>;
 		power-domains = <&pd_dma_lpi2c2>;
diff --git a/arch/arm/dts/imx6ul-14x14-evk.dtsi b/arch/arm/dts/imx6ul-14x14-evk.dtsi
index d1baf0f081..463d7ca124 100644
--- a/arch/arm/dts/imx6ul-14x14-evk.dtsi
+++ b/arch/arm/dts/imx6ul-14x14-evk.dtsi
@@ -268,6 +268,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc2>;
 	no-1-8-v;
+	broken-cd;
 	keep-power-in-suspend;
 	wakeup-source;
 	status = "okay";
diff --git a/arch/arm/dts/imx8-deneb.dts b/arch/arm/dts/imx8-deneb.dts
new file mode 100644
index 0000000000..04c764aa94
--- /dev/null
+++ b/arch/arm/dts/imx8-deneb.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Siemens AG
+ */
+
+#include "imx8qxp-capricorn.dtsi"
+
+/ {
+	model = "Siemens Deneb";
+};
diff --git a/arch/arm/dts/imx8-giedi.dts b/arch/arm/dts/imx8-giedi.dts
new file mode 100644
index 0000000000..0dbfef2ee9
--- /dev/null
+++ b/arch/arm/dts/imx8-giedi.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Siemens AG
+ */
+
+#include "imx8qxp-capricorn.dtsi"
+
+/ {
+	model = "Siemens Giedi";
+};
diff --git a/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi b/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi
new file mode 100644
index 0000000000..1cf58fc3f9
--- /dev/null
+++ b/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Siemens AG
+ */
+
+&{/imx8qx-pm} {
+
+	u-boot,dm-spl;
+};
+
+&mu {
+	u-boot,dm-spl;
+};
+
+&clk {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&pd_lsio {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio0 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio1 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio3 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio6 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio7 {
+	u-boot,dm-spl;
+};
+
+&pd_dma {
+	u-boot,dm-spl;
+};
+
+&pd_dma_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pd_dma_lpuart2 {
+	u-boot,dm-spl;
+};
+
+&pd_conn {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+	u-boot,dm-spl;
+};
+
+&gpio0 {
+	u-boot,dm-spl;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio3 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&gpio6 {
+	u-boot,dm-spl;
+};
+
+&gpio7 {
+	u-boot,dm-spl;
+};
+
+&lpuart0 {
+	u-boot,dm-spl;
+};
+
+&lpuart2 {
+	u-boot,dm-spl;
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8qxp-capricorn.dtsi b/arch/arm/dts/imx8qxp-capricorn.dtsi
new file mode 100644
index 0000000000..db5653ea1f
--- /dev/null
+++ b/arch/arm/dts/imx8qxp-capricorn.dtsi
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 NXP
+ *
+ * Copyright 2019 Siemens AG
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qxp.dtsi"
+#include "imx8qxp-capricorn-u-boot.dtsi"
+
+/ {
+	model = "Siemens Giedi";
+	compatible = "siemens,capricorn", "fsl,imx8qxp";
+
+	chosen {
+		bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
+		stdout-path = &lpuart2;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+
+		run {
+			label = "run";
+			gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		flt {
+			label = "flt";
+			gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		svc {
+			label = "svc";
+			gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		com1_tx {
+			label = "com1-tx";
+			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		com1_rx {
+			label = "com1-rx";
+			gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		com2_tx {
+			label = "com2-tx";
+			gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		com2_rx {
+			label = "com2-rx";
+			gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		cloud {
+			label = "cloud";
+			gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		wlan {
+			label = "wlan";
+			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		dbg1 {
+			label = "dbg1";
+			gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		dbg2 {
+			label = "dbg2";
+			gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		dbg3 {
+			label = "dbg3";
+			gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		dbg4 {
+			label = "dbg4";
+			gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	muxcgrp: imx8qxp-som {
+		pinctrl_gpio_leds: gpioledsgrp {
+			fsl,pins = <
+			SC_P_ESAI0_FST_LSIO_GPIO0_IO01		0x06000021
+			SC_P_ESAI0_TX0_LSIO_GPIO0_IO04		0x06000021
+			SC_P_SAI0_TXC_LSIO_GPIO0_IO26		0x06000021
+			SC_P_SAI1_RXD_LSIO_GPIO0_IO29		0x06000021
+			SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17	0x06000021
+			SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18	0x06000021
+			SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17	0x06000021
+			SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18	0x06000021
+			SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19	0x06000021
+			SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000021
+			SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x06000021
+			SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x06000021
+			SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000021
+			>;
+		};
+
+		pinctrl_lpi2c0: lpi2c0grp {
+			fsl,pins = <
+			SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL	0x0C000020
+			SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA	0x0C000020
+			>;
+		};
+
+		pinctrl_lpi2c1: lpi2c1grp {
+			fsl,pins = <
+			SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL	0x0C000020
+			SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA	0x0C000020
+			>;
+		};
+
+		pinctrl_lpuart2: lpuart2grp {
+			fsl,pins = <
+				SC_P_UART2_RX_ADMA_UART2_RX	0x06000020
+				SC_P_UART2_TX_ADMA_UART2_TX	0x06000020
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000041
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+				SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29	0x06000021
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK	0x06000041
+				SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
+				SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B	0x06000021
+				//SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x06000021
+				SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x06000021
+			>;
+		};
+
+		pinctrl_fec2: fec2grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0
+				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD		0x000514a0
+
+				SC_P_ENET0_MDC_CONN_ENET1_MDC                   0x00000060
+				SC_P_ENET0_MDIO_CONN_ENET1_MDIO                 0x00000060
+
+				SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN            0x00000060
+				SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0            0x00000060
+				SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1        0x00000060
+				SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER        0x00000060
+				SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL          0x00000060
+				SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0        0x00000060
+				SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1        0x00000060
+				SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL         0x00000060	/* ERST: Reset pin */
+			>;
+		};
+	};
+};
+
+&i2c0 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c0>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c1>;
+	status = "okay";
+};
+
+&lpuart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart2>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	clock-frequency=<52000000>;
+	no-1-8-v;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&fec1 {
+	status ="disabled";
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec2>;
+	phy-mode = "rmii";
+
+	phy-handle = <&ethphy1>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+	};
+};
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
new file mode 100644
index 0000000000..fb4f7f6f9d
--- /dev/null
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+/ {
+	chosen {
+		u-boot,dm-spl;
+	};
+};
+
+&lpuart1 { /* console */
+	u-boot,dm-spl;
+};
+
+&semc {
+	bank1: bank@0 {
+		u-boot,dm-spl;
+	};
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+
+	imxrt1050-evk {
+		u-boot,dm-spl;
+		pinctrl_lpuart1: lpuart1grp {
+			u-boot,dm-spl;
+		};
+
+		pinctrl_semc: semcgrp {
+			u-boot,dm-spl;
+		};
+
+		pinctrl_usdhc0: usdhc0grp {
+			u-boot,dm-spl;
+		};
+	};
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
new file mode 100644
index 0000000000..56b75986e2
--- /dev/null
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+/dts-v1/;
+#include "imxrt1050.dtsi"
+#include "imxrt1050-evk-u-boot.dtsi"
+#include <dt-bindings/pinctrl/pins-imxrt1050.h>
+
+/ {
+	model = "NXP IMXRT1050-evk board";
+	compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
+
+	chosen {
+		bootargs = "root=/dev/ram";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		reg = <0x80000000 0x2000000>;
+	};
+};
+
+&lpuart1 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart1>;
+	status = "okay";
+};
+
+&semc {
+	/*
+	 * Memory configuration from sdram datasheet IS42S16160J-6BLI
+	 */
+	fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
+				MUX_CSX0_SDRAM_CS1
+				0
+				0
+				0
+				0>;
+	fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
+					BL_8
+					COL_9BITS
+					CL_3>;
+	fsl,sdram-timing = /bits/ 8 <0x2
+				     0x2
+				     0x9
+				     0x1
+				     0x5
+				     0x6
+
+				     0x20
+				     0x09
+				     0x01
+				     0x00
+
+				     0x04
+				     0x0A
+				     0x21
+				     0x50>;
+
+	bank1: bank@0 {
+		fsl,base-address = <0x80000000>;
+		fsl,memory-size = <MEM_SIZE_32M>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart1>;
+
+	imxrt1050-evk {
+		pinctrl_lpuart1: lpuart1grp {
+			fsl,pins = <
+				MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
+					0xf1
+				MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
+					0xf1
+			>;
+		};
+
+		pinctrl_semc: semcgrp {
+			fsl,pins = <
+				MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
+					0xf1	/* SEMC_D0 */
+				MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
+					0xf1	/* SEMC_D1 */
+				MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
+					0xf1	/* SEMC_D2 */
+				MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
+					0xf1	/* SEMC_D3 */
+				MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
+					0xf1	/* SEMC_D4 */
+				MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
+					0xf1	/* SEMC_D5 */
+				MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
+					0xf1	/* SEMC_D6 */
+				MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
+					0xf1	/* SEMC_D7 */
+				MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
+					0xf1	/* SEMC_DM0 */
+				MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
+					0xf1	/* SEMC_A0 */
+				MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
+					0xf1	/* SEMC_A1 */
+				MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
+					0xf1	/* SEMC_A2 */
+				MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
+					0xf1	/* SEMC_A3 */
+				MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
+					0xf1	/* SEMC_A4 */
+				MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
+					0xf1	/* SEMC_A5 */
+				MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
+					0xf1	/* SEMC_A6 */
+				MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
+					0xf1	/* SEMC_A7 */
+				MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
+					0xf1	/* SEMC_A8 */
+				MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
+					0xf1	/* SEMC_A9 */
+				MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
+					0xf1	/* SEMC_A11 */
+				MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
+					0xf1	/* SEMC_A12 */
+				MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
+					0xf1	/* SEMC_BA0 */
+				MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
+					0xf1	/* SEMC_BA1 */
+				MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
+					0xf1	/* SEMC_A10 */
+				MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
+					0xf1	/* SEMC_CAS */
+				MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
+					0xf1	/* SEMC_RAS */
+				MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
+					0xf1	/* SEMC_CLK */
+				MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
+					0xf1	/* SEMC_CKE */
+				MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
+					0xf1	/* SEMC_WE */
+				MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
+					0xf1	/* SEMC_CS0 */
+				MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
+					0xf1	/* SEMC_D8 */
+				MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
+					0xf1	/* SEMC_D9 */
+				MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
+					0xf1	/* SEMC_D10 */
+				MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
+					0xf1	/* SEMC_D11 */
+				MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
+					0xf1	/* SEMC_D12 */
+				MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
+					0xf1	/* SEMC_D13 */
+				MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
+					0xf1	/* SEMC_D14 */
+				MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
+					0xf1	/* SEMC_D15 */
+				MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
+					0xf1	/* SEMC_DM1 */
+				MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
+					(IMX_PAD_SION | 0xf1)	/* SEMC_DQS */
+			>;
+		};
+
+		pinctrl_usdhc0: usdhc0grp {
+			fsl,pins = <
+				MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
+					0x1B000
+				MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
+					0xB069
+				MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD
+					0x17061
+				MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK
+					0x17061
+				MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
+					0x17061
+				MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
+					0x17061
+				MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
+					0x17061
+				MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
+					0x17061
+			>;
+		};
+	};
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc0>;
+	pinctrl-1 = <&pinctrl_usdhc0>;
+	pinctrl-2 = <&pinctrl_usdhc0>;
+	pinctrl-3 = <&pinctrl_usdhc0>;
+	status = "okay";
+
+	cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
new file mode 100644
index 0000000000..b1d98e6feb
--- /dev/null
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include "skeleton.dtsi"
+#include "armv7-m.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/imxrt1050-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/memory/imxrt-sdram.h>
+
+/ {
+	aliases {
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		mmc0 = &usdhc1;
+		serial0 = &lpuart1;
+	};
+
+	clocks {
+		u-boot,dm-spl;
+
+		osc {
+			u-boot,dm-spl;
+			compatible = "fsl,imx-osc", "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <24000000>;
+		};
+	};
+
+	soc {
+		u-boot,dm-spl;
+
+		semc: semc@402f0000 {
+			u-boot,dm-spl;
+			compatible = "fsl,imxrt-semc";
+			reg = <0x402f0000 0x4000>;
+			clocks = <&clks IMXRT1050_CLK_SEMC>;
+			pinctrl-0 = <&pinctrl_semc>;
+			pinctrl-names = "default";
+			status = "okay";
+		};
+
+		lpuart1: serial@40184000 {
+			compatible = "fsl,imxrt-lpuart";
+			reg = <0x40184000 0x4000>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks IMXRT1050_CLK_LPUART1>;
+			clock-names = "per";
+			status = "disabled";
+		};
+
+		iomuxc: iomuxc@401f8000 {
+			compatible = "fsl,imxrt-iomuxc";
+			reg = <0x401f8000 0x4000>;
+			fsl,mux_mask = <0x7>;
+		};
+
+		clks: ccm@400fc000 {
+			u-boot,dm-spl;
+			compatible = "fsl,imxrt1050-ccm";
+			reg = <0x400fc000 0x4000>;
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			#clock-cells = <1>;
+		};
+
+		usdhc1: usdhc@402c0000 {
+			u-boot,dm-spl;
+			compatible = "fsl,imxrt-usdhc";
+			reg = <0x402c0000 0x10000>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks IMXRT1050_CLK_USDHC1>;
+			clock-names = "per";
+			bus-width = <4>;
+			fsl,tuning-start-tap = <20>;
+			fsl,tuning-step= <2>;
+			status = "disabled";
+		};
+
+		gpio1: gpio@401b8000 {
+			u-boot,dm-spl;
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x401b8000 0x4000>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio2: gpio@401bc000 {
+			u-boot,dm-spl;
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x401bc000 0x4000>;
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio3: gpio@401c0000 {
+			u-boot,dm-spl;
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x401c0000 0x4000>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio4: gpio@401c4000 {
+			u-boot,dm-spl;
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x401c4000 0x4000>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio5: gpio@400c0000 {
+			u-boot,dm-spl;
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x400c0000 0x4000>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
diff --git a/arch/arm/include/asm/arch-imxrt/clock.h b/arch/arm/include/asm/arch-imxrt/clock.h
new file mode 100644
index 0000000000..7409028b9a
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/clock.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-imxrt/gpio.h b/arch/arm/include/asm/arch-imxrt/gpio.h
new file mode 100644
index 0000000000..da31a7438a
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/gpio.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+/* GPIO registers */
+struct gpio_regs {
+	u32 gpio_dr;	/* data */
+	u32 gpio_dir;	/* direction */
+	u32 gpio_psr;	/* pad satus */
+};
+#endif
+
+#endif /* __ASM_ARCH_GPIO_H__ */
diff --git a/arch/arm/include/asm/arch-imxrt/imx-regs.h b/arch/arm/include/asm/arch-imxrt/imx-regs.h
new file mode 100644
index 0000000000..4f1d439f6f
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/imx-regs.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright(C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __ASM_ARCH_IMX_REGS_H__
+#define __ASM_ARCH_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#define GPIO1_BASE_ADDR		0x401B8000
+#define GPIO2_BASE_ADDR		0x401BC000
+#define GPIO3_BASE_ADDR		0x401C0000
+#define GPIO4_BASE_ADDR		0x401C4000
+#define GPIO5_BASE_ADDR		0x400C0000
+
+#define ANATOP_BASE_ADDR	0x400d8000
+
+#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-imxrt/imxrt.h b/arch/arm/include/asm/arch-imxrt/imxrt.h
new file mode 100644
index 0000000000..1cb2c57d31
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/imxrt.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef _ASM_ARCH_IMXRT_H
+#define _ASM_ARCH_IMXRT_H
+
+#endif /* _ASM_ARCH_IMXRT_H */
+
diff --git a/arch/arm/include/asm/arch-imxrt/sys_proto.h b/arch/arm/include/asm/arch-imxrt/sys_proto.h
new file mode 100644
index 0000000000..eb878e672e
--- /dev/null
+++ b/arch/arm/include/asm/arch-imxrt/sys_proto.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 NXP
+ */
+
+#ifndef _ASM_ARCH_SYS_PROTO_H
+#define _ASM_ARCH_SYS_PROTO_H
+
+#include <asm/mach-imx/sys_proto.h>
+
+#endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index e14713c5c4..a70d51b5cf 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -27,7 +27,7 @@ endif
 obj-$(CONFIG_GPT_TIMER) += timer.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imxrt))
 obj-y	+= misc.o
 obj-$(CONFIG_SPL_BUILD)	+= spl.o
 endif
@@ -226,5 +226,6 @@ obj-$(CONFIG_MX7) += mx7/
 obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
 obj-$(CONFIG_IMX8M) += imx8m/
 obj-$(CONFIG_ARCH_IMX8) += imx8/
+obj-$(CONFIG_ARCH_IMXRT) += imxrt/
 
 obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index cdb78afacf..5827ab334f 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -55,6 +55,16 @@ config TARGET_COLIBRI_IMX8X
 	select BOARD_LATE_INIT
 	select IMX8QXP
 
+config TARGET_DENEB
+	bool "Support i.MX8QXP Capricorn Deneb board"
+	select BOARD_LATE_INIT
+	select IMX8QXP
+
+config TARGET_GIEDI
+	bool "Support i.MX8QXP Capricorn Giedi board"
+	select BOARD_LATE_INIT
+	select IMX8QXP
+
 config TARGET_IMX8QM_MEK
 	bool "Support i.MX8QM MEK board"
 	select BOARD_LATE_INIT
@@ -78,5 +88,6 @@ source "board/freescale/imx8qxp_mek/Kconfig"
 source "board/advantech/imx8qm_rom7720_a1/Kconfig"
 source "board/toradex/apalis-imx8/Kconfig"
 source "board/toradex/colibri-imx8x/Kconfig"
+source "board/siemens/capricorn/Kconfig"
 
 endif
diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig
new file mode 100644
index 0000000000..e3aff11d48
--- /dev/null
+++ b/arch/arm/mach-imx/imxrt/Kconfig
@@ -0,0 +1,25 @@
+if ARCH_IMXRT
+
+config IMXRT
+	bool
+
+config IMXRT1050
+	bool
+	select IMXRT
+
+config SYS_SOC
+	default "imxrt"
+
+choice
+	prompt "NXP i.MXRT board select"
+	optional
+
+config TARGET_IMXRT1050_EVK
+	bool "Support imxrt1050 EVK board"
+	select IMXRT1050
+
+endchoice
+
+source "board/freescale/imxrt1050-evk/Kconfig"
+
+endif
diff --git a/arch/arm/mach-imx/imxrt/Makefile b/arch/arm/mach-imx/imxrt/Makefile
new file mode 100644
index 0000000000..9621a8335a
--- /dev/null
+++ b/arch/arm/mach-imx/imxrt/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019
+# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+#
+
+obj-y	:= soc.o
diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c
new file mode 100644
index 0000000000..e1eea23035
--- /dev/null
+++ b/arch/arm/mach-imx/imxrt/soc.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/armv7_mpu.h>
+
+int arch_cpu_init(void)
+{
+	int i;
+
+	struct mpu_region_config imxrt1050_region_config[] = {
+		{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
+		  STRONG_ORDER, REGION_4GB },
+		{ PHYS_SDRAM, REGION_1, XN_DIS, PRIV_RW_USR_RW,
+		  O_I_WB_RD_WR_ALLOC, (ffs(PHYS_SDRAM_SIZE) - 2) },
+		{ DMAMEM_BASE,
+		  REGION_2, XN_DIS, PRIV_RW_USR_RW,
+		  STRONG_ORDER, (ffs(DMAMEM_SZ_ALL) - 2) },
+	};
+
+	/*
+	 * Configure the memory protection unit (MPU) to allow full access to
+	 * the whole 4GB address space.
+	 */
+	disable_mpu();
+	for (i = 0; i < ARRAY_SIZE(imxrt1050_region_config); i++)
+		mpu_config(&imxrt1050_region_config[i]);
+	enable_mpu();
+
+	return 0;
+}