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authorYe Li <ye.li@nxp.com>2020-05-04 22:08:54 +0800
committerStefano Babic <sbabic@denx.de>2020-05-10 20:55:20 +0200
commitff99041b3b6dccc1649d0c8512303a5240fb8785 (patch)
tree12a466b66e1940a5cc7c82f67237a814762e1299 /arch
parent29f40c07e7a649c6fc44a3a44449dce1ee733816 (diff)
mxs_nand: Add support for i.MX8M
Update the gpmi/apbh_dma/bch drivers and relevant registers for i.MX8M. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/mach-imx/dma.h2
-rw-r--r--arch/arm/include/asm/mach-imx/regs-apbh.h6
-rw-r--r--arch/arm/include/asm/mach-imx/regs-bch.h4
3 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/include/asm/mach-imx/dma.h b/arch/arm/include/asm/mach-imx/dma.h
index ca70731b9e..cb73aaeeb5 100644
--- a/arch/arm/include/asm/mach-imx/dma.h
+++ b/arch/arm/include/asm/mach-imx/dma.h
@@ -53,7 +53,7 @@ enum {
MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
MXS_MAX_DMA_CHANNELS,
};
-#elif defined(CONFIG_MX6) || defined(CONFIG_MX7)
+#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
enum {
MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
diff --git a/arch/arm/include/asm/mach-imx/regs-apbh.h b/arch/arm/include/asm/mach-imx/regs-apbh.h
index d7baf13343..d68953efd2 100644
--- a/arch/arm/include/asm/mach-imx/regs-apbh.h
+++ b/arch/arm/include/asm/mach-imx/regs-apbh.h
@@ -95,7 +95,7 @@ struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_version)
};
-#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_ctrl0)
mxs_reg_32(hw_apbh_ctrl1)
@@ -274,7 +274,7 @@ struct mxs_apbh_regs {
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
-#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
@@ -390,7 +390,7 @@ struct mxs_apbh_regs {
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
#endif
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
#endif
diff --git a/arch/arm/include/asm/mach-imx/regs-bch.h b/arch/arm/include/asm/mach-imx/regs-bch.h
index 3c1abb7221..4b99edbb3d 100644
--- a/arch/arm/include/asm/mach-imx/regs-bch.h
+++ b/arch/arm/include/asm/mach-imx/regs-bch.h
@@ -127,7 +127,7 @@ struct mxs_bch_regs {
#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
#else
@@ -158,7 +158,7 @@ struct mxs_bch_regs {
#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
#else