Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mips

- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
- mtmips: add new drivers for clock, reset-controller and pinctrl
- mtmips: add support for high speed UART
- mtmips: update/enhance drivers for SPI and ethernet
- mtmips: add support for MMC

13 files changed, 367 insertions, 25 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e3e7945567..eb1f67dccc 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -76,12 +76,18 @@ config ARCH_BMIPS
 
 config ARCH_MTMIPS
 	bool "Support MediaTek MIPS platforms"
+	select CLK
 	imply CMD_DM
 	select DISPLAY_CPUINFO
 	select DM
 	imply DM_ETH
 	imply DM_GPIO
+	select DM_RESET
 	select DM_SERIAL
+	select PINCTRL
+	select PINMUX
+	select PINCONF
+	select RESET_MTMIPS
 	imply DM_SPI
 	imply DM_SPI_FLASH
 	select LAST_STAGE_INIT
@@ -408,9 +414,17 @@ config SYS_ICACHE_LINE_SIZE
 	help
 	  The size of L1 Icache lines, if known at compile time.
 
+config SYS_SCACHE_LINE_SIZE
+	int
+	default 0
+	help
+	  The size of L2 cache lines, if known at compile time.
+
+
 config SYS_CACHE_SIZE_AUTO
 	def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
-		SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
+		SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
+		SYS_SCACHE_LINE_SIZE = 0
 	help
 	  Select this (or let it be auto-selected by not defining any cache
 	  sizes) in order to allow U-Boot to automatically detect the sizes
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index e2de1da147..c9d75596f2 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -10,6 +10,7 @@ dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
 dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
+dtb-$(CONFIG_BOARD_BROADCOM_BCM968380GERG) += brcm,bcm968380gerg.dtb
 dtb-$(CONFIG_BOARD_COMTREND_AR5315U) += comtrend,ar-5315u.dtb
 dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb
 dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
@@ -19,10 +20,9 @@ dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
 dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
 dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
 dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
+dtb-$(CONFIG_BOARD_SFR_NB4_SER) += sfr,nb4-ser.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
 dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
-dtb-$(CONFIG_SOC_BMIPS_BCM6358) += sfr,nb4-ser.dtb
-dtb-$(CONFIG_SOC_BMIPS_BCM6838) += brcm,bcm968380gerg.dtb
 dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
 dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
 dtb-$(CONFIG_SOC_JR2) += jr2_pcb110.dtb jr2_pcb111.dtb serval2_pcb112.dtb
diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi
index f8a72ef535..5294242529 100644
--- a/arch/mips/dts/brcm,bcm63268.dtsi
+++ b/arch/mips/dts/brcm,bcm63268.dtsi
@@ -141,6 +141,24 @@
 			status = "disabled";
 		};
 
+		nand: nand-controller@10000200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,nand-bcm6368",
+				     "brcm,brcmnand-v4.0",
+				     "brcm,brcmnand";
+			reg-names = "nand",
+				    "nand-cache",
+				    "nand-int-base";
+			reg = <0x10000200 0x180>,
+			      <0x10000600 0x200>,
+			      <0x100000b0 0x10>;
+			clocks = <&periph_clk BCM63268_CLK_NAND>;
+			clock-names = "nand";
+
+			status = "disabled";
+		};
+
 		periph_pwr: power-controller@1000184c {
 			compatible = "brcm,bcm6328-power-domain";
 			reg = <0x1000184c 0x4>;
diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi
index 50beed4171..350c0e903b 100644
--- a/arch/mips/dts/brcm,bcm6328.dtsi
+++ b/arch/mips/dts/brcm,bcm6328.dtsi
@@ -124,6 +124,22 @@
 			status = "disabled";
 		};
 
+		nand: nand-controller@10000200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,nand-bcm6368",
+				     "brcm,brcmnand-v2.2",
+				     "brcm,brcmnand";
+			reg-names = "nand",
+				    "nand-cache",
+				    "nand-int-base";
+			reg = <0x10000200 0x180>,
+			      <0x10000400 0x200>,
+			      <0x100000b0 0x10>;
+
+			status = "disabled";
+		};
+
 		leds: led-controller@10000800 {
 			compatible = "brcm,bcm6328-leds";
 			reg = <0x10000800 0x24>;
diff --git a/arch/mips/dts/brcm,bcm6362.dtsi b/arch/mips/dts/brcm,bcm6362.dtsi
index c77b80a4cc..71598f97b3 100644
--- a/arch/mips/dts/brcm,bcm6362.dtsi
+++ b/arch/mips/dts/brcm,bcm6362.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
  */
 
 #include <dt-bindings/clock/bcm6362-clock.h>
@@ -135,6 +135,24 @@
 			status = "disabled";
 		};
 
+		nand: nand-controller@10000200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,nand-bcm6368",
+				     "brcm,brcmnand-v2.2",
+				     "brcm,brcmnand";
+			reg-names = "nand",
+				    "nand-cache",
+				    "nand-int-base";
+			reg = <0x10000200 0x180>,
+			      <0x10000600 0x200>,
+			      <0x100000b0 0x10>;
+			clocks = <&periph_clk BCM6362_CLK_NAND>;
+			clock-names = "nand";
+
+			status = "disabled";
+		};
+
 		lsspi: spi@10000800 {
 			compatible = "brcm,bcm6358-spi";
 			reg = <0x10000800 0x70c>;
diff --git a/arch/mips/dts/brcm,bcm6368.dtsi b/arch/mips/dts/brcm,bcm6368.dtsi
index 89590d6ff9..69be65056e 100644
--- a/arch/mips/dts/brcm,bcm6368.dtsi
+++ b/arch/mips/dts/brcm,bcm6368.dtsi
@@ -146,6 +146,24 @@
 			status = "disabled";
 		};
 
+		nand: nand-controller@10000200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,nand-bcm6368",
+				     "brcm,brcmnand-v2.1",
+				     "brcm,brcmnand";
+			reg-names = "nand",
+				    "nand-cache",
+				    "nand-int-base";
+			reg = <0x10000200 0x180>,
+			      <0x10000600 0x200>,
+			      <0x100000b0 0x10>;
+			clocks = <&periph_clk BCM6368_CLK_NAND>;
+			clock-names = "nand";
+
+			status = "disabled";
+		};
+
 		spi: spi@10000800 {
 			compatible = "brcm,bcm6358-spi";
 			reg = <0x10000800 0x70c>;
diff --git a/arch/mips/dts/comtrend,vr-3032u.dts b/arch/mips/dts/comtrend,vr-3032u.dts
index 512cb52de3..110119b507 100644
--- a/arch/mips/dts/comtrend,vr-3032u.dts
+++ b/arch/mips/dts/comtrend,vr-3032u.dts
@@ -99,6 +99,19 @@
 	};
 };
 
+&nand {
+	status = "okay";
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+		nand-ecc-strength = <15>;
+		nand-ecc-step-size = <512>;
+		nand-on-flash-bbt;
+		brcm,nand-oob-sector-size = <64>;
+	};
+};
+
 &ohci {
 	status = "okay";
 };
diff --git a/arch/mips/dts/gardena-smart-gateway-mt7688.dts b/arch/mips/dts/gardena-smart-gateway-mt7688.dts
index eedde89dfd..b7b5a24058 100644
--- a/arch/mips/dts/gardena-smart-gateway-mt7688.dts
+++ b/arch/mips/dts/gardena-smart-gateway-mt7688.dts
@@ -85,15 +85,26 @@
 	};
 };
 
+&pinctrl {
+	state_default: pin_state {
+		p0led {
+			groups = "p0led_a";
+			function = "led";
+		};
+	};
+};
+
 &uart0 {
 	status = "okay";
-	clock-frequency = <40000000>;
 };
 
 &spi0 {
 	status = "okay";
 	num-cs = <2>;
 
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_dual_pins>;
+
 	spi-flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -110,3 +121,9 @@
 		reg = <1>;
 	};
 };
+
+&eth {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ephy_iot_mode>;
+	mediatek,poll-link-phy = <0>;
+};
diff --git a/arch/mips/dts/linkit-smart-7688.dts b/arch/mips/dts/linkit-smart-7688.dts
index bb10402174..f154aae190 100644
--- a/arch/mips/dts/linkit-smart-7688.dts
+++ b/arch/mips/dts/linkit-smart-7688.dts
@@ -26,9 +26,17 @@
 	};
 };
 
+&pinctrl {
+	state_default: pin_state {
+		p0led {
+			groups = "p0led_a";
+			function = "led";
+		};
+	};
+};
+
 &uart2 {
 	status = "okay";
-	clock-frequency = <40000000>;
 };
 
 &spi0 {
@@ -43,3 +51,9 @@
 		reg = <0>;
 	};
 };
+
+&eth {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ephy_iot_mode>;
+	mediatek,poll-link-phy = <0>;
+};
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi
index 1e7d0a6ec5..76a80c8952 100644
--- a/arch/mips/dts/mt7628a.dtsi
+++ b/arch/mips/dts/mt7628a.dtsi
@@ -1,4 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mt7628-clk.h>
+#include <dt-bindings/reset/mt7628-reset.h>
 
 / {
 	#address-cells = <1>;
@@ -16,11 +18,6 @@
 		};
 	};
 
-	resetc: reset-controller {
-		compatible = "ralink,rt2880-reset";
-		#reset-cells = <1>;
-	};
-
 	cpuintc: interrupt-controller {
 		#address-cells = <0>;
 		#interrupt-cells = <1>;
@@ -28,6 +25,14 @@
 		compatible = "mti,cpu-interrupt-controller";
 	};
 
+	clk48m: clk48m@0 {
+		compatible = "fixed-clock";
+
+		clock-frequency = <48000000>;
+
+		#clock-cells = <0>;
+	};
+
 	palmbus@10000000 {
 		compatible = "palmbus", "simple-bus";
 		reg = <0x10000000 0x200000>;
@@ -48,11 +53,175 @@
 			mask = <0x1>;
 		};
 
+		clkctrl: clkctrl@0x2c {
+			reg = <0x2c 0x8>, <0x10 0x4>;
+			reg-names = "syscfg0", "clkcfg";
+			compatible = "mediatek,mt7628-clk";
+			#clock-cells = <1>;
+			u-boot,dm-pre-reloc;
+		};
+
+		rstctrl: rstctrl@0x34 {
+			reg = <0x34 0x4>;
+			compatible = "mediatek,mtmips-reset";
+			#reset-cells = <1>;
+		};
+
+		pinctrl: pinctrl@60 {
+			compatible = "mediatek,mt7628-pinctrl";
+			reg = <0x3c 0x2c>, <0x1300 0x100>;
+			reg-names = "gpiomode", "padconf";
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&state_default>;
+
+			state_default: pin_state {
+			};
+
+			spi_single_pins: spi_single_pins {
+				groups = "spi";
+				function = "spi";
+			};
+
+			spi_dual_pins: spi_dual_pins {
+				spi_master_pins {
+					groups = "spi";
+					function = "spi";
+				};
+
+				spi_cs1_pin {
+					groups = "spi cs1";
+					function = "spi cs1";
+				};
+			};
+
+			uart0_pins: uart0_pins {
+				groups = "uart0";
+				function = "uart0";
+			};
+
+			uart1_pins: uart1_pins {
+				groups = "uart1";
+				function = "uart1";
+			};
+
+			uart2_pins: uart2_pins {
+				groups = "uart2";
+				function = "uart2";
+			};
+
+			i2c_pins: i2c_pins {
+				groups = "i2c";
+				function = "i2c";
+			};
+
+			ephy_iot_mode: ephy_iot_mode {
+				ephy4_1_dis {
+					groups = "ephy4_1_pad";
+					function = "digital";
+				};
+
+				ephy0_en {
+					groups = "ephy0";
+					function = "enable";
+				};
+			};
+
+			ephy_router_mode: ephy_router_mode {
+				ephy4_1_en {
+					groups = "ephy4_1_pad";
+					function = "analog";
+				};
+
+				ephy0_en {
+					groups = "ephy0";
+					function = "enable";
+				};
+			};
+
+			sd_iot_mode: sd_iot_mode {
+				ephy4_1_dis {
+					groups = "ephy4_1_pad";
+					function = "digital";
+				};
+
+				sdxc_en {
+					groups = "sdmode";
+					function = "sdxc";
+				};
+
+				sdxc_iot_mode {
+					groups = "sd router";
+					function = "iot";
+				};
+
+				sd_clk_pad {
+					pins = "sd_clk";
+					drive-strength-4g = <8>;
+				};
+			};
+
+			sd_router_mode: sd_router_mode {
+				sdxc_router_mode {
+					groups = "sd router";
+					function = "router";
+				};
+
+				sdxc_map_pins {
+					groups = "gpio0", "i2s", "sdmode", \
+						 "i2c", "uart1";
+					function = "gpio";
+				};
+
+				sd_clk_pad {
+					pins = "gpio0";
+					drive-strength-28 = <8>;
+				};
+			};
+
+			emmc_iot_8bit_mode: emmc_iot_8bit_mode {
+				ephy4_1_dis {
+					groups = "ephy4_1_pad";
+					function = "digital";
+				};
+
+				emmc_en {
+					groups = "sdmode";
+					function = "sdxc";
+				};
+
+				emmc_iot_mode {
+					groups = "sd router";
+					function = "iot";
+				};
+
+				emmc_d4_d5 {
+					groups = "uart2";
+					function = "sdxc d5 d4";
+				};
+
+				emmc_d6 {
+					groups = "pwm1";
+					function = "sdxc d6";
+				};
+
+				emmc_d7 {
+					groups = "pwm0";
+					function = "sdxc d7";
+				};
+
+				sd_clk_pad {
+					pins = "sd_clk";
+					drive-strength-4g = <8>;
+				};
+			};
+		};
+
 		watchdog: watchdog@100 {
 			compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt";
 			reg = <0x100 0x30>;
 
-			resets = <&resetc 8>;
+			resets = <&rstctrl MT7628_TIMER_RST>;
 			reset-names = "wdt";
 
 			interrupt-parent = <&intc>;
@@ -66,7 +235,7 @@
 			interrupt-controller;
 			#interrupt-cells = <1>;
 
-			resets = <&resetc 9>;
+			resets = <&rstctrl MT7628_INT_RST>;
 			reset-names = "intc";
 
 			interrupt-parent = <&cpuintc>;
@@ -89,6 +258,9 @@
 			compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
 			reg = <0x600 0x100>;
 
+			resets = <&rstctrl MT7628_PIO_RST>;
+			reset-names = "pio";
+
 			interrupt-parent = <&intc>;
 			interrupts = <6>;
 
@@ -117,17 +289,26 @@
 		spi0: spi@b00 {
 			compatible = "ralink,mt7621-spi";
 			reg = <0xb00 0x40>;
+
+			resets = <&rstctrl MT7628_SPI_RST>;
+			reset-names = "spi";
+
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			clock-frequency = <200000000>;
+			clocks = <&clkctrl CLK_SPI>;
 		};
 
 		uart0: uartlite@c00 {
-			compatible = "ns16550a";
+			compatible = "mediatek,hsuart", "ns16550a";
 			reg = <0xc00 0x100>;
 
-			resets = <&resetc 12>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart0_pins>;
+
+			clocks = <&clkctrl CLK_UART0>;
+
+			resets = <&rstctrl MT7628_UART0_RST>;
 			reset-names = "uart0";
 
 			interrupt-parent = <&intc>;
@@ -137,10 +318,15 @@
 		};
 
 		uart1: uart1@d00 {
-			compatible = "ns16550a";
+			compatible = "mediatek,hsuart", "ns16550a";
 			reg = <0xd00 0x100>;
 
-			resets = <&resetc 19>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart1_pins>;
+
+			clocks = <&clkctrl CLK_UART1>;
+
+			resets = <&rstctrl MT7628_UART1_RST>;
 			reset-names = "uart1";
 
 			interrupt-parent = <&intc>;
@@ -150,10 +336,15 @@
 		};
 
 		uart2: uart2@e00 {
-			compatible = "ns16550a";
+			compatible = "mediatek,hsuart", "ns16550a";
 			reg = <0xe00 0x100>;
 
-			resets = <&resetc 20>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart2_pins>;
+
+			clocks = <&clkctrl CLK_UART2>;
+
+			resets = <&rstctrl MT7628_UART2_RST>;
 			reset-names = "uart2";
 
 			interrupt-parent = <&intc>;
@@ -163,11 +354,14 @@
 		};
 	};
 
-	eth@10110000 {
+	eth: eth@10110000 {
 		compatible = "mediatek,mt7628-eth";
 		reg = <0x10100000 0x10000
 		       0x10110000 0x8000>;
 
+		resets = <&rstctrl MT7628_EPHY_RST>;
+		reset-names = "ephy";
+
 		syscon = <&sysc>;
 	};
 
@@ -178,8 +372,12 @@
 		#phy-cells = <0>;
 
 		ralink,sysctl = <&sysc>;
-		resets = <&resetc 22 &resetc 25>;
-		reset-names = "host", "device";
+
+		resets = <&rstctrl MT7628_UPHY_RST>;
+		reset-names = "phy";
+
+		clocks = <&clkctrl CLK_UPHY>;
+		clock-names = "cg";
 	};
 
 	ehci@101c0000 {
@@ -192,4 +390,18 @@
 		interrupt-parent = <&intc>;
 		interrupts = <18>;
 	};
+
+	mmc: mmc@10130000 {
+		compatible = "mediatek,mt7620-mmc";
+		reg = <0x10130000 0x4000>;
+		builtin-cd = <1>;
+		r_smpl = <1>;
+
+		clocks = <&clk48m>, <&clkctrl CLK_SDXC>;
+		clock-names = "source", "hclk";
+
+		resets = <&rstctrl MT7628_SDXC_RST>;
+
+		status = "disabled";
+	};
 };
diff --git a/arch/mips/dts/netgear,dgnd3700v2.dts b/arch/mips/dts/netgear,dgnd3700v2.dts
index 2b72491f0b..88fca647cd 100644
--- a/arch/mips/dts/netgear,dgnd3700v2.dts
+++ b/arch/mips/dts/netgear,dgnd3700v2.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
  */
 
 /dts-v1/;
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index d56fd1e0f4..0ddae30f2c 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -87,7 +87,7 @@ static inline unsigned long scache_line_size(void)
 #ifdef CONFIG_MIPS_L2_CACHE
 	return gd->arch.l2_line_size;
 #else
-	return 0;
+	return CONFIG_SYS_SCACHE_LINE_SIZE;
 #endif
 }
 
diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig
index 4af2d54528..c8dcf19c0d 100644
--- a/arch/mips/mach-mtmips/Kconfig
+++ b/arch/mips/mach-mtmips/Kconfig
@@ -13,6 +13,8 @@ choice
 config SOC_MT7628
 	bool "MT7628"
 	select MIPS_L1_CACHE_SHIFT_5
+	select PINCTRL_MT7628
+	select MTK_SERIAL
 	help
 	  This supports MediaTek MT7628/MT7688.