diff options
| author | Kevin Smith <kevin.smith@elecsyscorp.com> | 2015-10-23 17:53:19 +0000 |
|---|---|---|
| committer | Luka Perkov <luka.perkov@sartura.hr> | 2015-11-17 23:41:41 +0100 |
| commit | 544acb07ecebc096c9449e675481ba280311fb0b (patch) | |
| tree | 3e322a650976aa6972e69d84cf65e9b7e0664ae4 /board/Marvell/db-88f6820-gp | |
| parent | 3d4825446e4258192e1f2302d691a8c0c82a0975 (diff) | |
arm: mvebu: a38x: Remove unsupported topologies
A lot of extra configuration information was left over in the
Marvell serdes and DDR3 initialization code for boards that
U-boot does not support. Remove this extra config information,
and the concept of fixing up board topologies with information
loaded from an EEPROM. If this needs to be done, it should be
handled in the board file, not in core code.
Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Diffstat (limited to 'board/Marvell/db-88f6820-gp')
| -rw-r--r-- | board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c index 84ca55c7d5..384d002d5d 100644 --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -13,6 +13,7 @@ #include <asm/arch/soc.h> #include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h" +#include <../serdes/a38x/high_speed_env_spec.h> DECLARE_GLOBAL_DATA_PTR; @@ -55,6 +56,21 @@ static struct marvell_io_exp io_exp[] = { { 0x21, 3, 0xC0 } /* Output Data, register#1 */ }; +static struct serdes_map board_serdes_map[] = { + {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, + {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0} +}; + +int hws_board_topology_load(struct serdes_map *serdes_map_array) +{ + memcpy(serdes_map_array, board_serdes_map, sizeof(board_serdes_map)); + return 0; +} + /* * Define the DDR layout / topology here in the board file. This will * be used by the DDR3 init code in the SPL U-Boot version to configure |